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3028b04057
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1544 Commits

Author SHA1 Message Date
Evan Cheng
3028b04057 More efficient v2f64 shuffle using movlhps, movhlps, unpckhpd, and unpcklpd. 
llvm-svn: 27040
 2006-03-24 02:58:06 +00:00
Evan Cheng
184c4b937e A new entry 
llvm-svn: 27039
 2006-03-24 02:57:03 +00:00
Evan Cheng
68410804f0 Handle more shuffle cases with SHUFP* instructions. 
llvm-svn: 27024
 2006-03-24 01:18:28 +00:00
Evan Cheng
daa75ed684 Typo 
llvm-svn: 26997
 2006-03-23 20:26:04 +00:00
Jim Laskey
cec9c18c62 Add support to locate local variables in frames (early version.) 
llvm-svn: 26994
 2006-03-23 18:12:57 +00:00
Jim Laskey
f3cc740d75 Change interface to DwarfWriter. 
llvm-svn: 26991
 2006-03-23 18:09:44 +00:00
Chris Lattner
ec3f1b5cd1 Fix the encodings of these new instructions, hopefully fixing the JIT 
failures from last night

llvm-svn: 26981
 2006-03-23 16:13:50 +00:00
Evan Cheng
a6dc6e535d Following icc's lead: use movdqa to load / store 128-bit integer vectors 
llvm-svn: 26980
 2006-03-23 07:44:07 +00:00
Chris Lattner
89e0790edb Eliminate IntrinsicLowering from TargetMachine. 
Make the CBE and V9 backends create their own, since they're the only ones that use it.

llvm-svn: 26974
 2006-03-23 05:43:16 +00:00
Evan Cheng
c1fe87ea8b Add v4i32 <-> v4f32 bitconvert patterns. 
llvm-svn: 26969
 2006-03-23 02:36:37 +00:00
Evan Cheng
5f7cf963db Add 128-bit integer vector load and add (for testing). 
llvm-svn: 26967
 2006-03-23 01:57:24 +00:00
Nate Begeman
0ec15cd042 Add support for 8 bit immediates with 16/32 bit cmp instructions 
llvm-svn: 26966
 2006-03-23 01:29:48 +00:00
Evan Cheng
54215cd1ea Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.

llvm-svn: 26964
 2006-03-22 22:07:06 +00:00
Evan Cheng
56b67b2c4f SHUFP* are two address code. 
llvm-svn: 26959
 2006-03-22 20:08:18 +00:00
Evan Cheng
7cb4e14749 Some clean up. 
llvm-svn: 26957
 2006-03-22 19:22:18 +00:00
Evan Cheng
ae6a39ea92 - Supposely movlhps is faster / better than unpcklpd. 
- Don't forget pshufd is only available with sse2.

llvm-svn: 26956
 2006-03-22 19:16:21 +00:00
Evan Cheng
cff38e19c3 - Implement X86ISelLowering::isShuffleMaskLegal(). We currently only support 
splat and PSHUFD cases.
- Clean up shuffle / splat matching code.

llvm-svn: 26954
 2006-03-22 18:59:22 +00:00
Evan Cheng
f6dc0a7f5e - VECTOR_SHUFFLE of v4i32 / v4f32 with undef second vector always matches 
PSHUFD. We can make permutes entries which point to the undef pointing
  anything we want.
- Change some names to appease Chris.

llvm-svn: 26951
 2006-03-22 08:01:21 +00:00
Evan Cheng
25440d19b1 Fix PSHUF* and SHUF* jit code emission problems 
llvm-svn: 26949
 2006-03-22 07:10:28 +00:00
Chris Lattner
1554bf155e fix a warning 
llvm-svn: 26941
 2006-03-22 04:18:34 +00:00
Evan Cheng
7aac4350c7 Some splat and shuffle support. 
llvm-svn: 26940
 2006-03-22 02:53:00 +00:00
Evan Cheng
b6c46ed8c9 Add a couple more pseudo instructions. 
llvm-svn: 26939
 2006-03-22 02:52:03 +00:00
Evan Cheng
7c8d7bc4b3 Didn't mean to check this in. No MMX support yet. 
llvm-svn: 26933
 2006-03-21 23:04:23 +00:00
Evan Cheng
47dd756c72 - Use movaps to store 128-bit vector integers. 
- Each scalar to vector v8i16 and v16i8 is a any_extend followed by a movd.

llvm-svn: 26932
 2006-03-21 23:01:21 +00:00
Chris Lattner
31a93c7740 These targets don't support EXTRACT_VECTOR_ELT, though, in time, X86 will. 
llvm-svn: 26930
 2006-03-21 20:51:05 +00:00
Evan Cheng
a56ed39464 Combine 2 entries 
llvm-svn: 26921
 2006-03-21 07:18:26 +00:00
Evan Cheng
f8d8d45ff8 Add a note about x86 register coallescing 
llvm-svn: 26920
 2006-03-21 07:12:57 +00:00
Evan Cheng
6ec225863c - Remove scalar to vector pseudo ops. They are just wrong. 
- Handle FR32 to VR128:v4f32 and FR64 to VR128:v2f64 with aliases of MOVAPS
and MOVAPD. Mark them as move instructions and *hope* they will be deleted.

llvm-svn: 26919
 2006-03-21 07:09:35 +00:00
Evan Cheng
a4db61ddc1 x86 ISD::SCALAR_TO_VECTOR support. 
llvm-svn: 26911
 2006-03-21 00:33:35 +00:00
Evan Cheng
d90127aafd Junk unused vector register classes. 
llvm-svn: 26910
 2006-03-21 00:30:59 +00:00
Chris Lattner
09ede9ec9f Add a build_vector node 
llvm-svn: 26895
 2006-03-20 06:18:01 +00:00
Evan Cheng
c63d434203 Move a few things around. 
llvm-svn: 26893
 2006-03-20 06:04:52 +00:00
Chris Lattner
9a87d3e90d add a note with a testcase 
llvm-svn: 26877
 2006-03-19 22:27:41 +00:00
Evan Cheng
cc1e38c242 Vector undef's 
llvm-svn: 26870
 2006-03-19 09:38:54 +00:00
Evan Cheng
99327f9351 Turning on LSR by default 
llvm-svn: 26861
 2006-03-19 06:08:49 +00:00
Evan Cheng
98b79bf7ec Remember which tests are hurt by LSR. 
llvm-svn: 26860
 2006-03-19 06:08:11 +00:00
Chris Lattner
1bd0aaf2b8 rename these nodes 
llvm-svn: 26848
 2006-03-19 01:13:28 +00:00
Evan Cheng
8dd794ea70 Use the generic vector register classes VR64 / VR128 rather than V4F32, 
V8I16, etc.

llvm-svn: 26838
 2006-03-18 01:23:20 +00:00
Evan Cheng
f4774c9091 Darwin should use _setjmp/_longjmp instead of setjmp/longjmp. 
llvm-svn: 26833
 2006-03-17 20:31:41 +00:00
Evan Cheng
ee1a44d5d8 Move some pattern fragments to the right files. 
llvm-svn: 26831
 2006-03-17 19:55:52 +00:00
Chris Lattner
647503bccc Disable x86 fastcc from passing args in registers 
llvm-svn: 26824
 2006-03-17 17:27:47 +00:00
Chris Lattner
a71bc63ced Parameterize the number of integer arguments to pass in registers 
llvm-svn: 26818
 2006-03-17 05:10:20 +00:00
Evan Cheng
1f5cb60f28 Also fold MOV8r0, MOV16r0, MOV32r0 + store to MOV8mi, MOV16mi, and MOV32mi. 
llvm-svn: 26817
 2006-03-17 02:36:22 +00:00
Evan Cheng
fc79bdafbe Add some missing entries to X86RegisterInfo::foldMemoryOperand(). e.g. 
ADD32ri8.

llvm-svn: 26816
 2006-03-17 02:25:01 +00:00
Evan Cheng
d16fa97974 - Nuke 16-bit SBB instructions. We'll never use them. 
- Nuke a bogus comment.

llvm-svn: 26815
 2006-03-17 02:24:04 +00:00
Nate Begeman
42736d46b2 Remove BRTWOWAY* 
Make the PPC backend not dependent on BRTWOWAY_CC and make the branch
selector smarter about the code it generates, fixing a case in the
readme.

llvm-svn: 26814
 2006-03-17 01:40:33 +00:00
Evan Cheng
33055a8aba A new entry. 
llvm-svn: 26810
 2006-03-16 22:44:22 +00:00
Evan Cheng
0e1abe6e19 Bug fix: condition inverted. 
llvm-svn: 26804
 2006-03-16 22:02:48 +00:00
Evan Cheng
cad75d9f0c Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.

llvm-svn: 26802
 2006-03-16 21:47:42 +00:00
Evan Cheng
7ec94f2ff7 Added getTargetLowering() to TargetMachine. Refactored targets to support this. 
llvm-svn: 26742
 2006-03-13 23:20:37 +00:00