RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-01 08:23:21 +01:00
Code Issues Projects Releases Wiki Activity
81,522 Commits 4 Branches 5 Tags 704 MiB
304e4812bc
Commit Graph

231 Commits

Author SHA1 Message Date
Kevin Enderby
304e4812bc Fix ARM disassembly of VLD instructions with writebacks.  And add test a case 
for all opcodes handed by DecodeVLDInstruction() in ARMDisassembler.cpp .

llvm-svn: 154459
 2012-04-11 00:25:40 +00:00
Evan Cheng
12bfe1150d Fix a number of problems with ARM fused multiply add/subtract instructions. 
1. The new instruction itinerary entries are not properly described.
2. The asm parser can't handle vfms and vfnms.
3. There were no assembler, disassembler test cases.
4. HasNEON2 has the wrong assembler predicate.
rdar://10139676

llvm-svn: 154456
 2012-04-11 00:13:00 +00:00
Silviu Baranga
f376e00699 Added support for unpredictable ADC/SBC instructions on ARM, and also fixed some corner cases involving the PC register as an operand for these instructions. 
llvm-svn: 154101
 2012-04-05 16:19:29 +00:00
Silviu Baranga
1c2668f700 Added support for handling unpredictable arithmetic instructions on ARM. 
llvm-svn: 154100
 2012-04-05 16:13:15 +00:00
Silviu Baranga
77d372b45e Added fix in TableGen instruction decoder generation. The decoder now breaks for every leaf node. 
llvm-svn: 153874
 2012-04-02 15:20:39 +00:00
Eli Bendersky
3ef88c1833 Continue cleanup of LIT, getting rid of the remaining artifacts from dejagnu 
* Removed test/lib/llvm.exp - it is no longer needed 
* Deleted the dg.exp reading code from test/lit.cfg. There are no dg.exp files
  left in the test suite so this code is no longer required. test/lit.cfg is
  now much shorter and clearer 
* Removed a lot of duplicate code in lit.local.cfg files that need access to
  the root configuration, by adding a "root" attribute to the TestingConfig
  object. This attribute is dynamically computed to provide the same
  information as was previously provided by the custom getRoot functions. 
* Documented the config.root attribute in docs/CommandGuide/lit.pod

llvm-svn: 153408
 2012-03-25 09:02:19 +00:00
Silviu Baranga
d197baa066 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
llvm-svn: 153252
 2012-03-22 14:14:49 +00:00
Silviu Baranga
7bdfb9e34d Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
llvm-svn: 153251
 2012-03-22 13:24:43 +00:00
Silviu Baranga
c03971d4b1 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 
llvm-svn: 153250
 2012-03-22 13:14:39 +00:00
Kevin Enderby
e64335b34a Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .

llvm-svn: 153218
 2012-03-21 20:54:32 +00:00
Silviu Baranga
d20ed770e5 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
llvm-svn: 153089
 2012-03-20 15:54:56 +00:00
Kevin Enderby
64d11852dd Fix a bug in the ARM disassembly of the neon VLD2 all lanes instruction. 
llvm-svn: 152127
 2012-03-06 18:33:12 +00:00
Kevin Enderby
26dad6994b Change ARMInstPrinter::printPredicateOperand() so it will not abort if it 
runs into the undefined 15 condition code value.

llvm-svn: 151844
 2012-03-01 22:13:02 +00:00
Eli Bendersky
4afdeeb682 Replace all instances of dg.exp file with lit.local.cfg, since all tests are run with LIT now and now Dejagnu. dg.exp is no longer needed. 
Patch reviewed by Daniel Dunbar. It will be followed by additional cleanup patches.

llvm-svn: 150664
 2012-02-16 06:28:33 +00:00
James Molloy
85be8f7f88 Teach the MC and disassembler about SoftFail, and hook it up to UNPREDICTABLE on ARM. Wire this to tBLX in order to provide test coverage. 
llvm-svn: 150169
 2012-02-09 10:56:31 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Owen Anderson
35f049f1fb Fix an ambiguous decoding where we failed to properly decode VMOVv2f32 and VMOVv4f32. 
llvm-svn: 144683
 2011-11-15 19:55:00 +00:00
Jim Grosbach
4a2f107b04 ARM VLDR/VSTR instructions don't need a size suffix. 
Canonicallize on the non-suffixed form, but continue to accept assembly that
has any correctly sized type suffix.

llvm-svn: 144583
 2011-11-14 23:03:21 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr. 
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
 2011-11-07 21:00:59 +00:00
Owen Anderson
ac9fd95057 Fix the issue that r143552 was trying to address the _right_ way. One-register lists are legal on LDM/STM instructions, but we should not print the PUSH/POP aliases when they appear. This fixes round tripping on this instruction. 
llvm-svn: 143557
 2011-11-02 18:03:14 +00:00
Owen Anderson
0d69f6aa51 Fix disassembly of some VST1 instructions. 
llvm-svn: 143507
 2011-11-01 22:18:13 +00:00
Owen Anderson
d7700cb13f More not-crashing NEON disassembly updates for the vld refactoring. 
llvm-svn: 143351
 2011-10-31 17:17:32 +00:00
Owen Anderson
9e033c5b03 Fix illegal disassembly testcase. 
llvm-svn: 143231
 2011-10-28 21:45:09 +00:00
Owen Anderson
3dd6c949a5 Reapply r143202, with a manual decoding hook for SWP. This change inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. 
llvm-svn: 143208
 2011-10-28 18:02:13 +00:00
Owen Anderson
f22cd77ceb Add testcase for r143162. 
llvm-svn: 143163
 2011-10-27 22:54:14 +00:00
Owen Anderson
b0e09258e7 Fix a NEON disassembly case that was broken in the recent refactorings. As more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. 
llvm-svn: 142817
 2011-10-24 18:04:29 +00:00
Owen Anderson
2021ad2133 Revert r142618, r142622, and r142624, which were based on an incorrect reading of the ARMv7 docs. 
llvm-svn: 142626
 2011-10-20 22:23:58 +00:00
Owen Anderson
8067075218 Fix decoding tests for fixed MSR encodings. 
llvm-svn: 142624
 2011-10-20 22:01:48 +00:00
Jim Grosbach
422576b6e8 Thumb2 assembly parsing and encoding for LDC/STC. 
llvm-svn: 141811
 2011-10-12 20:54:17 +00:00
Jim Grosbach
313a74d565 Update test for r141704. 
llvm-svn: 141705
 2011-10-11 20:18:50 +00:00
James Molloy
c4fcff419c Check in a patch that has already been code reviewed by Owen that I'd forgotten to commit. 
Build on previous patches to successfully distinguish between an M-series and A/R-series MSR and MRS instruction. These take different mask names and have a *slightly* different opcode format.

Add decoder and disassembler tests.

Improvement on the previous patch - successfully distinguish between valid v6m and v7m masks (one is a subset of the other). The patch had to be edited slightly to apply to ToT.

llvm-svn: 140696
 2011-09-28 14:21:38 +00:00
Owen Anderson
bfb83aae27 Fix an incorrect decoder test. 
llvm-svn: 140579
 2011-09-26 23:08:34 +00:00
Owen Anderson
f9ff097fdd Fix incorrect disassembly test. 
llvm-svn: 140423
 2011-09-23 22:05:54 +00:00
Owen Anderson
53c6b08ad8 Post-index loads/stores in still need to print the post-indexed immediate, even if it's zero, to distinguish them from non-post-indexed instructions. 
llvm-svn: 140420
 2011-09-23 21:26:40 +00:00
Owen Anderson
071eb7580a Reapply r140412 (Thumb2 reg-reg loads cannot target SP or PC), with invalid testcases updated. 
llvm-svn: 140415
 2011-09-23 21:07:25 +00:00
Owen Anderson
7b134fe54c Print out immediate offset versions of PC-relative load/store instructions as [pc, #123] rather than simply #123. 
llvm-svn: 140283
 2011-09-21 23:44:46 +00:00
Owen Anderson
4177cfc809 Port over more Thumb2 encoding tests to decoding tests. 
llvm-svn: 140152
 2011-09-20 17:44:48 +00:00
Owen Anderson
b843f3625d Handle STRT (and friends) like LDRT (and friends) for decoding purposes. Port over additional encoding tests to decoding tests. 
llvm-svn: 140032
 2011-09-19 18:07:10 +00:00
Owen Anderson
df512e9961 Add a testcase for another corner-case decoding. 
llvm-svn: 139970
 2011-09-16 23:15:29 +00:00
Owen Anderson
eae0eee720 Fix disassembly of Thumb2 BFI instructions with bit range of [0, 32). 
llvm-svn: 139964
 2011-09-16 22:29:48 +00:00
Owen Anderson
3a487c8c9b Add fixed bits to correctly distinguish Thumb2 SSAT/SSAT16's. 
llvm-svn: 139958
 2011-09-16 22:17:02 +00:00
Owen Anderson
5804085f26 Fix disassembly of Thumb2 LDRSH with a #-0 offset. 
llvm-svn: 139943
 2011-09-16 21:08:33 +00:00
Owen Anderson
ceb2fb9548 Port over more Thumb2 assembly tests to disassembly tests. 
llvm-svn: 139915
 2011-09-16 17:56:04 +00:00
Owen Anderson
8bc7120609 Port over more Thumb2 assembly tests to disassembly tests. 
llvm-svn: 139912
 2011-09-16 17:22:48 +00:00
Owen Anderson
1037a3e60b Make use of Eli's FileCheck sorcery to improve this test. 
llvm-svn: 139645
 2011-09-13 21:37:50 +00:00
Owen Anderson
d0121fe635 Correct disassembly printing of Thumb2 post-incremented LDRD and STRD. 
llvm-svn: 139639
 2011-09-13 20:46:26 +00:00
Owen Anderson
a1a10ed5c6 Thumb2 POP's don't allow the PC as an operand, and PUSH's don't allow the SP either. 
llvm-svn: 139542
 2011-09-12 21:28:46 +00:00
Owen Anderson
05ef2c122d Port more encoding tests to decoding tests, and correct an improper Thumb2 pre-indexed load decoding this uncovered. 
llvm-svn: 139522
 2011-09-12 18:56:30 +00:00
Owen Anderson
9cd21ce8c9 LDM writeback is not allowed if Rn is in the target register list. 
llvm-svn: 139432
 2011-09-09 23:13:33 +00:00
Owen Anderson
dbe77fc5a1 Fix assembly/disassembly of Thumb2 ADR instructions with immediate operands. 
llvm-svn: 139422
 2011-09-09 22:24:36 +00:00