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1011 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
305e22bdab Annotate the remaining SSE MOV instructions. 
llvm-svn: 177592
 2013-03-20 22:37:16 +00:00
Jakob Stoklund Olesen
96a403dd67 Annotate SSE horizontal and integer instructions. 
llvm-svn: 177591
 2013-03-20 22:37:13 +00:00
Jakob Stoklund Olesen
d202f35d06 Add some missing SSE annotations. 
llvm-svn: 177540
 2013-03-20 16:56:39 +00:00
Jakob Stoklund Olesen
3b039fa614 Annotate various null idioms with SchedRW lists. 
llvm-svn: 177461
 2013-03-19 23:23:31 +00:00
Jakob Stoklund Olesen
a8c3f3d12c Annotate SSE float conversions with SchedRW lists. 
llvm-svn: 177460
 2013-03-19 23:23:29 +00:00
Jakob Stoklund Olesen
2d375df1d8 Add SchedRW annotations to most of X86InstrSSE.td. 
We hitch a ride with the existing OpndItins class that was used to add
instruction itinerary classes in the many multiclasses in this file.

Use the link provided by the X86FoldableSchedWrite.Folded to find the
right SchedWrite for folded loads.

llvm-svn: 177326
 2013-03-18 22:01:35 +00:00
Nadav Rotem
03b60b8657 Unaligned loads should use the VMOVUPS opcode. 
llvm-svn: 177130
 2013-03-14 23:49:44 +00:00
Craig Topper
97391f52d3 Fix inconsistent usage of PALIGN and PALIGNR when referring to the same instruction. 
llvm-svn: 173667
 2013-01-28 06:48:25 +00:00
Craig Topper
c5444baf77 Combine AVX and SSE forms of MOVSS and MOVSD into the same multiclasses so they get instantiated together. 
llvm-svn: 172704
 2013-01-17 06:59:42 +00:00
Craig Topper
58b9662000 Simplify nested strconcats in X86 td files since strconcat can take more than 2 arguments. 
llvm-svn: 172379
 2013-01-14 07:46:34 +00:00
Craig Topper
7dac5e7e3d Create a single multiclass for SSE and AVX version of MOVL/MOVH. Prevents needing to specify everything twice. No functional change intended 
llvm-svn: 172378
 2013-01-14 07:26:58 +00:00
Benjamin Kramer
26eae94ea6 X86: Add patterns for X86ISD::VSEXT in registers. 
Those can occur when something between the sextload and the store is on the same
chain and blocks isel. Fixes PR14887.

llvm-svn: 172353
 2013-01-13 11:37:04 +00:00
Craig Topper
b80024c8e6 Remove unnecessary # tokens at the beginning and end of defm names. 
llvm-svn: 171694
 2013-01-07 05:04:39 +00:00
Craig Topper
7af95b6c84 Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior. 
cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.

Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.

llvm-svn: 171668
 2013-01-06 20:39:29 +00:00
Craig Topper
23d1063500 Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
llvm-svn: 171356
 2013-01-02 08:00:39 +00:00
Craig Topper
f7827c5751 Merge SSE and AVX instruction definitions for PSHUFD/PSHUFHW/PSHUFLW. 
llvm-svn: 171355
 2013-01-02 07:27:49 +00:00
Rafael Espindola
cd13b5a188 Revert 171351. It broke MC/X86/x86-32-avx.s. 
llvm-svn: 171352
 2013-01-02 01:35:11 +00:00
Craig Topper
334e5f128c Merge SSE and AVX instruction definitions for scalar forms of SQRT, RSQRT, and RCP. 
llvm-svn: 171351
 2013-01-01 20:53:20 +00:00
Craig Topper
c4da4d53eb Remove unused argument from a multiclass. 
llvm-svn: 171340
 2013-01-01 03:42:44 +00:00
Craig Topper
94f978e60f Merge intrinsic instruction definitions for SSE and AVX versions of RCPPS and RSQRTPS. 
llvm-svn: 171339
 2013-01-01 03:30:21 +00:00
Craig Topper
4cb9a8b42e Remove 2 unused multiclasses. 
llvm-svn: 171338
 2013-01-01 02:02:45 +00:00
Craig Topper
912389c854 Merge AVX/SSE instruction definitions for SQRTPS/PD, RSQRTPS, RCPPS. No funcitonal change intended. 
llvm-svn: 171337
 2013-01-01 00:11:07 +00:00
Craig Topper
3a64f728dc Use packed instead of scalar itineraries for SSE1/2 SQRTPS/PD, RCPPS, and RSQRTPS. VEX-encoded forms already use packed. 
llvm-svn: 171336
 2012-12-31 23:49:05 +00:00
Craig Topper
175e8218c5 Remove intrinsic specific instructions for (V)SQRTPS/PD. Instead lower to target-independent ISD nodes and use the existing patterns for those. 
llvm-svn: 171237
 2012-12-29 18:18:20 +00:00
Craig Topper
93fdde7fff Remove intrinsic specific instructions for SSE/SSE2/AVX floating point max/min instructions. Lower them to target specific nodes and use those patterns instead. This also allows them to be commuted if UnsafeFPMath is enabled. 
llvm-svn: 171227
 2012-12-29 16:44:25 +00:00
Craig Topper
e2fd2d2c63 Merge basic_sse12_fp_binop_p_int and basic_sse12_fp_binop_p_y_int multiclasses. 
llvm-svn: 171171
 2012-12-27 22:53:47 +00:00
Craig Topper
179835e645 Merge basic_sse12_fp_binop_p and basic_sse12_fp_binop_p_y multiclasses. 
llvm-svn: 171166
 2012-12-27 18:51:50 +00:00
Craig Topper
f3cf4daada Add hasSideEffects=0 to some forms of ROUND, RCP, and RSQRT. 
llvm-svn: 171143
 2012-12-27 07:16:08 +00:00
Craig Topper
a44c63c7b9 Move single letter 'P' prefix out of multiclass now that tablegen allows defm to start with #NAME. This makes instruction names more searchable again. 
llvm-svn: 171141
 2012-12-27 06:34:54 +00:00
Craig Topper
152bee45fa Mark all the _REV instructions as not having side effects. They aren't really emitted by the backend, but it reduces the number of instructions in the output files with unmodelled side effects to make auditing easier. 
llvm-svn: 171118
 2012-12-26 21:30:22 +00:00
Craig Topper
2b01799bba Remove a special conditional setting of neverHasSideEffects if the instruction didn't have a pattern. This was leftover from when tablegen used to complain if things were already inferred from patterns. 
llvm-svn: 171117
 2012-12-26 21:04:30 +00:00
Craig Topper
d3212f7ab5 Merge still more SSE/AVX instruction definitions. 
llvm-svn: 171103
 2012-12-26 07:54:43 +00:00
Craig Topper
e1a7e48937 Merge more SSE/AVX instruction definitions. 
llvm-svn: 171102
 2012-12-26 07:20:35 +00:00
Craig Topper
e11b743aa8 Fix 80 column violation. 
llvm-svn: 171097
 2012-12-26 06:15:53 +00:00
Craig Topper
6bb87eb1c5 Fix class name in comment. 
llvm-svn: 171096
 2012-12-26 06:15:09 +00:00
Craig Topper
6548cfbc58 Merge SSE/AVX PCMPEQ/PCMPGT instruction definitions. 
llvm-svn: 171095
 2012-12-26 06:14:15 +00:00
Craig Topper
891ef3c0d5 Remove 'v' from mnemonic to fix asm matching failures. 
llvm-svn: 171093
 2012-12-26 06:02:15 +00:00
Craig Topper
0466a426a3 Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for a bunch of SSE2 integer arithmetic instructions. 
llvm-svn: 171092
 2012-12-26 05:49:15 +00:00
Craig Topper
cc9b1f307a Use an additional multiclass to merge the 128/256-bit SSE/AVX instruction definitions for PAND/POR/PXOR/PANDN 
llvm-svn: 171087
 2012-12-26 04:36:03 +00:00
Craig Topper
aabd76dd28 Merge an AVX/SSE 256-bit and 128-bit multiclass. 
llvm-svn: 171086
 2012-12-26 03:56:47 +00:00
Craig Topper
0b8d42715a Mark VANDNPD/VANDNPDS as not commutable. 
llvm-svn: 171085
 2012-12-26 03:48:10 +00:00
Benjamin Kramer
06ec6482f0 X86: Match the SSE/AVX min/max vector ops using a custom node instead of intrinsics 
This is very mechanical, no functionality change. Preparation for PR14667.

llvm-svn: 170898
 2012-12-21 14:04:55 +00:00
Elena Demikhovsky
12a5e01a52 Optimized load + SIGN_EXTEND patterns in the X86 backend. 
llvm-svn: 170506
 2012-12-19 07:50:20 +00:00
Benjamin Kramer
8d191a2586 X86: Add a couple of target-specific dag combines that turn VSELECTS into psubus if possible. 
We match the pattern "x >= y ? x-y : 0" into "subus x, y" and two special cases
if y is a constant. DAGCombiner canonicalizes those so we first have to undo the
canonicalization for those cases. The pattern occurs in gzip when the loop
vectorizer is enabled. Part of PR14613.

llvm-svn: 170273
 2012-12-15 16:47:44 +00:00
Craig Topper
e907c5dd53 Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing to the normal instructions. 
llvm-svn: 169482
 2012-12-06 07:31:16 +00:00
Craig Topper
32786c4c50 Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as neverHasSideEffects. 
llvm-svn: 169477
 2012-12-06 06:49:16 +00:00
Elena Demikhovsky
fa1ab36215 Simplified BLEND pattern matching for shuffles. 
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.

llvm-svn: 169366
 2012-12-05 09:24:57 +00:00
Craig Topper
ad33f996a6 Use roundps/pd for llvm.ceil, llvm.trunc, llvm.rint, and llvm.nearbyint of vector types. 
llvm-svn: 168141
 2012-11-16 06:37:56 +00:00
Craig Topper
f424da6ff9 Cleanup pcmp(e/i)str(m/i) instruction definitions and load folding support. 
llvm-svn: 167652
 2012-11-10 01:23:36 +00:00
Michael Liao
58efdb2214 Remove tailing whitespaces 
llvm-svn: 167445
 2012-11-06 08:06:35 +00:00