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101 Commits

Author SHA1 Message Date
Evan Cheng
0aced52f41 Added isPredicable bit to class Instruction. 
llvm-svn: 37117
 2007-05-16 20:47:01 +00:00
Evan Cheng
4dd52e052f PredicateOperand can be used as a normal operand for isel. 
llvm-svn: 36947
 2007-05-08 21:06:08 +00:00
Bill Wendling
dc82c5a195 Add an "implies" field to features. This indicates that, if the current 
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.

llvm-svn: 36756
 2007-05-04 20:38:40 +00:00
Chris Lattner
0b2b0185a0 expose HonorSignDependentRoundingFPMathOption to .td files 
llvm-svn: 36658
 2007-05-03 00:27:11 +00:00
Nate Begeman
767ee95d29 llvm bug #1350, parts 1, 2, and 3. 
llvm-svn: 36618
 2007-05-01 05:57:02 +00:00
Evan Cheng
842e2c48a0 Add sub-registers sets. 
llvm-svn: 36278
 2007-04-20 21:13:46 +00:00
Evan Cheng
498f19548c Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Chris Lattner
90c768b913 Add calling convention info 
llvm-svn: 34661
 2007-02-27 06:59:52 +00:00
Dan Gohman
e24135a647 Fix typos in comments. 
llvm-svn: 34456
 2007-02-20 20:52:03 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
0241c4a0b5 Comment. 
llvm-svn: 33114
 2007-01-12 07:25:16 +00:00
Chris Lattner
1158705ea7 add a new field needed by the code emitter generator. 
llvm-svn: 31768
 2006-11-15 22:55:04 +00:00
Chris Lattner
4296d2e0fa initial steps to getting the predicate on PPC::BLR right. 
llvm-svn: 31437
 2006-11-03 23:52:18 +00:00
Chris Lattner
f9394871ff remove dead var 
llvm-svn: 31436
 2006-11-03 23:50:15 +00:00
Evan Cheng
f49cb35d90 Add constraints to Instruction class. 
llvm-svn: 31332
 2006-11-01 00:26:27 +00:00
Chris Lattner
b25677f5ca Move the Imp tblgen class from the X86 backend to common code. 
llvm-svn: 30907
 2006-10-12 17:49:27 +00:00
Evan Cheng
abd650f034 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Evan Cheng
4bbd1c455f Added a Flags field to TargetOperandInfo. Currently the only flag is 
M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.

llvm-svn: 28387
 2006-05-18 20:44:26 +00:00
Evan Cheng
89187d589f Remove CalleeSavedRegisters from class Target. 
llvm-svn: 28377
 2006-05-18 00:09:53 +00:00
Evan Cheng
ea24815aa3 Remove PointerType from class Target 
llvm-svn: 28368
 2006-05-17 21:20:27 +00:00
Vladimir Prus
15fdb12773 Replace "../whatever.td" with "whatever.td", so that out-of-tree backends 
can just add lib/Target to TableGen includes.

llvm-svn: 28318
 2006-05-16 06:39:36 +00:00
Chris Lattner
676c3dfd68 Improve comment, patch provided by Vladimir Prus! 
llvm-svn: 28307
 2006-05-15 18:35:02 +00:00
Chris Lattner
3fe38bf77b Update comment. 
llvm-svn: 28283
 2006-05-14 02:05:19 +00:00
Chris Lattner
8456272509 Put PHI/INLINEASM into the correct namespace. 
llvm-svn: 28037
 2006-05-01 17:00:49 +00:00
Evan Cheng
5e80563052 Renamed AddedCost to AddedComplexity. 
llvm-svn: 27843
 2006-04-19 20:38:28 +00:00
Evan Cheng
318120f8ad Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Jim Laskey
d577317f38 Add support for dwarf register numbering. 
llvm-svn: 27080
 2006-03-24 21:13:21 +00:00
Chris Lattner
b979b51e39 Shuffle some includes around 
llvm-svn: 27073
 2006-03-24 18:52:35 +00:00
Chris Lattner
af9919716a Split the valuetypes out of Target.td into ValueTypes.td 
llvm-svn: 26490
 2006-03-03 01:55:26 +00:00
Evan Cheng
44412bbde0 New type v2f32. 
llvm-svn: 26435
 2006-03-01 01:06:22 +00:00
Evan Cheng
6a9422ce1c Added x86 integer vector types: 64-bit packed byte integer (v16i8), 64-bit 
packed word integer (v8i16), and 64-bit packed doubleword integer (v2i32).

llvm-svn: 26294
 2006-02-20 22:34:53 +00:00
Evan Cheng
77885c204d Subtarget feature can now set any variable to any value 
llvm-svn: 25678
 2006-01-27 08:09:42 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Evan Cheng
e720cfd690 New DAG node properties SNDPInFlag, SNDPOutFlag, and SNDPOptInFlag to replace 
hasInFlag, hasOutFlag.

llvm-svn: 25155
 2006-01-09 18:28:21 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Evan Cheng
d87688fe72 * Removed the use of FLAG. Now use hasFlagIn and hasFlagOut instead. 
* Added a pseudo instruction (for each target) that represent "return void".
  This is a workaround for lack of optional flag operand (return void is not
  lowered so it does not have a flag operand.)

llvm-svn: 24997
 2005-12-23 22:14:32 +00:00
Evan Cheng
297c23d2e7 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Evan Cheng
7580d9229f * Added instruction property hasCtrlDep for those which r/w control-flow 
chains.
* Added DAG node property SDNPHasChain for nodes which r/w control-flow
  chains.
* Renamed SDTVT to SDTOther.
* Added several new SDTypeProfiles for BR, BRCOND, RET, and WRITEPORT.
* Added SDNode definitions for BR, BRCOND, RET, and WRITEPORT.

llvm-svn: 24586
 2005-12-04 08:13:17 +00:00
Nate Begeman
811a41a87c Support multiple ValueTypes per RegisterClass, needed for upcoming vector 
work.  This change has no effect on generated code.

llvm-svn: 24563
 2005-12-01 04:51:06 +00:00
Nate Begeman
a1c2df2471 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00
Chris Lattner
c90cd9e5e8 refix typo 
llvm-svn: 24505
 2005-11-29 00:42:30 +00:00
Chris Lattner
7bc9c0d389 revert my change for the time being, which broke the build 
llvm-svn: 24503
 2005-11-29 00:24:08 +00:00
Chris Lattner
9e47c9a37a fix a typo :) 
llvm-svn: 24501
 2005-11-28 22:42:15 +00:00
Chris Lattner
bec2158e66 Capture more operand info, patch by Evan Cheng 
llvm-svn: 24422
 2005-11-19 07:00:10 +00:00
Nate Begeman
4567e9baf6 Also add the new vector value type here, for completeness. 
llvm-svn: 24405
 2005-11-18 00:53:32 +00:00
Jim Laskey
22e578cd95 Add attribute name and type to SubtargetFeatures. 
llvm-svn: 24012
 2005-10-26 17:28:23 +00:00
Jim Laskey
1fbdee408d Plugin new subtarget backend into the build. 
llvm-svn: 23870
 2005-10-21 19:05:19 +00:00
Jim Laskey
514a74d946 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Jim Laskey
0918760dec Push processor descriptions to the top of target and add command line info. 
llvm-svn: 23820
 2005-10-19 13:34:52 +00:00
Chris Lattner
2b9c260832 Pull DAG ISel generation nodes out of the PowerPC backend to where they 
can be used by other targets.  For those targets that want to use it,
have at.  :)

llvm-svn: 23680
 2005-10-10 06:00:30 +00:00