Andrew Trick
3166f72d7a
Removing the useless test that I added recently. It was meant as an example, but not complicated enough to merit another test.
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llvm-svn: 119898
2010-11-20 07:26:51 +00:00
Andrew Trick
189c10021d
RABasic fix. Regalloc is responsible for updating block live ins.
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llvm-svn: 119896
2010-11-20 02:57:05 +00:00
Andrew Trick
39d05a622e
Whitespace.
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llvm-svn: 119895
2010-11-20 02:43:55 +00:00
Bill Wendling
00481555e0
Add more Thumb add instruction encodings.
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llvm-svn: 119883
2010-11-20 01:18:47 +00:00
Bill Wendling
4fb2131b0a
Add Thumb encodings for some add instructions.
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llvm-svn: 119882
2010-11-20 01:00:29 +00:00
Bill Wendling
cd27d03d93
Add more encodings for Thumb instructions.
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llvm-svn: 119881
2010-11-20 00:53:35 +00:00
Bill Wendling
2271583883
Have the getAddrMode3OpValue() function in ARMCodeEmitter.cpp produce the same
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value that the one in ARMMCCodeEmitter.cpp does.
llvm-svn: 119878
2010-11-20 00:26:37 +00:00
Bill Wendling
55c499847a
Check for _setjmp too, because it's also used.
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llvm-svn: 119875
2010-11-20 00:03:09 +00:00
Jim Grosbach
b2b99c9b64
Fix ARM LDR* post-indexed operand encoding.
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llvm-svn: 119869
2010-11-19 23:14:43 +00:00
Bill Wendling
c568ce5bda
Encodings for the compare instructions.
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llvm-svn: 119868
2010-11-19 23:14:32 +00:00
Owen Anderson
023f096736
The Vm and Vn register fields must be the same for a register-register vmov.
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llvm-svn: 119867
2010-11-19 23:12:43 +00:00
Evan Cheng
2b30babdcc
Fix a cut-n-paste-error.
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llvm-svn: 119866
2010-11-19 23:01:16 +00:00
Owen Anderson
0d05099294
Document the new GVN number table structure.
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llvm-svn: 119865
2010-11-19 22:48:40 +00:00
Jim Grosbach
7445ae1145
Operand names
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llvm-svn: 119864
2010-11-19 22:43:08 +00:00
Jim Grosbach
4d6c419ea2
trailing whitespace
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llvm-svn: 119863
2010-11-19 22:42:55 +00:00
Eric Christopher
322b045c95
Don't need to save piecemeal now.
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llvm-svn: 119862
2010-11-19 22:39:56 +00:00
Eric Christopher
899d8247c8
Update comment.
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llvm-svn: 119861
2010-11-19 22:37:58 +00:00
Bill Wendling
65402c3a76
Add encodings for some of the thumb ADD instructions. Tests will come once the
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asm parser can handle them.
llvm-svn: 119860
2010-11-19 22:37:33 +00:00
Eric Christopher
716f891687
Update comment.
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llvm-svn: 119859
2010-11-19 22:36:41 +00:00
Jim Grosbach
69cad2c8b0
Clarify operand names.
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llvm-svn: 119858
2010-11-19 22:36:02 +00:00
Eric Christopher
563a0d8b6b
Refactor address mode handling into a single struct (ala x86), this
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should give allow a wider range of addressing modes.
No functional change.
llvm-svn: 119856
2010-11-19 22:30:02 +00:00
Jim Grosbach
0a0b2ed163
Fix encoding for ARM MLS instruction.
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llvm-svn: 119855
2010-11-19 22:22:37 +00:00
Owen Anderson
94babd312e
When folding addressing modes in CodeGenPrepare, attempt to look through PHI nodes
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if all the operands of the PHI are equivalent. This allows CodeGenPrepare to undo
unprofitable PRE transforms.
llvm-svn: 119853
2010-11-19 22:15:03 +00:00
Jim Grosbach
a7213faf85
Add ARM encoding information for STRD.
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llvm-svn: 119852
2010-11-19 22:14:31 +00:00
Jim Grosbach
bd80b3fe98
Shuffle things around a bit to keep like things together. Tidy up formatting.
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llvm-svn: 119851
2010-11-19 22:06:57 +00:00
Bill Wendling
29f262163a
Revert accidental commit.
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llvm-svn: 119850
2010-11-19 22:06:18 +00:00
Bill Wendling
e2f19dfde3
Change long binary encodings to use hex instead. It's more readable. Also
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initialize missing bit.
llvm-svn: 119849
2010-11-19 22:02:18 +00:00
Jim Grosbach
33930ff560
Factor out operand encoding bits for ARM addressing mode 2 store instructions.
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llvm-svn: 119846
2010-11-19 21:35:06 +00:00
Jim Grosbach
b58de2a8c7
Delete another dead class.
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llvm-svn: 119844
2010-11-19 21:16:08 +00:00
Jim Grosbach
dc695e7de2
whitespace tweak.
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llvm-svn: 119843
2010-11-19 21:14:37 +00:00
Rafael Espindola
68135a728b
Fix a use after free. Patch by Frits van Bommel.
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llvm-svn: 119842
2010-11-19 21:14:29 +00:00
Jim Grosbach
edef95dc56
Refactor PICSTR* instructions to really be pseudos. Nuke dead classes.
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llvm-svn: 119841
2010-11-19 21:14:02 +00:00
Jim Grosbach
a57ac3e282
Rename ARM .td class AIldst1 to AI2ldst for consistency with the other classes.
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llvm-svn: 119840
2010-11-19 21:07:51 +00:00
Jim Grosbach
9e50b14e34
Add ARM binary encoding information for the rest of the indexed loads.
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llvm-svn: 119821
2010-11-19 19:41:26 +00:00
Mon P Wang
4965983b22
Make isScalarToVector to return false if the node is a scalar. This will prevent
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DAGCombine from making an illegal transformation of bitcast of a scalar to a
vector into a scalar_to_vector.
llvm-svn: 119819
2010-11-19 19:08:12 +00:00
Kevin Enderby
214e641d8d
Added support for the Mach-O .symbol_resolver directive. rdar://8673046
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llvm-svn: 119816
2010-11-19 18:39:33 +00:00
Jim Grosbach
7a92d84b46
Remove dead code.
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llvm-svn: 119815
2010-11-19 18:18:37 +00:00
Jim Grosbach
c2ac477e54
ARM LDRD binary encoding.
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llvm-svn: 119812
2010-11-19 18:16:46 +00:00
Jim Grosbach
be61a90b99
Remove hard tabs.
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llvm-svn: 119810
2010-11-19 18:01:37 +00:00
Jim Grosbach
48531dd967
Remove trailing whitespace.
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llvm-svn: 119806
2010-11-19 17:11:02 +00:00
Benjamin Kramer
6807d1b8fa
Avoid release build warnings.
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llvm-svn: 119804
2010-11-19 16:36:02 +00:00
Owen Anderson
99c5ea71f7
Fix decoding ambiguities of stdrex and ldrex.
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llvm-svn: 119801
2010-11-19 13:11:50 +00:00
Benjamin Kramer
821c39433d
Silence warning about an uninitialized variable.
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llvm-svn: 119800
2010-11-19 11:37:26 +00:00
Duncan Sands
56aefef080
Remove threading of Xor over selects and phis, with an explanation
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of why such threading is pointless.
llvm-svn: 119798
2010-11-19 09:20:39 +00:00
Rafael Espindola
7c6bd9e0f9
Add a MCLineSectionOrder vector so that we produce the line tables in a
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deterministic order.
llvm-svn: 119795
2010-11-19 07:41:23 +00:00
Evan Cheng
46ea6d0bf1
These instructions are thumb2 only.
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llvm-svn: 119793
2010-11-19 06:28:11 +00:00
Evan Cheng
4a88903266
Fix an obvious oversight.
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llvm-svn: 119792
2010-11-19 06:15:10 +00:00
Jakob Stoklund Olesen
e3f7aad5c5
Don't attempt trivial coalescing for sub-register copies.
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Patch by Krister Wombell!
llvm-svn: 119791
2010-11-19 05:45:24 +00:00
Rafael Espindola
a06725942f
Add an assert.
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llvm-svn: 119788
2010-11-19 04:55:36 +00:00
Jakob Stoklund Olesen
52d6dd3079
Add ADT/IntervalMap.
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This is a sorted interval map data structure for small keys and values with
automatic coalescing and bidirectional iteration over coalesced intervals.
Except for coalescing intervals, it provides similar functionality to std::map.
It is however much more compact for small keys and values, and hopefully faster
too.
The container object itself can hold the first few intervals without any
allocations, then it switches to a cache conscious B+-tree representation. A
recycling allocator can be shared between many containers, even between
containers holding different types.
The IntervalMap is initially intended to be used with SlotIndex intervals for:
- Backing store for LiveIntervalUnion that is smaller and faster than std::set.
- Backing store for LiveInterval with less overhead than std::vector for typical
intervals and O(N log N) merging of large intervals. 99% of virtual registers
need 4 entries or less and would benefit from the small object optimization.
- Backing store for LiveDebugVariable which doesn't exist yet, but will track
debug variables during register allocation.
This is a work in progress. Missing items are:
- Performance metrics.
- erase().
- insert() shrinkage.
- clear().
- More performance metrics.
- Simplification and detemplatization.
llvm-svn: 119787
2010-11-19 04:47:19 +00:00