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Commit Graph

5 Commits

Author SHA1 Message Date
Stanislav Mekhanoshin
88108af2a3 [TBLGEN] Emit register pressure set enum
Differential Revision: https://reviews.llvm.org/D74649
2020-02-18 10:09:05 -08:00
Stanislav Mekhanoshin
563a9ce27a [TBLGEN] Fix subreg value overflow in DAGISelMatcher
Tablegen's DAGISelMatcher emits integers in a VBR format,
so if an integer is below 128 it can fit into a single
byte, otherwise high bit is set, next byte is used etc.
MatcherTable is essentially an unsigned char table. When
SelectionDAGISel parses the table it does a reverse translation.

In a situation when numeric value of an integer to emit is
unknown it can be emitted not as OPC_EmitInteger but as
OPC_EmitStringInteger using a symbolic name of the value.
In this situation the value should not exceed 127.

One of the situations when OPC_EmitStringInteger is used is
if we need to emit a subreg into a matcher table. However,
number of subregs can exceed 127. Currently last defined subreg
for AMDGPU is 192. That results in a silent bug in the ISel
with matcher reading from an invalid offset.

Fixed this bug to emit actual VBR encoded value for a subregs
which value exceeds 127.

Differential Revision: https://reviews.llvm.org/D74368
2020-02-12 13:29:57 -08:00
Matt Arsenault
63db126603 TableGen/GlobalISel: Fix pattern matching of immarg literals
For arguments that are not expected to be materialized with
G_CONSTANT, this was emitting predicates which could never match. It
was first adding a meaningless LLT check, which would always fail due
to the operand not being a register.

Infer the cases where a literal should check for an immediate operand,
instead of a register This avoids needing to invent a special way of
representing timm literal values.

Also handle immediate arguments in GIM_CheckLiteralInt. The comments
stated it handled isImm() and isCImm(), but that wasn't really true.

This unblocks work on the selection of all of the complicated AMDGPU
intrinsics in future commits.
2020-01-09 17:37:52 -05:00
Matt Arsenault
5bfe49f2ac GlobalISel/TableGen: Handle setcc patterns
This is a special case because one node maps to two different G_
instructions, and the operand order is changed.

This mostly enables G_FCMP for AMDPGPU. G_ICMP is still manually
selected for now since it has the SALU and VALU complication to deal
with.

llvm-svn: 370280
2019-08-29 01:13:41 +00:00
Jessica Paquette
582c860a72 [GlobalISel][NFC] Factor out common target code from GlobalISelEmitterTests
Factor out commonly-used target code from the GlobalISelEmitter tests into
a GlobalISelEmitterCommon.td file. This is tested by the original
GlobalISelEmitter.td test.

This reduces the amount of boilerplate code necessary for tests like this.

Differential Revision: https://reviews.llvm.org/D65777

llvm-svn: 368757
2019-08-13 22:14:37 +00:00