Evan Cheng
54215cd1ea
Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do
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64-bit vector shuffle.
llvm-svn: 26964
2006-03-22 22:07:06 +00:00
Chris Lattner
a3663c3dbb
Add some helper methods
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llvm-svn: 26882
2006-03-20 00:55:52 +00:00
Evan Cheng
cad75d9f0c
Added a way for TargetLowering to specify what values can be used as the
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scale component of the target addressing mode.
llvm-svn: 26802
2006-03-16 21:47:42 +00:00
Evan Cheng
ed013bd937
Add LSR hooks.
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llvm-svn: 26740
2006-03-13 23:18:16 +00:00
Chris Lattner
c656f75535
custom lowered nodes are legal too
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llvm-svn: 26561
2006-03-05 23:49:19 +00:00
Evan Cheng
0c445855f2
Number of NodeTypes now exceeds 128.
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llvm-svn: 26503
2006-03-03 06:58:59 +00:00
Chris Lattner
40501a50fe
Add interfaces for targets to provide target-specific dag combiner optimizations.
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llvm-svn: 26442
2006-03-01 04:52:55 +00:00
Evan Cheng
b8a44ab1dd
Missing a cast previously.
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llvm-svn: 26434
2006-03-01 00:58:54 +00:00
Chris Lattner
0957a2e87c
Add C_Memory operand type
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llvm-svn: 26344
2006-02-24 01:10:14 +00:00
Chris Lattner
ed45ad33b7
Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean.
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Patch by Martin Partel!
llvm-svn: 26313
2006-02-22 16:23:43 +00:00
Chris Lattner
6bb2c3e9cd
split register class handling from explicit physreg handling.
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llvm-svn: 26308
2006-02-22 00:56:39 +00:00
Chris Lattner
ed3b59056a
Pass in a value type to getRegForInlineAsmConstraint, allowing targets to
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select different sets of registers depending on the type requested.
llvm-svn: 26304
2006-02-21 23:10:29 +00:00
Nate Begeman
aef186befc
Fix a nit sabre noticed
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llvm-svn: 26262
2006-02-17 18:06:19 +00:00
Nate Begeman
0bc71999b9
Rework the SelectionDAG-based implementations of SimplifyDemandedBits
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and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.
llvm-svn: 26238
2006-02-16 21:11:51 +00:00
Evan Cheng
f6c74c0096
Rename maxStoresPerMemSet to maxStoresPerMemset, etc.
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llvm-svn: 26174
2006-02-14 08:38:30 +00:00
Chris Lattner
478eb50b79
getConstraintType should be virtual.
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llvm-svn: 26041
2006-02-07 20:13:44 +00:00
Chris Lattner
2395722dbd
Add some methods for inline asm support.
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llvm-svn: 25950
2006-02-04 02:12:09 +00:00
Nate Begeman
2d9838ec9b
Add a framework for eliminating instructions that produces undemanded bits.
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llvm-svn: 25945
2006-02-03 22:24:05 +00:00
Chris Lattner
5583b2e227
Clear the OpAction field before setting it. This allows a target to set
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an instruction operation action to Expand, then set it to Legal later.
llvm-svn: 25812
2006-01-30 06:09:03 +00:00
Chris Lattner
a1cc69e24e
Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface,
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making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.
llvm-svn: 25802
2006-01-30 04:08:18 +00:00
Chris Lattner
7f64ff5ce0
Pass the address of the main MaskedValueIsZero function to allow recursion.
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llvm-svn: 25797
2006-01-30 03:48:36 +00:00
Chris Lattner
a8ca8f5eb9
Clean up the interface to ValueTypeActions, allowing Legalize to use a copy
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of it more cleanly. Double the size of OpActions, allowing it to hold actions
for any VT.
llvm-svn: 25782
2006-01-29 08:40:37 +00:00
Chris Lattner
2240c0df71
remove this method I just added, now is not the time.
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llvm-svn: 25729
2006-01-28 03:43:33 +00:00
Chris Lattner
063c13029b
add a new callback
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llvm-svn: 25727
2006-01-28 03:37:03 +00:00
Nate Begeman
87c2c0e66b
Implement Promote for VAARG, and allow it to be custom promoted for people
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who don't want the default behavior (Alpha).
llvm-svn: 25726
2006-01-28 03:14:31 +00:00
Nate Begeman
d2c6fbef4a
Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for
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the same functionality. This addresses another piece of bug 680. Next,
on to fixing Alpha VAARG, which I broke last time.
llvm-svn: 25696
2006-01-27 21:09:22 +00:00
Chris Lattner
ab8e0e40f9
Add a method for inline asm support.
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llvm-svn: 25656
2006-01-26 20:27:33 +00:00
Nate Begeman
c29fac7fce
First part of bug 680:
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Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.
llvm-svn: 25606
2006-01-25 18:21:52 +00:00
Evan Cheng
f4b53efbb2
Add a enum to specify target scheduling preference: SchedulingForLatency or
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SchedulingForRegPressure. Added corresponding methods to set / get the value.
llvm-svn: 25598
2006-01-25 09:09:02 +00:00
Chris Lattner
8fe9dd16fb
Provide an interface for Targets to specify their stack pointer register
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for llvm.stacksave/restore.
llvm-svn: 25275
2006-01-13 17:47:52 +00:00
Jeff Cohen
8727139340
Oh oh... Unix is case sensitive.
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llvm-svn: 24928
2005-12-22 01:46:59 +00:00
Jeff Cohen
8afabfd8f1
Make it compile with VC++.
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llvm-svn: 24927
2005-12-22 01:44:51 +00:00
Evan Cheng
822f360f84
Added TargetLowering::isMaskedValueZeroForTargetNode() declaration.
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llvm-svn: 24923
2005-12-21 23:15:41 +00:00
Evan Cheng
44e4e6a57f
Added a hook to print out names of target specific DAG nodes.
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llvm-svn: 24877
2005-12-20 06:22:03 +00:00
Nate Begeman
a1c2df2471
Add the majority of the vector machien value types we expect to support,
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and make a few changes to the legalization machinery to support more than
16 types.
llvm-svn: 24511
2005-11-29 05:45:29 +00:00
Nate Begeman
5784fb4adf
Teach the type lowering code about turning packed types into vector types.
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Next step: generating vector dag nodes, and legalizing them into scalar
code.
llvm-svn: 24404
2005-11-17 21:44:42 +00:00
Nate Begeman
6c42f509bc
Invert the TargetLowering flag that controls divide by consant expansion.
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Add a new flag to TargetLowering indicating if the target has really cheap
signed division by powers of two, make ppc use it. This will probably go
away in the future.
Implement some more ISD::SDIV folds in the dag combiner
Remove now dead code in the x86 backend.
llvm-svn: 23853
2005-10-21 00:02:42 +00:00
Nate Begeman
2b0b27775d
Enable targets to say that integer divide is expensive, which will trigger
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an upcoming optimization in the DAG Combiner.
llvm-svn: 23834
2005-10-20 02:14:14 +00:00
Nate Begeman
ee581735d9
Add the ability to lower return instructions to TargetLowering. This
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allows us to lower legal return types to something else, to meet ABI
requirements (such as that i64 be returned in two i32 regs on Darwin/ppc).
llvm-svn: 23802
2005-10-18 23:23:37 +00:00
Chris Lattner
62922d5727
Add a new flag for targets where setjmp/longjmp saves/restores the signal mask,
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and _setjmp/_longjmp should be used instead (for llvm.setjmp/llvm.longjmp).
llvm-svn: 23479
2005-09-27 22:13:36 +00:00
Reid Spencer
31b20389f9
Change the names of member variables per Chris' instructions, and document
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them more clearly.
llvm-svn: 23118
2005-08-27 19:09:02 +00:00
Chris Lattner
e91069c4de
add some forward defs
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llvm-svn: 23100
2005-08-26 21:06:40 +00:00
Chris Lattner
ac19224b29
spell this right!
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llvm-svn: 23097
2005-08-26 20:53:44 +00:00
Chris Lattner
98bd9339ce
Add a hook
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llvm-svn: 23096
2005-08-26 20:53:09 +00:00
Chris Lattner
b71b78a79d
rename hasNativeSupportFor* -> is(Operation|Type)Legal.
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llvm-svn: 23011
2005-08-24 16:34:59 +00:00
Jeff Cohen
81980781a1
Eliminate tabs and trailing spaces.
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llvm-svn: 22520
2005-07-27 05:53:44 +00:00
Reid Spencer
40c5ebe4eb
For: memory operations -> stores
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This is the first incremental patch to implement this feature. It adds no
functionality to LLVM but setup up the information needed from targets in
order to implement the optimization correctly. Each target needs to specify
the maximum number of store operations for conversion of the llvm.memset,
llvm.memcpy, and llvm.memmove intrinsics into a sequence of store operations.
The limit needs to be chosen at the threshold of performance for such an
optimization (generally smallish). The target also needs to specify whether
the target can support unaligned stores for multi-byte store operations.
This helps ensure the optimization doesn't generate code that will trap on
an alignment errors.
More patches to follow.
llvm-svn: 22468
2005-07-19 04:52:44 +00:00
Chris Lattner
bf100c8bdb
Make several cleanups to Andrews varargs change:
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1. Pass Value*'s into lowering methods so that the proper pointers can be
added to load/stores from the valist
2. Intrinsics that return void should only return a token chain, not a token
chain/retval pair.
3. Rename LowerVAArgNext -> LowerVAArg, because VANext is long gone.
llvm-svn: 22338
2005-07-05 19:57:53 +00:00
Andrew Lenharth
108f509fb5
header file changes for varargs
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llvm-svn: 22253
2005-06-18 18:31:30 +00:00
Chris Lattner
ae59fdbd99
Pass the dag into LowerOperation
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llvm-svn: 22005
2005-05-14 05:51:05 +00:00