Richard Osborne
92f0d25122
Add instruction encodings for ZEXT and SEXT.
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Previously these were marked with the wrong format.
llvm-svn: 170327
2012-12-17 13:20:37 +00:00
Richard Osborne
cccafe2726
Add instruction encodings / disassembly support for 2r instructions.
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llvm-svn: 170323
2012-12-17 12:29:31 +00:00
Richard Osborne
815fca9724
Add instruction encodings / disassembly support for 0r instructions.
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llvm-svn: 170322
2012-12-17 12:26:29 +00:00
Richard Osborne
5c2cbafeba
Add instruction encodings and disassembly for 1r instructions.
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llvm-svn: 170293
2012-12-16 17:37:34 +00:00
Richard Osborne
514735415d
Replace ${:comment} with the comment symbol.
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llvm-svn: 170286
2012-12-16 15:59:02 +00:00
Jakob Stoklund Olesen
02cb24658a
Fix load/store SDNode flags.
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llvm-svn: 162558
2012-08-24 14:43:30 +00:00
Bill Wendling
17b12b72bc
Remove tabs.
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llvm-svn: 160477
2012-07-19 00:11:40 +00:00
Jakob Stoklund Olesen
b8af245a15
Remove variable_ops from call instructions in most targets.
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Call instructions are no longer required to be variadic, and
variable_ops should only be used for instructions that encode a variable
number of arguments, like the ARM stm/ldm instructions.
llvm-svn: 160189
2012-07-13 20:44:29 +00:00
Richard Osborne
96c0be7351
Fix pattern for MKMSK instruction.
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llvm-svn: 158409
2012-06-13 17:59:12 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Richard Osborne
0ec86a885b
Fix 80 column violations.
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Original patch by Liu.
llvm-svn: 140385
2011-09-23 16:28:10 +00:00
Richard Osborne
05cda7958d
Mark LDWCP as having no side effects.
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llvm-svn: 139494
2011-09-12 14:41:31 +00:00
Richard Osborne
6b6b0b535d
Add Uses=[SP] to call instructions. This fixes a miscompilation with a
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variable sized alloca.
llvm-svn: 138433
2011-08-24 13:32:43 +00:00
Richard Osborne
415c5ff412
Add intrinsics for SETEV, GETED, GETET.
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llvm-svn: 137938
2011-08-18 13:00:48 +00:00
Richard Osborne
b469141419
Add intrinsics for the zext / sext instructions.
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llvm-svn: 135476
2011-07-19 13:28:50 +00:00
Richard Osborne
50303e0d38
Add intrinsics for the testct, testwct instructions.
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llvm-svn: 135475
2011-07-19 13:00:40 +00:00
Richard Osborne
409c0d7768
Add intrinsics for the peek and endin instructions.
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llvm-svn: 135474
2011-07-19 12:50:25 +00:00
Richard Osborne
660fe84614
Fix 80 column violations.
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llvm-svn: 132341
2011-05-31 16:30:33 +00:00
Richard Osborne
4293c93896
Add XCore intrinsic for crc8.
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llvm-svn: 132340
2011-05-31 16:24:49 +00:00
Richard Osborne
34a4652dcd
Add XCore intrinsic for crc32.
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llvm-svn: 132336
2011-05-31 14:47:36 +00:00
Richard Osborne
5b9df0d075
Add XCore intrinsics for initializing / starting / synchronizing threads.
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llvm-svn: 128633
2011-03-31 15:13:13 +00:00
Richard Osborne
6bad79b514
Add XCore intrinsic for setpsc.
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llvm-svn: 127821
2011-03-17 18:42:05 +00:00
Richard Osborne
8b90369d96
Add XCore intrinsics for setclk, setrdy.
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llvm-svn: 127761
2011-03-16 21:56:00 +00:00
Richard Osborne
318e25c620
Add checkevent intrinsic to check if any resources owned by the current thread
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can event.
llvm-svn: 127741
2011-03-16 18:34:00 +00:00
Richard Osborne
70204c1c29
Add XCore intrinsics for getps, setps, setsr and clrsr.
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llvm-svn: 127678
2011-03-15 13:45:47 +00:00
Richard Osborne
a8df984a31
Add XCore intrinsic for eeu instruction.
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llvm-svn: 126384
2011-02-24 13:39:18 +00:00
Richard Osborne
d9564589f6
Add XCore intrinsic for clre instruction.
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llvm-svn: 126322
2011-02-23 18:52:05 +00:00
Richard Osborne
4a55817288
Add llvm.xcore.waitevent intrinsic. The effect of this intrinsic is to enable
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events on the thread and wait until a resource is ready to event. The vector
of the resource that is ready is returned.
llvm-svn: 126320
2011-02-23 18:35:59 +00:00
Richard Osborne
aaac1b01fd
Add XCore intrinsic for the setv instruction.
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llvm-svn: 126315
2011-02-23 16:46:37 +00:00
Richard Osborne
2374e9683e
Fix format for setc instruction.
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llvm-svn: 126314
2011-02-23 15:20:16 +00:00
Richard Osborne
aa39bf94b4
Add XCore intrinsic for settw instruction.
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llvm-svn: 126313
2011-02-23 14:45:03 +00:00
Richard Osborne
bd0e21b5ca
Add XCore intrinsics for various instructions on ports.
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llvm-svn: 126132
2011-02-21 18:23:30 +00:00
Richard Osborne
112cff2533
Add intrinsic for setc instruction on the XCore.
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llvm-svn: 125186
2011-02-09 13:22:12 +00:00
Richard Osborne
5c655f451e
Add XCore intrinsics for resource instructions.
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llvm-svn: 124794
2011-02-03 13:14:25 +00:00
Chris Lattner
01e8c46349
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Jakob Stoklund Olesen
216f6cc9ae
Remove Predicate_* calls from MBlaze and XCore
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llvm-svn: 112920
2010-09-03 00:35:16 +00:00
Eric Christopher
2dae43dbe4
Remove isTwoAddress from XCore.
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llvm-svn: 106446
2010-06-21 18:51:38 +00:00
Chris Lattner
4de7f7e862
fix a type contradition: XCoreISD::RETSP has one argument, not zero.
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llvm-svn: 99760
2010-03-28 08:47:39 +00:00
Chris Lattner
896b393fab
set SDNPVariadic on nodes throughout the rest of the targets that
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need them.
llvm-svn: 98937
2010-03-19 05:33:51 +00:00
Richard Osborne
92fb0be76b
Don't mark call instruction as a barrier.
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llvm-svn: 96983
2010-02-23 21:08:11 +00:00
Richard Osborne
eb0446c12a
ECALLF, ECALLT shouldn't be marked as barriers.
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llvm-svn: 96964
2010-02-23 18:29:49 +00:00
Richard Osborne
9abd3b3ca7
Mark unconditional branches as barriers. Found using -verify-machineinstrs
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llvm-svn: 96960
2010-02-23 18:13:38 +00:00
Richard Osborne
7387249531
Lower BR_JT on the XCore to a jump into a series of jump instructions.
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llvm-svn: 96942
2010-02-23 13:25:07 +00:00
Dan Gohman
92b6122204
Fix "the the" and similar typos.
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llvm-svn: 95781
2010-02-10 16:03:48 +00:00
Richard Osborne
fc2d5141a4
Add XCore support for indirectbr / blockaddress.
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llvm-svn: 89273
2009-11-18 23:20:42 +00:00
Dan Gohman
4631d78a3b
Set isBarrier = 1 on return instructions, as they are control barriers.
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llvm-svn: 86851
2009-11-11 18:11:07 +00:00
Dan Gohman
3393a4c997
Rename usesCustomDAGSchedInserter to usesCustomInserter, and update a
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bunch of associated comments, because it doesn't have anything to do
with DAGs or scheduling. This is another step in decoupling MachineInstr
emitting from scheduling.
llvm-svn: 85517
2009-10-29 18:10:34 +00:00
Richard Osborne
1719935e3f
Add some peepholes for signed comparisons using ashr X, X, 32.
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llvm-svn: 83549
2009-10-08 15:38:17 +00:00
Richard Osborne
90a7ea5c13
Remove xs1b predicate since it is no longer needed to differentiate betweem
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xs1a and xs1b.
llvm-svn: 83383
2009-10-06 16:17:57 +00:00
Richard Osborne
b692ade672
Remove xs1a subtarget. xs1a is a preproduction device used in
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early development boards which is no longer supported in the
XMOS toolchain.
llvm-svn: 83381
2009-10-06 16:01:09 +00:00