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Commit Graph

172297 Commits

Author SHA1 Message Date
Diana Picus
38eb1743f5 [ARM GlobalISel] Implement call lowering for Thumb2
The only things that are different from arm are:
* different opcodes for calls and returns
* Thumb calls take predicate operands

llvm-svn: 348347
2018-12-05 10:35:28 +00:00
Alina Sbirlea
1897ce7884 [LICM] *Actually* disable ControlFlowHoisting.
Summary:
The remaining code paths that ControlFlowHoisting introduced that were
not disabled, increased compile time by 3x for some benchmarks.
The time is spent in DominatorTree updates.

Reviewers: john.brawn, mkazantsev

Subscribers: sanjoy, jlebar, llvm-commits

Differential Revision: https://reviews.llvm.org/D55313

llvm-svn: 348345
2018-12-05 10:16:21 +00:00
Hans Wennborg
69ba78a8d8 HowToBuildWithPGO.rst: Fix a few details in the manual steps
Differential revision: https://reviews.llvm.org/D55268

llvm-svn: 348342
2018-12-05 08:35:30 +00:00
Craig Topper
8dd94abc04 [X86] Remove -costmodel-reduxcost=true from the experimental vector reduction intrinsic tests as it appears to be unnecessary. NFC
I think this has something to do with matching reductions from extractelement, binops, and shuffles. But we're not matching here.

llvm-svn: 348340
2018-12-05 07:56:50 +00:00
Craig Topper
c62560fb9a [X86] Add more cost model tests for vector reductions with narrow vector types. NFC
llvm-svn: 348339
2018-12-05 07:26:57 +00:00
Saleem Abdulrasool
dc3c5dd6f9 AArch64: support funclets in fastcall and swift_call
Functions annotated with `__fastcall` or `__attribute__((__fastcall__))`
or `__attribute__((__swiftcall__))` may contain SEH handlers even on
Win64.  This matches the behaviour of cl which allows for
`__try`/`__except` inside a `__fastcall` function.  This was detected
while trying to self-host clang on Windows ARM64.

llvm-svn: 348337
2018-12-05 07:09:20 +00:00
Craig Topper
3fdd2e4359 [X86] Add narrow vector test cases to vector-reduce* tests. Add copies of the tests with -x86-experimental-vector-widening-legalization
llvm-svn: 348334
2018-12-05 06:29:44 +00:00
Max Kazantsev
5517ebbb98 [NFC] Verify memoryssa in test for PR39783
llvm-svn: 348333
2018-12-05 05:20:08 +00:00
Craig Topper
6d3a936c11 [MachineLICM][X86][AMDGPU] Fix subtle bug in the updating of PhysRegClobbers in post-RA LICM
It looks like MCRegAliasIterator can visit the same physical register twice. When this happens in this code in LICM we end up setting the PhysRegDef and then later in the same loop visit the register again. Now we see that PhysRegDef is set from the earlier iteration so now set PhysRegClobber.

This patch splits the loop so we have one that uses the previous value of PhysRegDef to update PhysRegClobber and second loop that updates PhysRegDef.

The X86 atomic test is an improvement. I had to add sideeffect to the two shrink wrapping tests to prevent hoisting from occurring. I'm not sure about the AMDGPU tests. It looks like the branch instruction changed at end the of the loops. And in the branch-relaxation test I think there is now "and vcc, exec, -1" instruction that wasn't there before.

Differential Revision: https://reviews.llvm.org/D55102

llvm-svn: 348330
2018-12-05 03:41:26 +00:00
Vitaly Buka
8943dc47fc [asan] Add clang flag -fsanitize-address-use-odr-indicator
Reviewers: eugenis, m.ostapenko, ygribov

Subscribers: hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D55157

llvm-svn: 348327
2018-12-05 01:44:31 +00:00
Craig Topper
b6cd2e2aef [TableGen] Preserve order of output operands in DAGISelMatcherGen
Summary:
This fixes support in DAGISelMatcher backend for DAG nodes with multiple
result values. Previously the order of results in selected DAG nodes always
matched the order of results in ISel patterns. After the change the order of
results matches the order of operands in OutOperandList instead.

For example, given this definition from the attached test case:

  def INSTR : Instruction {
    let OutOperandList = (outs GPR:$r1, GPR:$r0);
    let InOperandList = (ins GPR:$t0, GPR:$t1);
    let Pattern = [(set i32:$r0, i32:$r1, (udivrem i32:$t0, i32:$t1))];
  }

the DAGISelMatcher backend currently produces a matcher that creates INSTR
nodes with the first result `$r0` and the second result `$r1`, contrary to the
order in the OutOperandList. The order of operands in OutOperandList does not
matter at all, which is unexpected (and unfortunate) because the order of
results of a DAG node does matters, perhaps a lot.

With this change, if the order in OutOperandList does not match the order in
Pattern, DAGISelMatcherGen emits CompleteMatch opcodes with the order of
results taken from OutOperandList. Backend writers can use it to express
result reorderings in TableGen.

If the order in OutOperandList matches the order in Pattern, the result of
DAGISelMatcherGen is unaffected.

Patch by Eugene Sharygin

Reviewers: andreadb, bjope, hfinkel, RKSimon, craig.topper

Reviewed By: craig.topper

Subscribers: nhaehnle, craig.topper, llvm-commits

Differential Revision: https://reviews.llvm.org/D55055

llvm-svn: 348326
2018-12-05 00:47:59 +00:00
Amara Emerson
15e381763b [SelectionDAG] Split very large token factors for loads into 64k chunks.
There's a 64k limit on the number of SDNode operands, and some very large
functions with 64k or more loads can cause crashes due to this limit being hit
when a TokenFactor with this many operands is created. To fix this, create
sub-tokenfactors if we've exceeded the limit.

No test case as it requires a very large function.

rdar://45196621

Differential Revision: https://reviews.llvm.org/D55073

llvm-svn: 348324
2018-12-05 00:41:30 +00:00
Michael Kruse
67da1c2e76 [ADT] Add zip_longest iterators.
Like the already existing zip_shortest/zip_first iterators, zip_longest
iterates over multiple iterators at once, but has as many iterations as
the longest sequence.

This means some iterators may reach the end before others do.
zip_longest uses llvm::Optional's None value to mark a
past-the-end value.

zip_longest is not reverse-iteratable because the tuples iterated over
would be different for different length sequences (IMHO for the same
reason neither zip_shortest nor zip_first should be reverse-iteratable;
one can still reverse the ranges individually if that's the expected
behavior).

In contrast to zip_shortest/zip_first, zip_longest tuples contain
rvalues instead of references. This is because llvm::Optional cannot
contain reference types and the value-initialized default does not have
a memory location a reference could point to.

The motivation for these iterators is to use C++ foreach to compare two
lists of ordered attributes in D48100 (SemaOverload.cpp and
ASTReaderDecl.cpp).

Idea by @hfinkel.

This re-commits r348301 which was reverted by r348303.
The compilation error by gcc 5.4 was resolved using make_tuple in the in
the initializer_list.
The compileration error by msvc14 was resolved by splitting
ZipLongestValueType (which already was a workaround for msvc15) into
ZipLongestItemType and ZipLongestTupleType.

Differential Revision: https://reviews.llvm.org/D48348

llvm-svn: 348323
2018-12-05 00:31:54 +00:00
Peter Collingbourne
fe3c1d8a1b LTO: Don't internalize available_externally globals.
This breaks C and C++ semantics because it can cause the address
of the global inside the module to differ from the address outside
of the module.

Differential Revision: https://reviews.llvm.org/D55237

llvm-svn: 348321
2018-12-05 00:09:36 +00:00
Amara Emerson
84e4cfc565 [AArch64][GlobalISel] Re-enable selection of volatile loads.
We previously disabled this in r323371 because of a bug where we selected an
extending load, but didn't delete the old G_LOAD, resulting in two loads being
generated for volatile loads.

Since we now have dedicated G_SEXTLOAD/G_ZEXTLOAD operations, and that the
tablegen patterns should no longer be able to select (ext(load x)) patterns, it
should be safe to re-enable it.

The old test case should still work as expected.

llvm-svn: 348320
2018-12-05 00:03:09 +00:00
Zachary Turner
5318eac711 Remove the hash code from CVRecord.
This is no longer used and is just taking up space in the structure.
Heap allocation of this structure is on the critical path, so space
actually matters.

llvm-svn: 348318
2018-12-04 23:56:07 +00:00
Vitaly Buka
0764434796 [asan] Split -asan-use-private-alias to -asan-use-odr-indicator
Reviewers: eugenis, m.ostapenko, ygribov

Subscribers: mehdi_amini, kubamracek, hiraditya, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D55156

llvm-svn: 348316
2018-12-04 23:17:41 +00:00
Sanjay Patel
28d71715a3 [InstCombine] add tests for implied simplifications; NFC
Ideally, we would fold all of these in InstSimplify in a
similar way to rL347896, but this is a bit awkward when
we're trying to simplify a compare directly because the
ValueTracking API expects the compare as an input, but
in InstSimplify, we just have the operands of the compare.

Given that we can do transforms besides just simplifications,
we might as well just extend the code in InstCombine (which 
already does simplifications with constant operands).

llvm-svn: 348312
2018-12-04 22:25:33 +00:00
Saleem Abdulrasool
f28e4aa042 AArch64: clean up some whitespace in Windows CC (NFC)
Drive by clean up for Windows ARM64 variadic CC (NFC).

llvm-svn: 348310
2018-12-04 22:19:29 +00:00
Zachary Turner
0e5c8b1f04 [llvm-pdbutil] Remove the analyze subcommand.
Nobody has used this since it was introduced, and it doesn't have
test coverage.

llvm-svn: 348307
2018-12-04 21:49:04 +00:00
Zachary Turner
2e1b430a43 [PDB] Emit S_UDT records in LLD.
Previously these were dropped.  We now understand them sufficiently
well to start emitting them.  From the debugger's perspective, this
now enables us to have debug info about typedefs (both global and
function-locally scoped)

Differential Revision: https://reviews.llvm.org/D55228

llvm-svn: 348306
2018-12-04 21:48:46 +00:00
Nirav Dave
63829c0cd0 [AVR] Silence fallthrough warning. NFC.
llvm-svn: 348304
2018-12-04 21:41:52 +00:00
Michael Kruse
1cbc2656f9 Revert "[ADT] Add zip_longest iterators"
This reverts commit r348301.

Compilation fails on buildbots with older versions of gcc and msvc.

llvm-svn: 348303
2018-12-04 21:38:55 +00:00
Michael Kruse
63a060a406 [ADT] Add zip_longest iterators
Like the already existing zip_shortest/zip_first iterators, zip_longest
iterates over multiple iterators at once, but has as many iterations as
the longest sequence.

This means some iterators may reach the end before others do.
zip_longest uses llvm::Optional's None value to mark a
past-the-end value.

zip_longest is not reverse-iteratable because the tuples iterated over
would be different for different length sequences (IMHO for the same
reason neither zip_shortest nor zip_first should be reverse-iteratable;
one can still reverse the ranges individually if that's the expected
behavior).

In contrast to zip_shortest/zip_first, zip_longest tuples contain
rvalues instead of references. This is because llvm::Optional cannot
contain reference types and the value-initialized default does not have
a memory location a reference could point to.

The motivation for these iterators is to use C++ foreach to compare two
lists of ordered attributes in D48100 (SemaOverload.cpp and
ASTReaderDecl.cpp).

Idea by @hfinkel.

Differential Revision: https://reviews.llvm.org/D48348

llvm-svn: 348301
2018-12-04 21:06:16 +00:00
Stefan Pintilie
edd36f6e4c [PowerPC] Make no-PIC default to match GCC - LLVM
Change the default for PowerPC LE to -fno-PIC.

Differential Revision: https://reviews.llvm.org/D53383

llvm-svn: 348298
2018-12-04 20:14:57 +00:00
Sanjay Patel
4b0bdd85c5 [CmpInstAnalysis] fix function signature for ICmp code to predicate; NFC
The old function underspecified the return type, took an unused parameter,
and had a misleading name.

llvm-svn: 348292
2018-12-04 18:53:27 +00:00
Matt Arsenault
8954c22356 Move llc-start-stop-instance to x86
Avoid bot failures where the host pass
setup might not have 2 dead-mi-elimination runs

llvm-svn: 348290
2018-12-04 18:19:08 +00:00
Nirav Dave
109821a1d1 [SelectionDAG] Redefine isGAPlusOffset in terms of unwrapAddress. NFCI.
llvm-svn: 348288
2018-12-04 17:59:43 +00:00
Matt Arsenault
9201a09e01 AMDGPU: Add f32 vectors to SGPR register classes
llvm-svn: 348286
2018-12-04 17:51:36 +00:00
Matt Arsenault
765e6aafe7 MIR: Add method to stop after specific runs of passes
Currently if you use -{start,stop}-{before,after}, it picks
the first instance with the matching pass name. If you run
the same pass multiple times, there's no way to distinguish them.

Allow specifying a run index wih ,N to specify which you mean.

llvm-svn: 348285
2018-12-04 17:45:12 +00:00
Sanjay Patel
444e9d9643 [InstCombine] rearrange foldICmpWithDominatingICmp; NFC
Move it out from under the constant check, reorder
predicates, add comments. This makes it easier to
extend to handle the non-constant case.

llvm-svn: 348284
2018-12-04 17:44:24 +00:00
Jonas Devlieghere
3cedfc1fd4 [dsymutil] Ensure we're comparing time stamps with the same precision.
After TimePoint's precision was increased in LLVM we started seeing
failures because the modification times didn't match. This adds a time
cast to ensure that we're comparing TimePoints with the same amount of
precision.

llvm-svn: 348283
2018-12-04 17:15:23 +00:00
Simon Pilgrim
8f7f9e2174 [X86][SSE] Add SimplifyDemandedBitsForTargetNode handling for MOVMSK
Moves existing SimplifyDemandedBits call out of combineMOVMSK and add SimplifyDemandedVectorElts call based on the sign bits we need.

llvm-svn: 348282
2018-12-04 16:52:32 +00:00
Ilya Biryukov
750ab7e0a9 Revert "Adapt gcov to changes in CFE."
This reverts commit r348203.
Reason: this produces absolute paths in .gcno files, breaking us
internally as we rely on them being consistent with the filenames passed
in the command line.

Also reverts r348157 and r348155 to account for revert of r348154 in
clang repository.

llvm-svn: 348279
2018-12-04 16:30:31 +00:00
Simon Pilgrim
2c7ccb1b33 [X86][SSE] Add MOVMSK demandedbits/elts tests
llvm-svn: 348277
2018-12-04 16:01:25 +00:00
Sanjay Patel
8fd602d4df [InstCombine] auto-generate full checks for icmp overflow tests; NFC
llvm-svn: 348274
2018-12-04 15:41:34 +00:00
Sanjay Patel
e741cdac9f [InstCombine] add helper for icmp with dominator; NFC
There's a potential small enhancement to this code that could
solve the cases currently under proposal in D54827 via SimplifyCFG.

Whether instcombine should be doing this kind of semi-non-local
analysis in the first place is an open question, but separating
the logic out can only help if/when we decide to move it to a
different pass. 

AFAICT, any proposal to do this in SimplifyCFG could also be seen 
as an overreach + it would be incomplete to start the fold from a 
branch rather than an icmp.

There's another question here about the code for processUGT_ADDCST_ADD().
That part may be completely dead after rL234638 ?

llvm-svn: 348273
2018-12-04 15:35:17 +00:00
Sanjay Patel
c395dc9511 [InstCombine] auto-generate full checks for icmp dominator tests; NFC
llvm-svn: 348270
2018-12-04 15:00:35 +00:00
Krzysztof Parzyszek
dfa3199607 [Hexagon] Remove unused checker functions from asm parser
llvm-svn: 348269
2018-12-04 14:58:14 +00:00
Alina Sbirlea
bc8eee3bb9 [SimpleLoopUnswitch] Remove debug dump.
llvm-svn: 348267
2018-12-04 14:43:24 +00:00
Simon Pilgrim
175c94193b Add common check prefix. NFCI.
llvm-svn: 348265
2018-12-04 14:32:42 +00:00
Xing GUO
08fc71ca9f [yaml2obj] Move redundant statements into a separate static function
Reviewers: jhenderson, grimar

Reviewed By: jhenderson

Subscribers: jakehehrlich, llvm-commits

Differential Revision: https://reviews.llvm.org/D55220

llvm-svn: 348264
2018-12-04 14:27:51 +00:00
Alina Sbirlea
7f0355fada Update MemorySSA in SimpleLoopUnswitch.
Summary:
Teach SimpleLoopUnswitch to preserve MemorySSA.

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D47022

llvm-svn: 348263
2018-12-04 14:23:37 +00:00
Martell Malone
7e5a79b353 [GN][NFC] Update readme example to functional command
`ninja -C out/gn check-lld` is not a valid command yet

Differential revision: https://reviews.llvm.org/D54840

llvm-svn: 348259
2018-12-04 12:59:22 +00:00
Clement Courbet
cc92633a48 [X86][NFC] Add more constant-size memcmp tests.
llvm-svn: 348257
2018-12-04 12:35:51 +00:00
Simon Pilgrim
f953064f10 Fix MSVC "unknown pragma" warning. NFCI.
llvm-svn: 348256
2018-12-04 12:31:52 +00:00
Simon Pilgrim
dbfdba9405 Fix -Wparentheses warning. NFCI.
llvm-svn: 348254
2018-12-04 12:24:10 +00:00
Simon Pilgrim
513fbd00e4 [X86] Remove unnecessary peekThroughEXTRACT_SUBVECTORs call.
The GetSplatValue/IsSplatVector call will call this anyhow and the later code is just for a v2i64 type so doesn't need it.

llvm-svn: 348253
2018-12-04 12:21:43 +00:00
Simon Pilgrim
5e25d966f6 [TargetLowering] expandFP_TO_UINT - avoid FPE due to out of range conversion (PR17686)
PR17686 demonstrates that for some targets FP exceptions can fire in cases where the FP_TO_UINT is expanded using a FP_TO_SINT instruction.

The existing code converts both the inrange and outofrange cases using FP_TO_SINT and then selects the result, this patch changes this for 'strict' cases to pre-select the FP_TO_SINT input and the offset adjustment.

The X87 cases don't need the strict flag but generates much nicer code with it....

Differential Revision: https://reviews.llvm.org/D53794

llvm-svn: 348251
2018-12-04 11:21:30 +00:00
Simon Pilgrim
5f2f923973 Revert rL348121 from llvm/trunk: [NFC][AArch64] Split out backend features
This patch splits backend features currently
hidden behind architecture versions.

For example, currently the only way to activate
complex numbers extension is targeting an v8.3
architecture, where after the patch this extension
can be added separately.

This refactoring is required by the new command lines proposal:
http://lists.llvm.org/pipermail/llvm-dev/2018-September/126346.html

Reviewers: DavidSpickett, olista01, t.p.northover

Subscribers: kristof.beyls, bryanpkc, javed.absar, pbarrio

Differential revision: https://reviews.llvm.org/D54633

........

This has been causing buildbots failures for the past 24 hours: http://lab.llvm.org:8011/builders/llvm-clang-x86_64-expensive-checks-win/builds/14386

llvm-svn: 348249
2018-12-04 10:55:48 +00:00