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Author SHA1 Message Date
Jakob Stoklund Olesen
3a19b732d8 Replace the tablegen RegisterClass field SubRegClassList with an alist-like data 
structure that represents a mapping without any dependencies on SubRegIndex
numbering.

This brings us closer to being able to remove the explicit SubRegIndex
numbering, and it is now possible to specify any mapping without inventing
*_INVALID register classes.

llvm-svn: 104563
 2010-05-24 21:46:58 +00:00
Evan Cheng
e34814c0bc Avoid adding duplicate function live-in's. 
llvm-svn: 104560
 2010-05-24 21:33:37 +00:00
Dan Gohman
824858ebb0 Fix an mmx movd encoding. 
llvm-svn: 104552
 2010-05-24 20:51:08 +00:00
Kevin Enderby
a911679139 MC/X86: Add aliases for CMOVcc variants. 
llvm-svn: 104549
 2010-05-24 20:32:23 +00:00
Bob Wilson
e6a30dc530 Clean up some extra whitespace. 
llvm-svn: 104544
 2010-05-24 20:08:34 +00:00
Bob Wilson
c71b7c8c61 Thumb2 RSBS instructions were being printed without the 'S' suffix. 
Fix it by changing the T2I_rbin_s_is multiclass to handle the CPSR
output and 'S' suffix in the same way as T2I_bin_s_irs.

llvm-svn: 104531
 2010-05-24 18:44:06 +00:00
Devang Patel
345bc8667e Do not emit line number entries for unknown debug values. 
This fixes recent regression in store.exp from gdb testsuite.

llvm-svn: 104524
 2010-05-24 18:26:49 +00:00
Evan Cheng
9b011e343c LR is in GPR, not tGPR even in Thumb1 mode. 
llvm-svn: 104518
 2010-05-24 18:00:18 +00:00
Jakob Stoklund Olesen
4f2bfd8451 Add SubRegIndex defs to PowerPC. It looks like the CR subregister indices are 
never used.

llvm-svn: 104517
 2010-05-24 17:55:38 +00:00
Jakob Stoklund Olesen
26bb6fd4f2 Use SubRegIndex in SystemZ. 
Anton, please review the change to SystemZAsmPrinter.cpp. It could be a bug.

llvm-svn: 104515
 2010-05-24 17:43:01 +00:00
Jakob Stoklund Olesen
7c5127a0c6 SubRegIndex'ize Mips 
llvm-svn: 104514
 2010-05-24 17:42:58 +00:00
Jakob Stoklund Olesen
6d971535b8 SubRegIndex'ize MSP430 
llvm-svn: 104513
 2010-05-24 17:42:55 +00:00
Jakob Stoklund Olesen
d48a2f5afd Fix a few places that depended on the numeric value of subreg indices. 
Add assertions in places that depend on consecutive indices.

llvm-svn: 104510
 2010-05-24 17:13:28 +00:00
Jakob Stoklund Olesen
ac6f519e79 Switch ARMRegisterInfo.td to use SubRegIndex and eliminate the parallel enums 
from ARMRegisterInfo.h

llvm-svn: 104508
 2010-05-24 16:54:32 +00:00
Jakob Stoklund Olesen
f40bb16b94 Rename X86 subregister indices to something shorter. 
Use the tablegen-produced enums.

llvm-svn: 104493
 2010-05-24 14:48:17 +00:00
Jakob Stoklund Olesen
9a54fec092 Add the SubRegIndex TableGen class. 
This is the beginning of purely symbolic subregister indices, but we need a bit
of jiggling before the explicit numeric indices can be completely removed.

llvm-svn: 104492
 2010-05-24 14:48:12 +00:00
Nicolas Geoffray
803f2761ec Encode the Caml frametable by following what the comment says: the number of descriptors 
is first emitted, and StackOffsets are emitted in 16 bits.

llvm-svn: 104488
 2010-05-24 12:24:11 +00:00
Duncan Sands
f2bec8edf6 Apply timeouts and memory limits in more places. In particular, when 
bugpoint does "Running the code generator to test for a crash" this
gets you a crash if llc goes into an infinite loop or uses up vast
amounts of memory.

llvm-svn: 104485
 2010-05-24 07:49:55 +00:00
Daniel Dunbar
5bef2f5031 llvm-mc: Use EmitIntValue where possible, which makes the API calls from the AsmParser and CodeGen line up better. 
llvm-svn: 104467
 2010-05-23 18:36:38 +00:00
Daniel Dunbar
e87e067d2c llvm-mc: Use AddBlankLine in asm parser. This makes transliteration match the input much more closely, and also makes the API calls from the AsmParser and CodeGen line up better. 
llvm-svn: 104466
 2010-05-23 18:36:34 +00:00
Daniel Dunbar
eb23d9ac22 MC: Add an MCLoggingStreamer, for use in debugging integrated-as mismatches. 
llvm-svn: 104463
 2010-05-23 17:44:06 +00:00
Bob Wilson
c7efe760d6 VDUP doesn't support vectors with 64-bit elements. 
llvm-svn: 104455
 2010-05-23 05:42:31 +00:00
Daniel Dunbar
50265dbaf0 MC/X86: Subdivide immediates a bit more, so that we properly recognize immediates based on the width of the target instruction. For example: 
addw $0xFFFF, %ax
should match the same as
  addw $-1, %ax
but we used to match it to the longer encoding.

llvm-svn: 104453
 2010-05-22 21:02:33 +00:00
Daniel Dunbar
ee525943d8 tblgen/AsmMatcher: Change AsmOperandClass to allow a list of superclasses instead of just one. 
llvm-svn: 104452
 2010-05-22 21:02:29 +00:00
Daniel Dunbar
7c60f7caa2 MC/X86: Add alias for setz, setnz, jz, jnz. 
llvm-svn: 104435
 2010-05-22 06:37:33 +00:00
John Mosby
cec9b7fc9c Trivial change to dump() function for SparseBitVector 
llvm-svn: 104433
 2010-05-22 05:13:17 +00:00
Evan Cheng
241d2c434e Implement @llvm.returnaddress. rdar://8015977. 
llvm-svn: 104421
 2010-05-22 01:47:14 +00:00
Jim Grosbach
b6cc69c655 Implement eh.sjlj.longjmp for ARM. Clean up the intrinsic a bit. 
Followups: docs patch for the builtin and eh.sjlj.setjmp cleanup to match
longjmp.

llvm-svn: 104419
 2010-05-22 01:06:18 +00:00
Eric Christopher
189eca1291 This test is darwin only. Make it so(tm). 
llvm-svn: 104418
 2010-05-22 00:55:55 +00:00
Bob Wilson
b8ebb375b6 Recognize more BUILD_VECTORs and VECTOR_SHUFFLEs that can be implemented by 
copying VFP subregs.  This exposed a bunch of dead code in the *spill-q.ll
tests, so I tweaked those tests to keep that code from being optimized away.
Radar 7872877.

llvm-svn: 104415
 2010-05-22 00:23:12 +00:00
Eric Christopher
165bcdf8a8 Add full bss data support for darwin tls variables. 
llvm-svn: 104414
 2010-05-22 00:10:22 +00:00
Devang Patel
e611375617 Collect variable information during endFunction() instead of beginFunction(). 
llvm-svn: 104412
 2010-05-22 00:04:14 +00:00
Eric Christopher
6bd67791da Add a new section and accessor for TLS data. 
llvm-svn: 104411
 2010-05-22 00:00:58 +00:00
Bob Wilson
3994f42952 Clean up extra whitespace. 
llvm-svn: 104410
 2010-05-21 23:53:55 +00:00
Eric Christopher
8f296fd844 Make this LookAheadLimit, not the uninitialized LookAheadLeft. 
Evan please verify!

llvm-svn: 104408
 2010-05-21 23:40:03 +00:00
Chris Lattner
d5c391bba6 add a note 
llvm-svn: 104404
 2010-05-21 23:16:21 +00:00
Eric Christopher
d250f449cb Expand on comment. 
llvm-svn: 104396
 2010-05-21 23:03:53 +00:00
Kevin Enderby
1e4a4f5899 Added retl for 32-bit x86 and added retq for 64-bit x86. 
llvm-svn: 104394
 2010-05-21 23:01:38 +00:00
Eric Christopher
0df4e8b6a5 Fix comment and whitespace. 
llvm-svn: 104392
 2010-05-21 22:39:11 +00:00
Chris Lattner
d96398e6b4 expand on the llvm ir bitcode dox. Patch by Peter Housel! 
llvm-svn: 104391
 2010-05-21 22:20:54 +00:00
Evan Cheng
6a0784954a Allow machine cse to cse instructions which define physical registers. Controlled by option -machine-cse-phys-defs. 
llvm-svn: 104385
 2010-05-21 21:22:19 +00:00
Eric Christopher
5fc9256574 Fix section attribute name. 
llvm-svn: 104381
 2010-05-21 21:08:52 +00:00
Bob Wilson
586811b244 Change CodeGen/ARM/2009-11-02-NegativeLane.ll to use 16-bit vector elements 
so that it will continue to test what it was meant to test when I commit a
separate change for better support of BUILD_VECTOR and VECTOR_SHUFFLE for Neon.
Fix a DAG combiner crash exposed by this test change.

llvm-svn: 104380
 2010-05-21 21:05:32 +00:00
Evan Cheng
3c850aecf6 - Change MachineInstr::findRegisterDefOperandIdx so it can also look for defs 
that are aliases of the specified register.
- Rename modifiesRegister to definesRegister since it's looking a def of the
specific register or one of its super-registers. It's not looking for def of a
sub-register or alias that could change the specified register.
- Added modifiesRegister to look for defs of aliases.

llvm-svn: 104377
 2010-05-21 20:53:24 +00:00
Jakob Stoklund Olesen
0f1087b284 Add MachineInstr::readsWritesVirtualRegister() to determine if an instruction 
reads or writes a register.

This takes partial redefines and undef uses into account.

Don't actually use it yet. That caused miscompiles.

llvm-svn: 104372
 2010-05-21 20:02:01 +00:00
Devang Patel
e8f686625e Simplify 
llvm-svn: 104338
 2010-05-21 18:49:09 +00:00
Dale Johannesen
787ace240c Previous commit message should refer to 104308. 
llvm-svn: 104337
 2010-05-21 18:44:47 +00:00
Dale Johannesen
38109a0b04 Fix two bugs in 104348: 
Case where MMX is disabled wasn't handled right.
MMX->MMX bitconverts are Legal.

llvm-svn: 104336
 2010-05-21 18:40:15 +00:00
Nathan Jeffords
28b485543b added an assertion to MCObjectWriter::WriteBytes to catch misuse of the ZeroFillSize parameter 
If the size of the string is greater than the zero fill size, the function will attempt to write a very large string of zeros to the object file (~4GB on 32 bit platforms). This assertion will catch the scenario and crash the program before the write occurs.

llvm-svn: 104334
 2010-05-21 18:23:56 +00:00
Chris Lattner
4c14d2c4a4 now that fp reg kill insertion stuff happens as a separate 
pass after isel instead of being interlaced with it, we can
trust that all the code for a function has been isel'd before
it is run.

The practical impact of this is that we can scan for machine
instr phis instead of doing a fuzzy match on the LLVM BB for
phi nodes.  Doing the fuzzy match required knowing when isel
would produce an fp reg stack phi which was gross.  It was
also wrong in cases where select got lowered to a branch
tree because cmovs aren't available (PR6828).

Just do the scan on machine phis which is simpler, faster
and more correct.  This fixes PR6828.

llvm-svn: 104333
 2010-05-21 18:17:54 +00:00