David Goodwin
6fa63db9be
Fix typo in addrmode definition.
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llvm-svn: 76806
2009-07-22 22:24:31 +00:00
Evan Cheng
268b47b1fb
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
David Goodwin
1a6f4f6f8d
Predicate VFP instructions on HasVFP2 instead of IsARM. This allows VFP instructions with thumb-2.
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llvm-svn: 75254
2009-07-10 17:03:29 +00:00
Evan Cheng
991f885915
- Add some NEON ld / st instruction static encoding.
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- Make bits 25-27 for ldrh, etc. explicitly zero. Previously only the JIT uses the encoding information and it's assuming anything not specified to be zero. Making them explicit so the disassembler is happy.
Patch by Sean Callanan.
llvm-svn: 75065
2009-07-08 22:51:32 +00:00
Bob Wilson
3809b333de
Implement NEON vld1 instructions.
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llvm-svn: 75019
2009-07-08 18:11:30 +00:00
Evan Cheng
18d70ca551
Add a Thumb2 instruction flag to that indicates whether the instruction can be transformed to 16-bit variant.
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llvm-svn: 74988
2009-07-08 01:46:35 +00:00
Evan Cheng
dad6a41d14
Thumb2 pre/post indexed loads.
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llvm-svn: 74696
2009-07-02 07:28:31 +00:00
Evan Cheng
57bb186a0c
Change the meaning of predicate hasThumb2 to mean thumb2 ISA is available, not that it's in thumb mode and thumb2 is available. Added isThumb2 predicate to replace the old predicate.
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llvm-svn: 74692
2009-07-02 06:38:40 +00:00
Bob Wilson
810a970c6f
Add a new addressing mode for NEON load/store instructions.
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llvm-svn: 74658
2009-07-01 23:16:05 +00:00
David Goodwin
5545d82866
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
Evan Cheng
093adf3ff9
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Evan Cheng
817712377a
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Evan Cheng
a3be8cba60
Change thumb2 instruction definitions so if-converter so add predicate operands and / or flip the 's' bit to set the condition flag.
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llvm-svn: 74158
2009-06-25 02:08:06 +00:00
Evan Cheng
1333ee8eb6
Add IsThumb1Only to most 16-bit thumb instructions since we want to isel 32-bit instructions when they are available.
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llvm-svn: 73985
2009-06-23 19:38:13 +00:00
Evan Cheng
3e8033f7f7
Initial Thumb2 support. Majority of the work is done by David Goodwin. There are
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also some contribution from Jim Grosbach, Bob Wilson, and Evan Cheng.
I've done my best to consolidate the patches with those that were done by
Viktor Kutuzov and Anton Korzh from Access Softek, Inc. Let me know if missed
anything. I've completely reorganized the thumb2 td file, made more extensive
uses of multiclass, etc.
Test cases will be contributed later after I re-organize what's in svn first.
llvm-svn: 73965
2009-06-23 17:48:47 +00:00
Bob Wilson
6db76aaf10
Add support for ARM's Advanced SIMD (NEON) instruction set.
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This is still a work in progress but most of the NEON instruction set
is supported.
llvm-svn: 73919
2009-06-22 23:27:02 +00:00
Evan Cheng
f7c1da41a1
Handle the rest of pseudo instructions.
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llvm-svn: 59275
2008-11-13 23:36:57 +00:00
Evan Cheng
3c0113820b
Fix pre- and post-indexed load / store encoding bugs.
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llvm-svn: 59230
2008-11-13 07:34:59 +00:00
Evan Cheng
7fef8cfe75
Consolidate formats; fix FCMPED etc. encodings.
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llvm-svn: 59107
2008-11-12 07:18:38 +00:00
Evan Cheng
0966883093
Fix VFP conversion instruction encodings.
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llvm-svn: 59104
2008-11-12 06:41:41 +00:00
Evan Cheng
8b7fefc126
Fix FMDRR encoding.
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llvm-svn: 59088
2008-11-11 22:46:12 +00:00
Evan Cheng
35f1477c5a
Encode VFP load / store instructions.
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llvm-svn: 59084
2008-11-11 21:48:44 +00:00
Evan Cheng
91e4ef91c5
Encode VFP conversion instructions.
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llvm-svn: 59074
2008-11-11 19:40:26 +00:00
Evan Cheng
3c62bb7471
Encode VFP arithmetic instructions.
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llvm-svn: 59016
2008-11-11 02:11:05 +00:00
Evan Cheng
21df9f3b4f
Jump table JIT support. Work in progress.
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llvm-svn: 58836
2008-11-07 09:06:08 +00:00
Evan Cheng
88726d85eb
Encode misc arithmetic instructions.
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llvm-svn: 58828
2008-11-07 01:41:35 +00:00
Evan Cheng
3bcb71912f
Encode extend instructions; more clean up.
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llvm-svn: 58818
2008-11-06 22:15:19 +00:00
Evan Cheng
af54e4ed18
- Improve naming consistency: Branch -> BrFrm, BranchMisc -> BrMiscFrm.
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- Consolidate instruction formats.
- Other clean up.
llvm-svn: 58808
2008-11-06 17:48:05 +00:00
Evan Cheng
aa24d19533
Remove opcode from instruction TS flags; add MOVCC support; fix addrmode3 encoding bug.
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llvm-svn: 58800
2008-11-06 08:47:38 +00:00
Evan Cheng
078361bddc
Handle smul<x><y>, smulw<y>, smla<x><y>, smlaw<y>.
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llvm-svn: 58793
2008-11-06 03:35:07 +00:00
Evan Cheng
ca6759021b
Fix encoding of multiple instructions with 3 src operands; also handle smmul, smmla, and smmls.
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llvm-svn: 58789
2008-11-06 01:21:28 +00:00
Evan Cheng
ce97712aa6
Encode pic load / store instructions; fix some encoding bugs.
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llvm-svn: 58780
2008-11-05 23:22:34 +00:00
Evan Cheng
9970c31dcf
Restructure ARM code emitter to use instruction formats instead of addressing modes to determine how to encode instructions.
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llvm-svn: 58764
2008-11-05 18:35:52 +00:00
Evan Cheng
088f7c51a4
LDM_RET restores pc, do not set 's' bit which would restore CPSR from SPSR.
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llvm-svn: 58707
2008-11-04 17:57:07 +00:00
Jim Grosbach
5262898365
Add binary encoding support for multiply instructions. Some blanks left to fill in, but the basics are there.
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llvm-svn: 58626
2008-11-03 18:38:31 +00:00
Jim Grosbach
d0ff59ec42
Update ARM Insn encoding to get endian-ness to match the documentation (31-0 left to right)
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llvm-svn: 57524
2008-10-14 20:36:24 +00:00
Evan Cheng
f2c04a10e6
Fix addrmode1 instruction encodings; fix bx_ret encoding.
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llvm-svn: 56277
2008-09-17 07:53:38 +00:00
Evan Cheng
d268288d39
Specify instruction encoding using range list to avoid endianess issues.
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llvm-svn: 56276
2008-09-17 07:16:21 +00:00
Evan Cheng
0a3a595612
Revert 56176. All those instruction formats are still needed.
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llvm-svn: 56180
2008-09-13 01:35:33 +00:00
Evan Cheng
18fd8337b3
Eliminate unnecessary instruction formats.
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llvm-svn: 56176
2008-09-12 23:15:39 +00:00
Evan Cheng
66e7651a16
Addrmode 1 S bit can be dynamically set. Look for CPSR def.
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llvm-svn: 56172
2008-09-12 22:45:55 +00:00
Evan Cheng
738426a2a1
Control flow instruction encodings.
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llvm-svn: 55601
2008-09-01 08:25:56 +00:00
Evan Cheng
36170e63a3
ldm / stm instruction encodings.
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llvm-svn: 55599
2008-09-01 07:48:18 +00:00
Evan Cheng
01019d7909
AXI2 and AXI3 instruction encodings.
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llvm-svn: 55598
2008-09-01 07:34:13 +00:00
Evan Cheng
fdae49e627
Reorganize instruction formats again; AXI1 encoding.
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llvm-svn: 55597
2008-09-01 07:19:00 +00:00
Evan Cheng
26305b192f
addrmode3 instruction encodings.
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llvm-svn: 55596
2008-09-01 07:00:14 +00:00
Evan Cheng
eb40cb3e42
Reorganize some instruction format definitions. No functionality change.
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llvm-svn: 55594
2008-09-01 01:51:14 +00:00
Evan Cheng
fa095aec1e
Rest of addrmode2 instruction encodings.
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llvm-svn: 55593
2008-09-01 01:27:33 +00:00
Evan Cheng
4c8338c0d3
Addr2 word / byte load encodings.
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llvm-svn: 55591
2008-08-31 19:02:21 +00:00