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2790 Commits

Author SHA1 Message Date
Evan Cheng
3bd61a0be5 Use MachineConstantPoolEntry getOffset() and getType() accessors. 
llvm-svn: 30326
 2006-09-14 07:35:00 +00:00
Evan Cheng
58d454a49e A MachineConstantPool may have mixed Constant* and MachineConstantPoolValue* values. 
llvm-svn: 30316
 2006-09-14 05:50:57 +00:00
Chris Lattner
fdf4c06dac If LSR went through a lot of trouble to put constants (e.g. the addr of a global 
in a specific BB, don't undo this!).  This allows us to compile
CodeGen/X86/loop-hoist.ll into:

_foo:
        xorl %eax, %eax
***     movl L_Arr$non_lazy_ptr, %ecx
        movl 4(%esp), %edx
LBB1_1: #cond_true
        movl %eax, (%ecx,%eax,4)
        incl %eax
        cmpl %edx, %eax
        jne LBB1_1      #cond_true
LBB1_2: #return
        ret

instead of:

_foo:
        xorl %eax, %eax
        movl 4(%esp), %ecx
LBB1_1: #cond_true
***     movl L_Arr$non_lazy_ptr, %edx
        movl %eax, (%edx,%eax,4)
        incl %eax
        cmpl %ecx, %eax
        jne LBB1_1      #cond_true
LBB1_2: #return
        ret

This was noticed in 464.h264ref.  This doesn't usually affect PPC,
but strikes X86 all the time.

llvm-svn: 30290
 2006-09-13 06:02:42 +00:00
Chris Lattner
81566af673 Compile X << 1 (where X is a long-long) to: 
addl %ecx, %ecx
        adcl %eax, %eax

instead of:

        movl %ecx, %edx
        addl %edx, %edx
        shrl $31, %ecx
        addl %eax, %eax
        orl %ecx, %eax

and to:

        addc r5, r5, r5
        adde r4, r4, r4

instead of:

        slwi r2,r9,1
        srwi r0,r11,31
        slwi r3,r11,1
        or r2,r0,r2

on PPC.

llvm-svn: 30284
 2006-09-13 03:50:39 +00:00
Evan Cheng
499d77553a Added support for machine specific constantpool values. These are useful for 
representing expressions that can only be resolved at link time, etc.

llvm-svn: 30278
 2006-09-12 21:00:35 +00:00
Nate Begeman
1109e4a222 Behold, more work on relocations. Things are looking pretty good now. 
llvm-svn: 30240
 2006-09-10 23:03:44 +00:00
Chris Lattner
480465a171 This code was trying too hard. By eliminating redundant edges in the CFG 
due to switch cases going to the same place, it make #pred != #phi entries,
breaking live interval analysis.

This fixes 458.sjeng on x86 with llc.

llvm-svn: 30236
 2006-09-10 06:36:57 +00:00
Chris Lattner
b935214653 Implement the fpowi now by lowering to a libcall 
llvm-svn: 30225
 2006-09-09 06:03:30 +00:00
Chris Lattner
8536526496 Allow targets to custom lower expanded BIT_CONVERT's 
llvm-svn: 30217
 2006-09-09 00:20:27 +00:00
Nate Begeman
2dfa13e74f First pass at supporting relocations. Relocations are written correctly to 
the file now, however the relocated address is currently wrong.  Fixing
that will require some deep pondering.

llvm-svn: 30207
 2006-09-08 22:42:09 +00:00
Chris Lattner
d269774664 Non-allocatable physregs can be killed and dead, but don't treat them as 
safe for later allocation.  This fixes McCat/18-imp with llc-beta.

llvm-svn: 30204
 2006-09-08 20:21:31 +00:00
Chris Lattner
a531dd1879 This fixes Benchmarks/Prolangs-C/unix-smail 
llvm-svn: 30198
 2006-09-08 19:11:11 +00:00
Chris Lattner
16e4937a31 Fix a bunch of llc-beta failures on x86 yesterday. Don't allow selection 
of unallocatable registers, just because an alias is allocatable.  We were
picking registers like SIL just because ESI was being used.

llvm-svn: 30197
 2006-09-08 19:03:30 +00:00
Jim Laskey
9da25f6119 Make target asm info a property of the target machine. 
llvm-svn: 30162
 2006-09-07 22:06:40 +00:00
Evan Cheng
fe263e552a Fix pasto that was breaking x86 tests. 
llvm-svn: 30151
 2006-09-07 18:50:20 +00:00
Chris Lattner
8b75d6e068 Fix CodeGen/Generic/2006-09-06-SwitchLowering.ll, a bug where SDIsel inserted 
too many phi operands when lowering a switch to branches in some cases.

llvm-svn: 30142
 2006-09-07 01:59:34 +00:00
Jim Laskey
6b86ef852c Separate target specific asm properties from the asm printers. 
llvm-svn: 30126
 2006-09-06 18:34:40 +00:00
Evan Cheng
82fabe541b Only call isUse/isDef on register operands 
llvm-svn: 30122
 2006-09-05 20:32:06 +00:00
Chris Lattner
0fad1515ee Only call isUse/isDef on register operands 
llvm-svn: 30118
 2006-09-05 20:19:27 +00:00
Chris Lattner
5c74b99a20 Don't call isDef on non-registers 
llvm-svn: 30117
 2006-09-05 20:02:51 +00:00
Chris Lattner
5f36aaa98f Change the default to 0, which means 'default'. 
llvm-svn: 30114
 2006-09-05 17:39:15 +00:00
Chris Lattner
9cd4e3429e Completely eliminate def&use operands. Now a register operand is EITHER a 
def operand or a use operand.

llvm-svn: 30109
 2006-09-05 02:31:13 +00:00
Chris Lattner
59a4d8dfcd Fix a long-standing wart in the code generator: two-address instruction lowering 
actually *removes* one of the operands, instead of just assigning both operands
the same register.  This make reasoning about instructions unnecessarily complex,
because you need to know if you are before or after register allocation to match
up operand #'s with the target description file.

Changing this also gets rid of a bunch of hacky code in various places.

This patch also includes changes to fold loads into cmp/test instructions in
the X86 backend, along with a significant simplification to the X86 spill
folding code.

llvm-svn: 30108
 2006-09-05 02:12:02 +00:00
Chris Lattner
b26f7cd68a Correct fix for a crasher on functions with live in values 
llvm-svn: 30099
 2006-09-04 18:27:40 +00:00
Chris Lattner
ae9537991c Hack around a regression I introduced yesterday 
llvm-svn: 30098
 2006-09-04 18:20:15 +00:00
Duraid Madina
e1bb6d9ff8 forgot this 
llvm-svn: 30097
 2006-09-04 07:44:11 +00:00
Duraid Madina
51396ffd3e add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Chris Lattner
93ed29cb5d new file 
llvm-svn: 30082
 2006-09-04 04:16:09 +00:00
Chris Lattner
b590a41f7b Avoid beating on the mi2i map when we know the answer already. 
llvm-svn: 30066
 2006-09-03 08:07:11 +00:00
Chris Lattner
4890186e93 minor speedup 
llvm-svn: 30065
 2006-09-03 07:53:50 +00:00
Chris Lattner
ff7657a869 Fix Regression/CodeGen/Generic/2006-09-02-LocalAllocCrash.ll on X86. 
Just because an alias of a register is available, it doesn't mean that we
can arbitrarily evict the register.

llvm-svn: 30064
 2006-09-03 07:15:37 +00:00
Chris Lattner
2a9da0da7b When deleting a machine instruction, make sure to remove it from the 
livevariables information.  This fixes several regalloc=local failures on x86

llvm-svn: 30062
 2006-09-03 00:06:08 +00:00
Chris Lattner
cc5b4bff8f Move two methods out of line, make them work when the record for a machine 
instruction includes physregs.

llvm-svn: 30061
 2006-09-03 00:05:09 +00:00
Chris Lattner
d4cc3dbac4 improve compat with certain versions of GCC (on cygwin?) 
llvm-svn: 30054
 2006-09-02 17:37:30 +00:00
Chris Lattner
dfda549a00 Iteration is required for some cases, even if they don't occur in crafty. 
Restore it, which re-fixes X86/2006-08-21-ExtraMovInst.ll

llvm-svn: 30050
 2006-09-02 05:32:53 +00:00
Chris Lattner
382e699e59 When joining two intervals where the RHS is really simple, use a light-weight 
method for joining the live ranges instead of the fully-general one.

llvm-svn: 30049
 2006-09-02 05:26:59 +00:00
Evan Cheng
464ef8dc53 Allow legalizer to expand ISD::MUL using only MULHS in the rare case that is 
possible and the target only supports MULHS.

llvm-svn: 30022
 2006-09-01 18:17:58 +00:00
Jim Laskey
2f8c98b9b1 Corrections. 
llvm-svn: 30021
 2006-09-01 12:55:05 +00:00
Chris Lattner
fc38415ddc Pull some code out of a hot recursive function because the common case doesn't 
need recursion.

llvm-svn: 30015
 2006-09-01 07:00:23 +00:00
Chris Lattner
2aef97494c Reserve space in the ValueNumberInfo vector. This speeds up live interval 
analysis 16% on crafty.

Wrap long lines.

llvm-svn: 30012
 2006-09-01 06:10:18 +00:00
Chris Lattner
0c120af606 Iterative coallescing doesn't buy us anything (we get identical results on 
crafty with and without it).  Removing it speeds up live intervals 6%.

llvm-svn: 30010
 2006-09-01 04:02:42 +00:00
Evan Cheng
b2933f3f52 DAG combiner fix for rotates. Previously the outer-most condition checks 
for ROTL availability. This prevents it from forming ROTR for targets that
has ROTR only.

llvm-svn: 29997
 2006-08-31 07:41:12 +00:00
Chris Lattner
fbb467f738 Add a special case that speeds up coallescing a bit, but not enough. 
llvm-svn: 29996
 2006-08-31 06:48:26 +00:00
Chris Lattner
1020604f2c Delete copies as they are coallesced instead of waiting until the end. 
llvm-svn: 29995
 2006-08-31 05:58:59 +00:00
Chris Lattner
998dd9b42e avoid calling the virtual isMoveInstr method endlessly by caching its results. 
llvm-svn: 29994
 2006-08-31 05:54:43 +00:00
Chris Lattner
44b10a80c3 Fix a compiler crash bootstrapping llvm-gcc. 
llvm-svn: 29989
 2006-08-30 23:02:29 +00:00
Chris Lattner
3a4d512930 Teach the coallescer to coallesce live intervals joined by an arbitrary 
number of copies, potentially defining live ranges that appear to have
differing value numbers that become identical when coallsced.  Among other
things, this fixes CodeGen/X86/shift-coalesce.ll and PR687.

llvm-svn: 29968
 2006-08-29 23:18:15 +00:00
Jim Laskey
d44e9493e6 Handle callee saved registers in dwarf frame info (lead up to exception 
handling.)

llvm-svn: 29954
 2006-08-29 16:24:26 +00:00
Evan Cheng
2335c819cd Move isCommutativeBinOp from SelectionDAG.cpp and DAGCombiner.cpp out. Make it a static method of SelectionDAG. 
llvm-svn: 29951
 2006-08-29 06:42:35 +00:00
Chris Lattner
a39dcb5377 eliminate RegisterOpt. It does the same thing as RegisterPass. 
llvm-svn: 29925
 2006-08-27 22:42:52 +00:00