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7465 Commits

Author SHA1 Message Date
Dan Gohman
3c7e8160f6 Add a new register class to describe operands that can't be SP, 
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.

llvm-svn: 77565
 2009-07-30 01:56:29 +00:00
Evan Cheng
31ac181755 tbb / tbh instructions only branch forward, not backwards. 
llvm-svn: 77522
 2009-07-29 23:20:20 +00:00
Evan Cheng
fabbd6219a Add VFP3 D registers to the DPR register class. 
llvm-svn: 77521
 2009-07-29 23:03:41 +00:00
Devang Patel
d5b7c64109 Read and write NamedMDNode. 
llvm-svn: 77517
 2009-07-29 22:34:41 +00:00
Daniel Dunbar
89cb72a6bc Fix PR4645 which was fallout from the fix for PR4641. 
- Call RAUW to delete all instructions (this is a patch from Nick Lewycky).

llvm-svn: 77512
 2009-07-29 22:00:43 +00:00
Evan Cheng
9712360f80 xfail for now. 
llvm-svn: 77478
 2009-07-29 17:40:28 +00:00
Bob Wilson
355e0b70e0 Change Neon VLDn intrinsics to return multiple values instead of really 
wide vectors.  Likewise, change VSTn intrinsics to take separate arguments
for each vector in a multi-vector struct.  Adjust tests accordingly.

llvm-svn: 77468
 2009-07-29 16:39:22 +00:00
Nick Lewycky
1961298b63 Just discard the output, no need to turn it back into text. 
llvm-svn: 77439
 2009-07-29 06:14:52 +00:00
Chris Lattner
e5f1099d05 don't dump .bc file to stdout, and simplify this to a trivial testcase. 
llvm-svn: 77436
 2009-07-29 05:32:07 +00:00
Chris Lattner
f8a9c2f843 fix PR4584 with a trivial patch now that the pieces are in place. 
llvm-svn: 77434
 2009-07-29 05:20:33 +00:00
Nick Lewycky
e0524c1795 Bulk erasing instructions without RAUWing them is unsafe. Instead, break them 
into a new BB that has no predecessors.

llvm-svn: 77433
 2009-07-29 05:17:50 +00:00
Evan Cheng
fc846dd401 Optimize Thumb2 jumptable to use tbb / tbh when all the offsets fit in byte / halfword. 
llvm-svn: 77422
 2009-07-29 02:18:14 +00:00
Eric Christopher
88c1b51020 Add a couple more tests for the ptest intrinsics to make sure we're 
grabbing them all correctly.

llvm-svn: 77413
 2009-07-29 00:51:15 +00:00
Eric Christopher
c7b97d1f03 Add support for gcc __builtin_ia32_ptest{z,c,nzc} intrinsics. Lower 
to ptest instruction plus setcc. Revamp ptest instruction. Add test.

llvm-svn: 77407
 2009-07-29 00:28:05 +00:00
Andreas Bolka
7d6b4c24e6 Slightly reformat LDA tests to ease grepping. 
llvm-svn: 77398
 2009-07-28 23:40:40 +00:00
Evan Cheng
cf483eb0c0 In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in). 
llvm-svn: 77364
 2009-07-28 20:53:24 +00:00
David Goodwin
0c9e96bf09 Remove support for ORN to workaround <rdar://problem/7096522>. 
llvm-svn: 77363
 2009-07-28 20:51:25 +00:00
David Goodwin
dbc23ece04 Add workaround for <rdar://problem/7098328>. 
llvm-svn: 77340
 2009-07-28 18:15:38 +00:00
Chris Lattner
a8faf6b1b6 fix testcase for previous patch. 
llvm-svn: 77338
 2009-07-28 18:04:18 +00:00
Chris Lattner
986bd2bd0a Fix PR4639, a ELF-TLS regression from some of my refactoring. 
llvm-svn: 77336
 2009-07-28 17:57:51 +00:00
David Goodwin
e94d490b89 Add Thumb-2 patterns for ARMsrl_flag and ARMsra_flag. 
llvm-svn: 77329
 2009-07-28 17:06:49 +00:00
Evan Cheng
05555a7d31 tADDrSPI doesn't have a predicate operand, but tADDhirr and tADDi3 have. 
llvm-svn: 77305
 2009-07-28 07:38:35 +00:00
Evan Cheng
b740190d2e - More refactoring. This gets rid of all of the getOpcode calls. 
- This change also makes it possible to switch between ARM / Thumb on a
  per-function basis.
- Fixed thumb2 routine which expand reg + arbitrary immediate. It was using
  using ARM so_imm logic.
- Use movw and movt to do reg + imm when profitable.
- Other code clean ups and minor optimizations.

llvm-svn: 77300
 2009-07-28 05:48:47 +00:00
Dan Gohman
0d0dd7b732 Teach instcombine to respect and preserve inbounds. Add inbounds 
to a few tests where it is required for the expected transformation.

llvm-svn: 77290
 2009-07-28 01:40:03 +00:00
David Goodwin
0bcb94eeff ORN does not require (and can not have) the ".w" suffix. "Orthogonality" is a dirty word at ARM. 
llvm-svn: 77275
 2009-07-27 23:34:12 +00:00
Daniel Dunbar
3edfc4bb16 llvm-mc: Implement .abort fully in the front end 
llvm-svn: 77272
 2009-07-27 23:20:52 +00:00
Dan Gohman
490eb36e1d Add a new keyword 'inbounds' for use with getelementptr. See the 
LangRef.html changes for details.

llvm-svn: 77259
 2009-07-27 21:53:46 +00:00
David Goodwin
471e9f5b8d Add ".w" suffix for wide thumb-2 instructions. 
llvm-svn: 77199
 2009-07-27 16:31:55 +00:00
Sanjiv Gupta
f39c96217b Test case to check that separate section is created for a global variable specified with section attribute. 
llvm-svn: 77195
 2009-07-27 16:20:41 +00:00
Dan Gohman
39c0d3b10a Change the assembly syntax for nsw, nuw, and exact, putting them 
after their associated opcodes rather than before. This makes them
a little easier to read.

llvm-svn: 77194
 2009-07-27 16:11:46 +00:00
Chris Lattner
19c9914343 update testcase. 
llvm-svn: 77192
 2009-07-27 15:52:58 +00:00
Chris Lattner
5547fd80ad put normal data into .data instead of .data.rel on elf systems. 
llvm-svn: 77116
 2009-07-26 03:06:11 +00:00
Chris Lattner
9cd489c7f1 finish simplifying DarwinTargetAsmInfo::SelectSectionForGlobal 
for now.  Make the section switching directives more consistent
by not including \n and including \t for them all.

llvm-svn: 77107
 2009-07-26 01:24:18 +00:00
Chris Lattner
b95150b65a simplify DarwinTargetAsmInfo::SelectSectionForGlobal a bit 
and make it more aggressive, we now put:

const int G2 __attribute__((weak)) = 42;

into the text (readonly) segment like gcc, previously we put
it into the data (readwrite) segment.

llvm-svn: 77104
 2009-07-26 00:51:36 +00:00
Bob Wilson
ec256c8938 Add support for ARM Neon VREV instructions. 
Patch by Anton Korzh, with some modifications from me.

llvm-svn: 77101
 2009-07-26 00:39:34 +00:00
Chris Lattner
cf7cc0ed7d add the most expedient hack to fix PR4619, along with a testcase. 
Thanks to Rafael for the great example.

llvm-svn: 77083
 2009-07-25 17:57:37 +00:00
Dan Gohman
c126330ef1 When attempting to sign-extend an addrec by interpreting 
the step value as unsigned, the start value and the addrec
itself still need to be treated as signed.

llvm-svn: 77078
 2009-07-25 16:03:30 +00:00
Chris Lattner
06449afe92 remove this test. It is currently failing because we now emit the string 
on darwin with ".cstring" instead of ".section  __TEXT,__cstring".  They
are the same and the former is better.  Remove this because this is no longer
magic pixie dust in the frontend.

llvm-svn: 77055
 2009-07-25 07:31:51 +00:00
Dan Gohman
13aabe2ba4 Teach ScalarEvolution to make use of no-overflow flags when 
analyzing add recurrences.

llvm-svn: 77034
 2009-07-25 01:22:26 +00:00
Evan Cheng
12dd5c078f I've lost my mind. PR4572 has not been fixed. 
llvm-svn: 77031
 2009-07-25 01:11:46 +00:00
Evan Cheng
d615e606c4 Change Thumb2 jumptable codegen to one that uses two level jumps: 
Before:
      adr r12, #LJTI3_0_0
      ldr pc, [r12, +r0, lsl #2]
LJTI3_0_0:
      .long    LBB3_24
      .long    LBB3_30
      .long    LBB3_31
      .long    LBB3_32

After:
      adr r12, #LJTI3_0_0
      add pc, r12, +r0, lsl #2
LJTI3_0_0:
      b.w    LBB3_24
      b.w    LBB3_30
      b.w    LBB3_31
      b.w    LBB3_32

This has several advantages.
1. This will make it easier to optimize this to a TBB / TBH instruction +
   (smaller) table.
2. This eliminate the need for ugly asm printer hack to force the address
   into thumb addresses (bit 0 is one).
3. Same codegen for pic and non-pic.
4. This eliminate the need to align the table so constantpool island pass
   won't have to over-estimate the size.

Based on my calculation, the later is probably slightly faster as well since
ldr pc with shifter address is very slow. That is, it should be a win as long
as the HW implementation can do a reasonable job of branch predict the second
branch.

llvm-svn: 77024
 2009-07-25 00:33:29 +00:00
Evan Cheng
bddff8fbe0 Remove a duplicated test. 
llvm-svn: 77020
 2009-07-25 00:24:40 +00:00
Evan Cheng
5faed6335e Forgot this test earlier. 
llvm-svn: 77007
 2009-07-24 22:42:45 +00:00
Evan Cheng
b8b61017e8 Fix these tests. 
llvm-svn: 77006
 2009-07-24 22:42:22 +00:00
Eli Friedman
11e86150c4 Fix assert assembling zero-argument constant GEP. 
There's still a strict-aliasing violation here, but I don't feel like 
dealing with that right now...

llvm-svn: 77005
 2009-07-24 21:56:17 +00:00
Eric Christopher
24a620ec3d Move insertps tests to sse41 combo test file, convert to filecheck 
format and add an extract/insert test.

llvm-svn: 76994
 2009-07-24 19:24:26 +00:00
Evan Cheng
bbac2397c5 Convert a test to FileCheck. 
llvm-svn: 76954
 2009-07-24 06:01:46 +00:00
Chris Lattner
09511ed243 Remove SectionKind::Small*. This was only used on mips, and is apparently 
a sad mistake that is regretted. :)

llvm-svn: 76935
 2009-07-24 03:11:51 +00:00
Richard Osborne
19591063fc Add tests for handling of globals and tls on the XCore. These currently fail 
but pass when run against r76652.

llvm-svn: 76923
 2009-07-24 00:38:20 +00:00
Dan Gohman
62c8b40b66 Remove the IA-64 backend. 
llvm-svn: 76920
 2009-07-24 00:30:09 +00:00