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Author SHA1 Message Date
Evan Cheng
e96f5af925 Add a pshufhw test case. 
llvm-svn: 27251
 2006-03-29 22:51:28 +00:00
Evan Cheng
d0d3eade59 Need to special case splat after all. Make the second operand of splat 
vector_shuffle undef.

llvm-svn: 27250
 2006-03-29 19:02:40 +00:00
Evan Cheng
0e323f1e49 Use unpcklpd for v2f64 splat. 
llvm-svn: 27249
 2006-03-29 18:59:48 +00:00
Evan Cheng
e7701928bb Floating point logical operation patterns should match bit_convert. Or else 
integer vector logical operations would match andp{s|d} instead of pand.

llvm-svn: 27248
 2006-03-29 18:47:40 +00:00
Evan Cheng
84c8b5bcd9 Add more SSE intrinsics 
llvm-svn: 27247
 2006-03-29 06:07:16 +00:00
Evan Cheng
02b5de9b3e - More shuffle related bug fixes. 
- Whenever possible use ops of the right packed types for vector shuffles /
  splats.

llvm-svn: 27246
 2006-03-29 03:04:49 +00:00
Evan Cheng
6e8b924416 Another entry about shuffles. 
llvm-svn: 27245
 2006-03-29 03:03:46 +00:00
Evan Cheng
5194a37602 - Only use pshufd for v4i32 vector shuffles. 
- Other shuffle related fixes.

llvm-svn: 27244
 2006-03-29 01:30:51 +00:00
Chris Lattner
1a773f8f18 add a note 
llvm-svn: 27243
 2006-03-29 00:24:13 +00:00
Chris Lattner
c8eb55d37d new testcase 
llvm-svn: 27242
 2006-03-29 00:12:08 +00:00
Chris Lattner
9a46d1605c Bug fixes: handle constantexpr insert/extract element operations 
Handle constantpacked vectors with constantexpr elements.

This fixes CodeGen/Generic/vector-constantexpr.ll

llvm-svn: 27241
 2006-03-29 00:11:43 +00:00
Evan Cheng
e7a50a5851 Added aliases to scalar SSE instructions, e.g. addss, to match x86 intrinsics. 
The source operands type are v4sf with upper bits passes through.
Added matching code for these.

llvm-svn: 27240
 2006-03-28 23:51:43 +00:00
Evan Cheng
178e36174a Fixing buggy code. 
llvm-svn: 27239
 2006-03-28 23:41:33 +00:00
Evan Cheng
86b5b7cf18 Don't sort the names before outputing the intrinsic name table. It causes a 
mismatch against the enum table.
This is a part of Sabre's master plan to drive me nuts with subtle bugs that
happens to only affect x86 be. :-)

llvm-svn: 27237
 2006-03-28 22:25:56 +00:00
Chris Lattner
95a8c4fb11 When building a VVECTOR_SHUFFLE node from extract_element operations, make 
sure to build it as SHUFFLE(X, undef, mask), not SHUFFLE(X, X, mask).

The later is not canonical form, and prevents the PPC splat pattern from
matching.  For a particular splat, we go from generating this:

	li r10, lo16(LCPI1_0)
	lis r11, ha16(LCPI1_0)
	lvx v3, r11, r10
	vperm v3, v2, v2, v3

to generating:

	vspltw v3, v2, 3

llvm-svn: 27236
 2006-03-28 22:19:47 +00:00
Chris Lattner
017e8f1798 Canonicalize VECTOR_SHUFFLE(X, X, Y) -> VECTOR_SHUFFLE(X,undef,Y') 
llvm-svn: 27235
 2006-03-28 22:11:53 +00:00
Chris Lattner
bd095fd427 new testcase 
llvm-svn: 27234
 2006-03-28 20:32:12 +00:00
Chris Lattner
a623f6f696 Turn a series of extract_element's feeding a build_vector into a 
vector_shuffle node.  For this:

void test(__m128 *res, __m128 *A, __m128 *B) {
  *res = _mm_unpacklo_ps(*A, *B);
}

we now produce this code:

_test:
        movl 8(%esp), %eax
        movaps (%eax), %xmm0
        movl 12(%esp), %eax
        unpcklps (%eax), %xmm0
        movl 4(%esp), %eax
        movaps %xmm0, (%eax)
        ret

instead of this:

_test:
        subl $76, %esp
        movl 88(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, (%esp)
        movaps %xmm0, 32(%esp)
        movss 4(%esp), %xmm0
        movss 32(%esp), %xmm1
        unpcklps %xmm0, %xmm1
        movl 84(%esp), %eax
        movaps (%eax), %xmm0
        movaps %xmm0, 16(%esp)
        movaps %xmm0, 48(%esp)
        movss 20(%esp), %xmm0
        movss 48(%esp), %xmm2
        unpcklps %xmm0, %xmm2
        unpcklps %xmm1, %xmm2
        movl 80(%esp), %eax
        movaps %xmm2, (%eax)
        addl $76, %esp
        ret

GCC produces this (with -fomit-frame-pointer):

_test:
        subl    $12, %esp
        movl    20(%esp), %eax
        movaps  (%eax), %xmm0
        movl    24(%esp), %eax
        unpcklps        (%eax), %xmm0
        movl    16(%esp), %eax
        movaps  %xmm0, (%eax)
        addl    $12, %esp
        ret

llvm-svn: 27233
 2006-03-28 20:28:38 +00:00
Chris Lattner
c6e37432b5 Teach Legalize how to pack VVECTOR_SHUFFLE nodes into VECTOR_SHUFFLE nodes. 
llvm-svn: 27232
 2006-03-28 20:24:43 +00:00
Chris Lattner
5b8467460a new node 
llvm-svn: 27231
 2006-03-28 19:54:42 +00:00
Chris Lattner
83ec289ebf Add a new node 
llvm-svn: 27230
 2006-03-28 19:54:11 +00:00
Chris Lattner
cad173698d Don't crash on X^X if X is a vector. Instead, produce a vector of zeros. 
llvm-svn: 27229
 2006-03-28 19:11:05 +00:00
Chris Lattner
6af8c19e4f Add an assertion 
llvm-svn: 27228
 2006-03-28 19:04:49 +00:00
Chris Lattner
93559450b8 add a note 
llvm-svn: 27227
 2006-03-28 18:56:23 +00:00
Jim Laskey
4c2d4d1912 Refactor address attributes. Add base register to frame info. 
llvm-svn: 27226
 2006-03-28 14:58:32 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Jim Laskey
a9e74309d9 More bulletproofing of llvm.dbg.declare. 
llvm-svn: 27224
 2006-03-28 13:45:20 +00:00
Jim Laskey
fa6dfa9212 Added missing paren on behalf of Ramana Radhakrishnan. 
llvm-svn: 27223
 2006-03-28 10:17:11 +00:00
Evan Cheng
0305cec743 Missed X86::isUNPCKHMask 
llvm-svn: 27222
 2006-03-28 08:27:15 +00:00
Evan Cheng
7b7954f53f movlps and movlpd should be modeled as two address code. 
llvm-svn: 27221
 2006-03-28 07:01:28 +00:00
Evan Cheng
a96380ba3f Update 
llvm-svn: 27220
 2006-03-28 06:55:45 +00:00
Evan Cheng
9f0e244187 Typo 
llvm-svn: 27219
 2006-03-28 06:53:49 +00:00
Evan Cheng
fb4b2bfc7d * Prefer using operation of matching types. e.g unpcklpd rather than movlhps. 
* Bug fixes.

llvm-svn: 27218
 2006-03-28 06:50:32 +00:00
Evan Cheng
e5ae0c50ab Use movhpd is even better than movlhps. 
llvm-svn: 27217
 2006-03-28 06:40:57 +00:00
Nate Begeman
d432d66cc8 Fix a couple typos 
llvm-svn: 27216
 2006-03-28 04:18:18 +00:00
Nate Begeman
5a82c8ccbd Add a few more altivec intrinsics 
llvm-svn: 27215
 2006-03-28 04:15:58 +00:00
Jeff Cohen
d6a0ead88c Keep Visual Studio informed. 
llvm-svn: 27214
 2006-03-28 04:01:27 +00:00
Chris Lattner
1a5116bd0c These don't directly map to gcc intrinsics any more. 
llvm-svn: 27213
 2006-03-28 03:52:36 +00:00
Evan Cheng
ca067debe3 Added a couple of entries about movhps and movlhps. 
llvm-svn: 27212
 2006-03-28 02:49:12 +00:00
Evan Cheng
9accac09cd All unpack cases are now being handled. 
llvm-svn: 27211
 2006-03-28 02:44:05 +00:00
Evan Cheng
4d554dae17 - Clean up / consoladate various shuffle masks. 
- Some misc. bug fixes.
- Use MOVHPDrm to load from m64 to upper half of a XMM register.

llvm-svn: 27210
 2006-03-28 02:43:26 +00:00
Chris Lattner
a570305421 implement a bunch more intrinsics. 
llvm-svn: 27209
 2006-03-28 02:29:37 +00:00
Chris Lattner
176d16aec7 Add some more intrinsics: rotates, fp rounds, and random other fp instructions. 
llvm-svn: 27208
 2006-03-28 02:28:48 +00:00
Evan Cheng
d10153ba72 getVectorTyppe(MVT::i64, 2) ==> MVT::v2i64. 
llvm-svn: 27207
 2006-03-28 01:59:17 +00:00
Chris Lattner
76ce849af5 Add lvxl 
llvm-svn: 27206
 2006-03-28 01:49:27 +00:00
Chris Lattner
ac98e20cc9 Use normal lvx for scalar_to_vector instead of lve*x. They do the exact 
same thing and we have a dag node for the former.

llvm-svn: 27205
 2006-03-28 01:43:22 +00:00
Jim Laskey
792c32936a Regression test for the handling of nulls as arguments to debug intrinsics. 
llvm-svn: 27204
 2006-03-28 01:34:14 +00:00
Jim Laskey
702240530d More bulletproofing of DebugInfoDesc verify. 
llvm-svn: 27203
 2006-03-28 01:30:18 +00:00
Chris Lattner
723cb246c9 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
Also, don't emit dynamic checks when we can compute them statically

llvm-svn: 27202
 2006-03-28 00:41:33 +00:00
Chris Lattner
d5da541d42 Tblgen doesn't like multiple SDNode<> definitions that map to the sameenum value. Split them into separate enums. 
llvm-svn: 27201
 2006-03-28 00:40:33 +00:00