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189298 Commits

Author SHA1 Message Date
David Herzka
3caead3cf9 Make lazyload_metadata.ll resilient to the addition of new metadata kinds
Summary: The specific number of records loaded depends on the number of kinds, but the difference between the lazy and not lazy cases does not.

Reviewers: modocache

Subscribers: llvm-commits, dexonsmith, steven_wu, hiraditya, mehdi_amini

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71882
2019-12-26 13:56:07 -05:00
Kristina Bessonova
678c15be2e [DebugInfo][SelectionDAG] Change order while transferring SDDbgValue to another node
SelectionDAG::transferDbgValues() can 'reattach' SDDbgValue from one to
another node, but doesn't change its source order. If the destination node has
the order greater than the SDDbgValue, there are two possible issues
revealed later:

* If debug info is attached to an instruction that is the first definition
of a register, this ends up with a def-after-use and the debug info
gets 'undef' later.

* If MIR has another definition of a register above the debug info,
the debug info may represent a source variable incorrectly because
it appears (significantly) before an instruction corresponded
to this debug info.

So, the patch changes the order of an SDDbgValue when it is moved
to a node with greater order.

Reviewers: dblaikie, jmorse, aprantl

Reviewed By: aprantl

Subscribers: aprantl, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71175
2019-12-26 21:01:59 +03:00
Hideto Ueno
32636b9bc2 [Attributor] Add helper to change an instruction to unreachable inst
Summary: Calling `changeToUnreachable` in `manifest` from different places might cause really unpredictable problems. As other deleting functions are doing, we need to change these instructions after all `manifest`.

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71910
2019-12-27 02:39:37 +09:00
Yonghong Song
5edd9fe417 [BPF] Enable relocation location for load/store/shifts
Previous btf field relocation is always at assignment like
   r1 = 4
which is converted from an ld_imm64 instruction.

This patch did an optimization such that relocation
instruction might be load/store/shift. Specically, the
following insns may also have relocation, except BPF_MOV:
  LDB, LDH, LDW, LDD, STB, STH, STW, STD,
  LDB32, LDH32, LDW32, STB32, STH32, STW32,
  SLL, SRL, SRA

To accomplish this, a few BPF target specific
codegen only instructions are invented. They
are generated at backend BPF SimplifyPatchable phase,
which is at early llc phase when SSA form is available.
The new codegen only instructions will be converted to
real proper instructions at the codegen and BTF emission stage.

Note that, as revealed by a few tests, this optimization might
be actual generating more relocations:
Scenario 1:
  if (...) {
    ... __builtin_preserve_field_info(arg->b2, 0) ...
  } else {
    ... __builtin_preserve_field_info(arg->b2, 0) ...
  }
  Compiler could do CSE to only have one relocation. But if both
  of the above is translated into codegen internal instructions,
  the compiler will not be able to do that.
Scenario 2:
  offset = ... __builtin_preserve_field_info(arg->b2, 0) ...
  ...
  ...  offset ...
  ...  offset ...
  ...  offset ...
  For whatever reason, the compiler might be temporarily do copy
  propagation of the righthand of "offset" assignment like
  ...  __builtin_preserve_field_info(arg->b2, 0) ...
  ...  __builtin_preserve_field_info(arg->b2, 0) ...
  and CSE will be able to deduplicate later.
  But if these intrinsics are converted to BPF pseudo instructions,
  they will not be able to get deduplicated.

I do not expect we have big instruction count difference.
It may actually reduce instruction count since now relocation
is in deeper insn dependency chain.
For example, for test offset-reloc-fieldinfo-2.ll, this patch
generates 7 instead of 6 relocations for non-alu32 mode, but it
actually reduced instruction count from 29 to 26.

Differential Revision: https://reviews.llvm.org/D71790
2019-12-26 09:07:39 -08:00
Johannes Doerfert
9844011a9e [OpenMP][NFCI] Use the libFrontend ProcBindKind in Clang
This removes the OpenMPProcBindClauseKind enum in favor of
llvm::omp::ProcBindKind which lives in OpenMPConstants.h and was
introduced in D70109.

No change in behavior is expected.

Reviewed By: JonChesterfield

Differential Revision: https://reviews.llvm.org/D70289
2019-12-26 11:04:07 -06:00
Craig Topper
503de2f1bb [X86] Merge the SINT_TO_FP/UINT_TO_FP handlers in ReplaceNodeResults since the AVX512DQ+AVX512VL code is very similar in both. NFC 2019-12-26 08:58:34 -08:00
Craig Topper
db12482580 [X86] Add custom lowering for v2i64->v2f32 strict_sint_to_fp/strict_uint_to_fp for avx512dq+avx512vl targets.
With avx512dq+avx512vl we have instruction that implements this and
places zeroes in the upper 64-bits of the destination xmm register.
2019-12-26 08:58:34 -08:00
Craig Topper
1e3366c8f5 [X86] Add test cases for v2i64->v2f32 strict_sint_to_fp/strict_uint_to_fp. 2019-12-26 08:58:34 -08:00
Craig Topper
1f371e48ae [X86] Add avx512f and avx512dq+vl command lines to the vector strictfp int<->fp tests. 2019-12-26 08:58:34 -08:00
Reid Kleckner
9621aaa540 Partially revert "Add initial tests for update_{llc_,cc_,}test_checks.py"
This reverts part of commit 240aff80e0e59b79779d046b3275904fc0750d59.
It reverts cc802ea67beb66d2f8a935e647c3aedcf7848211.

We currently run LLVM tests in environments where python3 exists on
PATH, but it is broken. I don't think PATH discovery is a strong enough
signal that a working Python 3 installation exists.

If this will be the way forward, IMO we should follow the direction of
debug-info-tests, and use CMake's PYTHON_EXECUTABLE, which in the near
future will be a known-to-work Python 3 executable. If it's not Python
3, then we don't have to run this test.
2019-12-26 08:53:06 -08:00
czhengsz
4e05af94f0 [PowerPC] stop folding if result rlwinm mask is wrap while original rlwinm is not.
%1:g8rc = RLWINM8 %0:g8rc, 0, 16, 9
%2:g8rc = RLWINM8 killed %1:g8rc, 0, 0, 31
->
%2:g8rc = RLWINM8 %0:g8rc, 0, 16, 9

The above folding is wrong. Before transformation, %2:g8rc is 32 bit value. After
transformation, %2:g8rc becomes a 64 bit value.
This patch fixes above issue.

Reviewed by: steven.zhang

Differential Revision: https://reviews.llvm.org/D71833
2019-12-25 21:56:18 -05:00
Fangrui Song
d1b45108f8 [Bitstream] Delete skipAbbreviatedField which duplicates readAbbreviatedField 2019-12-25 18:55:02 -08:00
QingShan Zhang
c3d9654128 [NFC][PowerPC] Add a function tryAndWithMask to handle all the cases
that 'and' with constant

More patches will be committed later to exploit more about 'and' with
constant.

Differential Revision: https://reviews.llvm.org/D71693
2019-12-26 02:48:30 +00:00
Whitney Tsang
263807e28c [NFC][LoopFusion] Fix printing of the guard branch.
Reviewer: kbarton, jdoerfert
Reviewed By: jdoerfert
Subscribers: hiraditya, llvm-commits
Tag: LLVM
Differential Revision: https://reviews.llvm.org/D71878
2019-12-26 02:45:29 +00:00
Kang Zhang
f7cad0a97a [PowerPC] Modify the hasSideEffects of MTLR and MFLR from 1 to 0
Summary:
If we didn't set the value for hasSideEffects bit in our td file, `llvm-tblgen`
will set it as true for those instructions which has no match pattern.
The instructions `MTLR` and `MFLR` don't set the hasSideEffects flag and don't
have match pattern, so their hasSideEffects flag will be set true by
`llvm-tblgen`.
But in fact, we can use `[LR]` to model the two instructions, so they should not
have SideEffects.

This patch is to modify the hasSideEffects of MTLR and MFLR from 1 to 0.

Reviewed By: jsji

Differential Revision: https://reviews.llvm.org/D71390
2019-12-26 02:12:32 +00:00
David Herzka
6d5d0bb01c Revert "Make lazyload_metadata.ll resilient to the addition of new metadata kinds"
This reverts commit 2e6c15d1e7a47f11fab2dd3a40fcff01906923ae.

It causes the test to fail on Windows
2019-12-25 19:52:17 -05:00
Wang, Pengfei
1a25dc07c8 [X86] Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend
Summary: Enable STRICT_SINT_TO_FP/STRICT_UINT_TO_FP on X86 backend

Reviewers: craig.topper, RKSimon, LiuChen3, uweigand, andrew.w.kaylor

Subscribers: hiraditya, llvm-commits, LuoYuanke

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71871
2019-12-26 08:15:13 +08:00
Johannes Doerfert
9c02ea5b83 [OpenMP][IR-Builder] Introduce "pragma omp parallel" code generation
This patch combines the `emitParallel` logic prototyped in D61953 with
the OpenMPIRBuilder (D69785) and introduces `CreateParallel`.

Reviewed By: fghanim

Differential Revision: https://reviews.llvm.org/D70109
2019-12-25 18:02:23 -06:00
David Herzka
65a463a420 Make lazyload_metadata.ll resilient to the addition of new metadata kinds
Summary: The specific number of records loaded depends on the number of kinds, but the difference between the lazy and not lazy cases does not.

Reviewers: modocache

Subscribers: mehdi_amini, hiraditya, steven_wu, dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71730
2019-12-25 18:59:21 -05:00
Johannes Doerfert
7b9709c111 [OpenMP][IR-Builder] Introduce the finalization stack
As a permanent and generic solution to the problem of variable
finalization (destructors, lastprivate, ...), this patch introduces the
finalization stack. The objects on the stack describe (1) the
(structured) regions the OpenMP-IR-Builder is currently constructing,
(2) if these are cancellable, and (3) the callback that will perform the
finalization (=cleanup) when necessary.

As the finalization can be necessary multiple times, at different source
locations, the callback takes the position at which code is currently
generated. This position will also encode the destination of the "region
exit" block *iff* the finalization call was issues for a region
generated by the OpenMPIRBuilder. For regions generated through the old
Clang OpenMP code geneneration, the "region exit" is determined by Clang
inside the finalization call instead (see getOMPCancelDestination).

As a first user, the parallel + cancel barrier interaction is changed.
In contrast to the temporary solution before, the barrier generation in
Clang does not need to be aware of the "CancelDestination" block.
Instead, the finalization callback is and, as described above, later
even that one does not need to be.

D70109 will be updated to use this scheme.

Reviewed By: ABataev

Differential Revision: https://reviews.llvm.org/D70258
2019-12-25 16:57:08 -06:00
Craig Topper
935be4e0c0 [X86] Use zero vector to extend to 512-bits for strict_fp_to_uint v2i1->v2f64 on targets with AVX512F, but not AVX512VL.
In the worst case, this requires a 128-bit move instruction to
implicitly zero the upper bits. In the common case, we should
recognize the producing instruction already zeroed the upper bits.
2019-12-25 10:46:00 -08:00
Craig Topper
8870316bcc [X86FixupSetCC] Remember the preceding eflags defining instruction while we're scanning the basic block instead of looking back for it.
Summary:
We're already scanning forward through the basic block. Might as
well just remember eflags defs instead of doing a bounded search
backwards later.

Based on a comment in D71841.

Reviewers: RKSimon, spatel, uweigand

Reviewed By: uweigand

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71865
2019-12-25 10:26:13 -08:00
Craig Topper
1afeab6ac2 [X86] Merge together some common code in LowerFP_TO_INT now that we have STRICT_CVTTP2SI/STRICT_CVTTP2UI nodes. NFC 2019-12-25 09:57:27 -08:00
Fangrui Song
8e823f1246 [llvm-nm] Display STT_GNU_IFUNC as 'i'
Reviewed By: grimar

Differential Revision: https://reviews.llvm.org/D71803
2019-12-25 09:47:53 -08:00
Dmitry Preobrazhensky
d3bcd94780 [AMDGPU][MC][DOC] Updated AMD GPU assembler syntax description.
Summary of changes:
- added description of GFX9 subtargets:
  - gfx900;
  - gfx902;
  - gfx904;
  - gfx906;
  - gfx908;
  - gfx909.
2019-12-25 17:51:53 +03:00
Georgii Rymar
603edd8aae [llvm-readobj] - Merge gnu-symbols.test to symbols.test and cleanup.
This cleans up and merges `gnu-symbols.test` to `symbols.test`.
Initially `gnu-symbols.test` tested the following things:
1) How symbols are printed in GNU style.
   It does not make sense to have a separate file for such tests.
2) It tried to test proc-specific symbol indexes. The test was incomplete and
   also we already have `symbol-shndx.test` for that, so this part was removed.
3) It tested `--dyn-symbols` and `--symbols` correlation. All following
   cases were moved to `symbols.test`:
   a) That `--dyn-symbols` does not trigger showing regular symbols..
   b) That `--symbols` triggers `--dyn-symbols` implicitly.
   c) That `--dyn-symbols` and `--symbols` works fine together.

Differential revision: https://reviews.llvm.org/D71697
2019-12-25 15:30:36 +03:00
Georgii Rymar
f79d94e9da [llvm-readobj/llvm-readelf][test] - Add testing for EI_OSABI and EI_ABIVERSION fields of an ELF header.
We had no separate tests for these fields.

Differential revision: https://reviews.llvm.org/D71766
2019-12-25 15:03:00 +03:00
Liu, Chen3
811dbea11b Add missing strict_fp_to_int
Differential Revision: https://reviews.llvm.org/D71867
2019-12-25 16:10:10 +08:00
Hideto Ueno
21c47b8ae3 [Attributor] Reach optimistic fixpoint in AAValueSimplify when the value is constant or undef
Summary:
As discussed in D71799, we have found that it is more useful to reach an optimistic fixpoint in AAValueSimpify when the value is constant or undef.

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert

Subscribers: baziotis, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71852
2019-12-25 14:18:34 +09:00
Craig Topper
78bdee725f [X86FixupSetCC] Use MachineInstr::readRegister/definesRegister to check for EFLAGS use/def instead of our own custom operand scan. NFCI 2019-12-24 20:34:33 -08:00
Johannes Doerfert
e26de0ea0b [Attributor] UB Attribute now handles all instructions that access memory through a pointer
Summary:
Follow-up on: https://reviews.llvm.org/D71435
We basically use `checkForAllInstructions` to loop through all the instructions in a function that access memory through a pointer: load, store, atomicrmw, atomiccmpxchg
Note that we can now use the `getPointerOperand()` that gets us the pointer operand for an instruction that belongs to the aforementioned set.

Question: This function returns `nullptr` if the instruction is `volatile`. Why?
Guess:  Because if it is volatile, we don't want to do any transformation to it.

Another subtle point is that I had to add AtomicRMW, AtomicCmpXchg to `initializeInformationCache()`. Following `checkAllInstructions()` path, that
seemed the most reasonable place to add it and correct the fact that these instructions were ignored (they were not in `OpcodeInstMap` etc.). Is that ok?

Reviewers: jdoerfert, sstefan1

Reviewed By: jdoerfert, sstefan1

Subscribers: hiraditya, jfb, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D71787
2019-12-24 19:25:08 -06:00
Johannes Doerfert
2852239785 [Attributor] Function level undefined behavior attribute
_Eventually_, this attribute will be assigned to a function if it
contains undefined behavior. As a first small step, I tried to make it
loop through the load instructions in a function (eventually, the plan
is to check if a load instructions causes undefined behavior, because
e.g. dereferences a null pointer - Also eventually, this won't happen in
initialize() but in updateImpl()).

Patch By: Stefanos Baziotis (@baziotis)

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D71435
2019-12-24 19:23:08 -06:00
Fangrui Song
23ebb038ec [MCJIT] Migrate function attribute "no-frame-pointer-elim" to "frame-pointer" 2019-12-24 17:12:21 -08:00
Fangrui Song
34ab9ca145 [WinEH] Delete addFnAttr("no-frame-pointer-elim") which seems no longer needed
It was added in rL238619.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D71862
2019-12-24 17:02:19 -08:00
Fangrui Song
8d35ec8cc0 [Thumb][test] Fix CodeGen/Thumb/PR17309.ll after llvmorg-10-init-16046-ga36ddf0aa9d
All of

"no-frame-pointer-elim-non-leaf"
"no-frame-pointer-elim-non-leaf"="true"
"no-frame-pointer-elim-non-leaf"="false"

mean "frame-pointer"="non-leaf", which is quite counter-intuitive.
llvmorg-10-init-16046-ga36ddf0aa9d accidentally broke it.

This fixes the -DLLVM_ENABLE_EXPENSIVE_CHECKS=On test:

```
*** Bad machine code: Non-flag-setting Thumb1 mov is v6-only ***
- function:    pass_C
- basic block: %bb.0 entry (0x1fc9bf0)
- instruction: $r0 = tMOVr killed $r6, 14, $noreg
```
2019-12-24 16:58:12 -08:00
Johannes Doerfert
c1d473a27d [Support] Fix behavior of StringRef::count with overlapping occurrences, add tests
Summary:
Fix the behavior of StringRef::count(StringRef) to not count overlapping occurrences, as is stated in the documentation.
Fixes bug https://bugs.llvm.org/show_bug.cgi?id=44072

I added Krzysztof Parzyszek to review this change because a use of this function in HexagonInstrInfo::getInlineAsmLength might depend on the overlapping-behavior. I don't have enough domain knowledge to tell if this change could break anything there.

All other uses of this method in LLVM (besides the unit tests) only use single-character search strings. In those cases, search occurrences can not overlap anyway.

Patch by Benno (@Bensge)

Reviewed By: jdoerfert

Differential Revision: https://reviews.llvm.org/D70585
2019-12-24 18:30:41 -06:00
Fangrui Song
2d0a36fd96 Migrate function attribute "no-frame-pointer-elim"="false" to "frame-pointer"="none" as cleanups after D56351 2019-12-24 16:27:51 -08:00
Fangrui Song
148dd94d20 Migrate function attribute "no-frame-pointer-elim-non-leaf" to "frame-pointer"="non-leaf" as cleanups after D56351 2019-12-24 16:05:15 -08:00
Fangrui Song
d9c5df08b1 Migrate function attribute "no-frame-pointer-elim" to "frame-pointer"="all" as cleanups after D56351 2019-12-24 15:57:33 -08:00
Matt Arsenault
96f076f9f0 AMDGPU/GlobalISel: Fix mapping and selection of llvm.amdgcn.div.fixup 2019-12-24 15:36:29 -05:00
Craig Topper
d56992931f [X86] Use 128-bit vector instructions for f32/f64->i64 conversions on 32-bit targets with avx512dq and avx512vl instructions.
On 32-bit targets we can't use the scalar instruction so we
insert the scalar into a vector and use packed conversions.
Previously we used either v4f32->v4i64 or v4f64->v4i64 to avoid
some complexity creating target specific ISD opcodes for
v4f32->v2i64. But this causes extra vzeroupper instructions and
possibly frequency throttling on Intel CPUs.

This patch changes this to create a 128-bit vector and uses a
target specific ISD opcode if needed.
2019-12-24 11:20:10 -08:00
Craig Topper
fa1a4c5352 [X86] Add STRICT versions of CVTTP2SI, CVTTP2UI, CMPM, and CMPP.
Differential Revision: https://reviews.llvm.org/D71850
2019-12-24 10:07:04 -08:00
Matt Arsenault
746c82bba4 GlobalISel: Update syntax in debug printing
Physical register names now start with $, not %
2019-12-24 10:37:36 -05:00
Matt Arsenault
62bbba4bb4 GlobalISel: Define equivalent node for G_INTRINSIC_ROUND 2019-12-24 10:36:54 -05:00
Matt Arsenault
ec17d50e02 GlobalISel: Fix naming variables "brank" instead of "bank" 2019-12-24 10:36:54 -05:00
Matt Arsenault
815b914730 AMDGPU/GlobalISel: Legalize some 16-bit round instructions 2019-12-24 09:53:01 -05:00
Matt Arsenault
e430cb728d GlobalISel: Define equivalent node for G_INTRINSIC_TRUNC 2019-12-24 09:53:01 -05:00
Matt Arsenault
21e2e91a0c AMDGPU/GlobalISel: Lower llvm.amdgcn.else 2019-12-24 09:53:01 -05:00
Sylvestre Ledru
019a50342e VariableName doc: fix the link to the mozilla doc 2019-12-24 13:39:22 +01:00
Russell Gallop
2102a38188 Revert "[Support] Extend TimeProfiler to support multiple threads"
and "[Support] Try to fix bot failure after 8ddcd1dc26"

This reverts commits f70f180148 and 8ddcd1dc26 as this was breaking the
MacOS build, which doesn't support thread_local.
2019-12-24 11:31:48 +00:00