3 Commits

Author	SHA1	Message	Date
Bob Wilson	c01101e76c	Add alignment arguments to all the NEON load/store intrinsics. ... Update all the tests using those intrinsics and add support for auto-upgrading bitcode files with the old versions of the intrinsics. llvm-svn: 112271	2010-08-27 17:13:24 +00:00
Jakob Stoklund Olesen	d76041cf58	Add a -regalloc=default option that chooses a register allocator based on the -O ... optimization level. This only really affects llc for now because both the llvm-gcc and clang front ends override the default register allocator. I intend to remove that code later. llvm-svn: 104904	2010-05-27 23:57:25 +00:00
Jakob Stoklund Olesen	924b84cf0f	Teach VirtRegRewriter to handle spilling in instructions that have multiple ... definitions of the virtual register. This happens when spilling the registers produced by REG_SEQUENCE: %reg1047:5<def>, %reg1047:6<def>, %reg1047:7<def> = VLD3d8 %reg1033, 0, pred:14, pred:%reg0 The rewriter would spill the register multiple times, dead store elimination tried to keep up, but ended up cutting the branch it was sitting on. llvm-svn: 104321	2010-05-21 16:36:13 +00:00