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Commit Graph

200319 Commits

Author SHA1 Message Date
Roman Lebedev
321fbe74f0 [NFC][SimplifyCFG] Rename statistic NumSinkCommons into NumSinkCommonInstrs
It really counts instructions added into common block,
not number of instruction groups sunk.
2020-07-16 00:21:55 +03:00
Roman Lebedev
348c4b6ddd [NFC][LoopRotate] Add a statistic for how many times rotation failed due to the header size 2020-07-16 00:21:55 +03:00
Jared Wyles
3a74adf066 [jitlink] Adding support for PCRel32GOTLoad in ELF x86 for the jitlinker
Summary: This adds the basic support for GOT in elf x86.
Was able to just get away using the macho code by generalising the edges.
There will be a follow up patch to turn that into a generic utility for both of the x86 and Mach-O code.

This patch also lands support for relocations relative to symbol.

Reviewers: lhames

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83748
2020-07-16 07:15:08 +10:00
Mehdi Amini
6f679f30fe Document the testing of Analyses in the LLVM testing guide (NFC)
This came up in a recent review, someone was wondering were was
this all documented and I couldn't find a reference to provide.

Differential Revision: https://reviews.llvm.org/D83816
2020-07-15 21:11:49 +00:00
Mehdi Amini
0080e83362 Clarify a bit the guideline on omitting braces, including more examples (NFC)
Like most readability rules, it isn't absolute and there is a matter of taste
to it. I think more recent part of the project may be more consistent in the
current application of the guideline. I suspect sources like
mlir/lib/Dialect/StandardOps/IR/Ops.cpp may be examples of this at the moment.

Differential Revision: https://reviews.llvm.org/D82594
2020-07-15 21:11:30 +00:00
Abhina Sreeskantharajan
14ef44b9eb [NFC] [AIX] [z/OS] Fix build failure on AIX and z/OS
Summary: This PR contains a build failure fix that occurs on both AIX and z/OS as a result of this commit https://reviews.llvm.org/rG670915094462d831e3733e5b01a76471b8cf6dd8.

Reviewers: uweigand, Kai, hubert.reinterpretcast, daltenty, lhames

Reviewed By: Kai, hubert.reinterpretcast, daltenty

Subscribers: SeanP, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83889
2020-07-15 16:07:34 -04:00
Hongtao Yu
cc553c933f [LoopUnroll] Update branch weight for remainder loop
Unrolling a loop with compile-time unknown trip count results in a remainder loop. The remainder loop executes the remaining iterations of the original loop when the original trip count is not a multiple of the unroll factor. For better profile counts maintenance throughout the optimization pipeline, I'm assigning an artificial weight to the latch branch of the remainder loop.

A remainder loop runs up to as many times as the unroll factor subtracted by 1. Therefore I'm assigning the maximum possible trip count as the back edge weight. This should be more accurate than the default non-profile weight, which assumes the back edge runs much more frequently than the exit edge.

Differential Revision: https://reviews.llvm.org/D83187
2020-07-15 12:33:29 -07:00
dfukalov
4e76681a5e [NFC] Fixed typo in tests parameters
Summary:
llc reports `fp32-denormals` is not recognized. I guess it was intended to be
`-denormal-fp-math-f32={preserve-sign|ieee} -mattr=+mad-mac-f32-insts`

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: jvesely, nhaehnle, llvm-commits, kerbowa

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83883
2020-07-15 22:09:01 +03:00
Hiroshi Yamauchi
f77ecf351a [PGO][PGSO] Add profile guided size optimization to loop vectorization legality.
Differential Revision: https://reviews.llvm.org/D83329
2020-07-15 11:49:36 -07:00
Sanjay Patel
4f51031c07 [InstCombine] prevent infinite looping in or-icmp fold (PR46712)
I'm not sure if the test is truly minimal, but we need to
induce a situation where a value becomes a constant but is
not immediately folded before getting to the 'or' transform.
2020-07-15 14:12:12 -04:00
Sanjay Patel
00941df37c [InstCombine] update datalayout in test file; NFC
We need to specify legal integer widths to trigger PR46712,
so add those here. This doesn't appear to affect any existing
tests, and it's not clear why a datalayout would not include
any legal integer widths.

While here, change some variable names that include 'tmp' to
avoid warnings from the auto-generating script for CHECK lines.
2020-07-15 14:12:12 -04:00
LLVM GN Syncbot
3194a601ce [gn build] Port 4a539faf74b 2020-07-15 17:53:38 +00:00
Hiroshi Yamauchi
a85cda4f5a [PGO] Extend the value profile buckets for mem op sizes.
Extend the memop value profile buckets to be more flexible (could accommodate a
mix of individual values and ranges) and to cover more value ranges (from 11 to
22 buckets).

Disabled behind a flag (to be enabled separately) and the existing code to be
removed later.
2020-07-15 10:26:15 -07:00
Hiroshi Yamauchi
bd196de5cc [PGO][PGSO] Add profile guided size optimization to LegalizeDAG.
Reviewers: davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83333
2020-07-15 10:03:38 -07:00
Dmitry Preobrazhensky
5fa0e72fe0 [AMDGPU][MC] Corrected MTBUF parsing and decoding
MTBUF implementation has many issues and this change addresses most of these:
- refactored duplicated code;
- hardcoded constants moved out of high-level code;
- fixed a decoding error when nfmt or dfmt are zero (bug 36932);
- corrected parsing of operand separators (bug 46403);
- corrected handling of missing operands (bug 46404);
- corrected handling of out-of-range modifiers (bug 46421);
- corrected default value (bug 46467).

Reviewers: arsenm, rampitec, vpykhtin, artem.tamazov, kzhuravl

Differential Revision: https://reviews.llvm.org/D83760
2020-07-15 19:46:00 +03:00
Arthur Eubanks
e676ba13ee [NPM][IVUsers] Rename ivusers -> iv-users
LPM passes were named iv-users, which seems nicer than ivusers.

Reviewed By: hans

Differential Revision: https://reviews.llvm.org/D83803
2020-07-15 09:38:21 -07:00
Petr Hosek
3bd12e996a [CMake][runtimes] Pass the CMAKE_ARGS to runtimes build correctly
We were relying on CMAKE_ARGS argument to be passed to subbuild, but
this argument was never properly defined. This patch addresses that.

Differential Revision: https://reviews.llvm.org/D83842
2020-07-15 09:25:18 -07:00
Cameron McInally
e85faaeff6 [Legalize] Hoist invariant condition in ExpandVectorBuildThroughStack(...)
The operands of a BUILD_VECTOR must all have the same type, so we can hoist this invariant condition out of the loop.

Differential Revision: https://reviews.llvm.org/D83882
2020-07-15 11:05:20 -05:00
David Green
10c8c57cad [HardwareLoops] Add sibling loop test.
This missed being part of 9e03547cab69.
2020-07-15 16:36:17 +01:00
Tim Northover
e5ccba81cf CodeGenPrep: remove AssertingVH references before deleting dead instructions.
CodeGenPrepare keeps fairly close track of various instructions it's
seen, particularly GEPs, in maps and vectors. However, sometimes those
instructions become dead and get removed while it's still executing.
This triggers AssertingVH references to them in an asserts build and
could lead to miscompiles in a release build (I've only seen a later
segfault though).

So this patch adds a callback to
RecursivelyDeleteTriviallyDeadInstructions which can make sure the
instruction about to be deleted is removed from CodeGenPrepare's data
structures.
2020-07-15 15:19:21 +01:00
YunQiang Su
f59acd352c [mips] Rename FeatureMadd4 to FeatureNoMadd4. NFC
`FeatureMadd4` is used to disable `madd4`, and the corresponding feature
option is `(+-)nomadd4`. Renaming to the `FeatureNoMadd4` makes its
purpose clear.

Patch by YunQiang Su.

Differential Revision: https://reviews.llvm.org/D83780
2020-07-15 14:39:38 +03:00
lewis-revill
8b1bd76f10 [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbt asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions from the ternary subset (zbt subextension) of the
experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79875
2020-07-15 12:19:34 +01:00
lewis-revill
fe292b0d36 [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbs asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions from the single-bit subset (zbs subextension) of
the experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79874
2020-07-15 12:19:34 +01:00
lewis-revill
b1bad8652a [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbbp asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions belonging to both the permutation and the base
subsets of the experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79873
2020-07-15 12:19:34 +01:00
lewis-revill
ae71533886 [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbp asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions from the permutation subset (zbp subextension) of
the experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79871
2020-07-15 12:19:34 +01:00
lewis-revill
f877008728 [RISCV] Add matching of codegen patterns to RISCV Bit Manipulation Zbb asm instructions
This patch provides optimization of bit manipulation operations by
enabling the +experimental-b target feature.
It adds matching of single block patterns of instructions to specific
bit-manip instructions from the base subset (zbb subextension) of the
experimental B extension of RISC-V.
It adds also the correspondent codegen tests.

This patch is based on Claire Wolf's proposal for the bit manipulation
extension of RISCV:
https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.92.pdf

Differential Revision: https://reviews.llvm.org/D79870
2020-07-15 12:19:34 +01:00
John Brawn
e3485c1b1b [DSE,MSSA] Recognise init_trampoline in getLocForWriteEx
This fixes an instance where MemorySSA-using Dead Store Elimination is failing
to do a transformation that the non-MemorySSA-using version does.

Differential Revision: https://reviews.llvm.org/D83783
2020-07-15 12:18:58 +01:00
Xing GUO
0c62b8c27a [DWARFYAML] Remove useless conditional statement. NFC.
The conditional statement is useless after
3a48a632d00ef1c98042140f402337fe13cdff52.
2020-07-15 19:04:58 +08:00
Florian Hahn
46013c4277 [LoopRotate] Remove unnecessary verifyMemorySSA calls.
The actual rotation happens in processLoop, so the second removed
call to verifyMemorySSA was unnecessary.

In fact, processLoop/rotateLoop already verify MemorySSA before
and after transforming each loop. Hence, both calls can be removed.

Pointed out by @lebedev.ri post-commit D51718.
2020-07-15 11:49:24 +01:00
Hans Wennborg
7ddc914b02 Bump the trunk major version to 12
and clear the release notes.
2020-07-15 12:05:05 +02:00
Jessica Clarke
d84def18b6 [RISCV] Duplicate pseudo expansion comment to RISCVMCCodeEmitter
Follow-on from D77443. Although we're not fixing any of these
pseudo-instructions, the potential for them to be out of sync still
exists.
2020-07-15 10:52:42 +01:00
Jessica Clarke
38500c1e8c [RISCV] Fix RISCVInstrInfo::getInstSizeInBytes for atomics pseudos
Summary:
Without these, the generic branch relaxation pass will underestimate the
range required for branches spanning these and we can end up with
"fixup value out of range" errors rather than relaxing the branches.
Some of the instructions in the expansion may end up being compressed
but exactly determining that is awkward, and these conservative values
should be safe, if slightly suboptimal in rare cases.

Reviewers: asb, lenary, luismarques, lewis-revill

Reviewed By: asb, luismarques

Subscribers: hiraditya, rbar, johnrusso, simoncook, sabuasal, niosHD, kito-cheng, shiva0217, MaskRay, zzheng, edward-jones, rogfer01, MartinMosbeck, brucehoult, the_o, rkruppe, jfb, PkmX, jocewei, psnobl, benna, Jim, s.egerton, pzheng, sameer.abuasal, apazos, evandro, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D77443
2020-07-15 10:50:55 +01:00
Georgii Rymar
99edb55f34 [yaml2obj] - Rename FileHeader::SH* fields.
In D83482 we agreed to name e_* fields that are used for overriding
values (like e_phoff) as EPh* (e.g. EPhOff).

Currently we have a set of e_sh* fields that are named inconsistently
with this rule. This patch renames all of them.

Differential revision: https://reviews.llvm.org/D83766
2020-07-15 12:47:31 +03:00
Florian Hahn
efc99fc64b [Matrix] Only pass vector arg as overloaded type in MatrixBuilder.
In 2b3c505, the pointer arguments for the matrix load and store
intrinsics was changed to always be the element type of the vector
argument.

This patch updates the MatrixBuilder to not add the pointer type to the
overloaded types and adjusts the clang/mlir tests.

This should fix a few build failures on GreenDragon, including
 http://green.lab.llvm.org/green/job/test-suite-verify-machineinstrs-x86_64-O0-g/7891/
2020-07-15 10:42:24 +01:00
Georgii Rymar
a6f65b5f35 [llvm-readobj] - Verify the location of program headers better.
This improves condition in the ELFFile::program_headers().
Previously if was possible to read the headers from the wrong place when
the value of e_phoff was so large that computation overflowed.

Differential revision: https://reviews.llvm.org/D83774
2020-07-15 12:37:23 +03:00
Andrew Ng
f8a51407d1 [Support] Fix Windows directory_iterator_construct out of bounds
Fix incorrect use of the size of Path when accessing PathUTF16, as the
UTF-16 path can be shorter. Added unit test for coverage of this test
case.

Thanks to Ding Fei (danix800) for the code fix, see
https://reviews.llvm.org/D83321.

Differential Revision: https://reviews.llvm.org/D83689
2020-07-15 10:13:45 +01:00
Tim Northover
80a21440b3 AArch64+ARM: make LLVM consider system registers volatile.
Some of the system registers readable on AArch64 and ARM platforms
return different values with each read (for example a timer counter),
these shouldn't be hoisted outside loops or otherwise interfered with,
but the normal @llvm.read_register intrinsic is only considered to read
memory.

This introduces a separate @llvm.read_volatile_register intrinsic and
maps all system-registers on ARM platforms to use it for the
__builtin_arm_rsr calls. Registers declared with asm("r9") or similar
are unaffected.
2020-07-15 09:47:36 +01:00
Roger Ferrer Ibanez
97e701dc7a [DAGCombiner] Rebuild (setcc x, y, ==) from (xor (xor x, y), 1)
The existing code already considered this case. Unfortunately a typo in
the condition prevents it from triggering. Also the existing code, had
it run, forgot to do the folding.

This fixes PR42876.

Differential Revision: https://reviews.llvm.org/D65802
2020-07-15 07:34:22 +00:00
Roger Ferrer Ibanez
7ef6c6e4c3 [NFC] Add tests for boolean comparisons
They currently show that the not equal case may be improved.

See PR42876

Differential Revision: https://reviews.llvm.org/D65801
2020-07-15 07:33:43 +00:00
Chen Zheng
9b8b4880f9 [IndVarSimplify] Uniformly use emplace_back for DeadInsts, nfc 2020-07-15 02:48:09 -04:00
Giorgis Georgakoudis
78d6ec66f7 [OpenMPOpt][NFC] Update checks for parallel_deletion test 2020-07-14 23:36:33 -07:00
Giorgis Georgakoudis
e7d9dfd776 [OpenMPOpt] Fix preserved analyses return 2020-07-14 23:18:43 -07:00
Mircea Trofin
b01ead51c6 [llvm][NFC] Hide the tensorflow dependency from headers.
Summary:
This change avoids exposing tensorflow types when including TFUtils.h.
They are just an implementation detail, and don't need to be used
directly when implementing an analysis requiring ML model evaluation.

The TFUtils APIs, while generically typed, are still not exposed unless
the tensorflow C library is present, as they currently have no use
otherwise.

Reviewers: mehdi_amini, davidxl

Subscribers: hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D83843
2020-07-14 21:14:11 -07:00
Alex Bradbury
aa7e5053d4 [Attributor] Fix build of unittest with DBUILD_SHARED_LIBS=True
The dependencies in llvm/unittests/Transforms/IPO/CMakeLists.txt
introduced in revision 0750757e were incomplete, leading to link errors
for a DBUILD_SHARED_LIBS=True build.
2020-07-15 05:05:31 +01:00
Luofan Chen
18d73b0b26 Revert "[Attributor] Track AA dependency using dependency graph"
This reverts commit 8df7af560aebce3f3de3541d039e17331c479831.
2020-07-15 11:48:08 +08:00
Johannes Doerfert
a69b2e1ce4 [OpenMP][IRBuilder] Support nested parallel regions
During code generation we might change/add basic blocks so keeping a
list of them is fairly easy to break. Nested parallel regions were
enough. The new scheme does recompute the list of blocks to be outlined
once it is needed.

Reviewed By: anchu-rajendran

Differential Revision: https://reviews.llvm.org/D82722
2020-07-14 22:39:06 -05:00
Johannes Doerfert
86ca930dc4 [CallGraph] Update callback call sites in RefreshCallGraph
Since D82572, we keep "reference" edges for callback call sites. While
not strictly necessary they can improve the traversal order. However, we
did not update them properly in case a pass removed the callback call
site which caused a verification error (PR46687). With this patch we
update these reference edges properly during the invocation of
`CallGraphSCCPass::RefreshCallGraph` in non-checking mode.

Reviewed By: sdmitriev

Differential Revision: https://reviews.llvm.org/D83718
2020-07-14 22:33:57 -05:00
Johannes Doerfert
97f0a6251c [OpenMP] Emit remarks during GPU state machine optimization
Since D83271 we can optimize the GPU state machine to avoid spurious
call edges that increase the register usage of kernels. With this patch
we inform the user why and if this optimization is happening and when it
is not.

Reviewed By: ye-luo

Differential Revision: https://reviews.llvm.org/D83707
2020-07-14 22:33:57 -05:00
Petr Hosek
53d387776f Revert "[CMake] Simplify CMake handling for zlib"
This reverts commit 8c1a79dc12f3cc600e16153961cd8cc50ba2c33b because
it fails when zlib isn't installed.
2020-07-14 19:56:10 -07:00
Luofan Chen
fb747305dd [Attributor] Track AA dependency using dependency graph
Summary: This patch added dependency graph to the attributor so that we can dump the dependencies between AAs more easily. We can also apply general graph algorithms to the graph, making it easier for us to create deep wrappers.

Reviewers: jdoerfert, sstefan1, uenoku, homerdin, baziotis

Reviewed By: jdoerfert

Subscribers: jfb, okura, mgrang, kuter, lebedev.ri, hiraditya, uenoku, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D78861
2020-07-15 10:40:21 +08:00