RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 03:23:01 +02:00
Code Issues Projects Releases Wiki Activity
78,781 Commits 4 Branches 5 Tags 704 MiB
3d0382e29d
Commit Graph

20174 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
3d0382e29d Note ARM constant island alignment in the release notes. 
The command line option should be removed, but not until the feature has
gotten a lot of testing. The ARMConstantIslandPass tends to have subtle
bugs that only show up after a while.

llvm-svn: 146739
 2011-12-16 16:07:41 +00:00
Craig Topper
88e2bfef0a Don't try to match 'unpackl/h v, v' for 32xi8 and 16xi16 when only AVX1 is supported. Fix 'unpackh v, v' for 256-bit types to understand 128-bit lanes. 
llvm-svn: 146726
 2011-12-16 08:06:31 +00:00
NAKAMURA Takumi
1aaed909ae Target/Hexagon: Fix CMake build. 
llvm-svn: 146724
 2011-12-16 06:21:02 +00:00
Jim Grosbach
42bf8d8526 ARM NEON aliases for vmovq.f* 
llvm-svn: 146714
 2011-12-16 00:12:22 +00:00
Jim Grosbach
5f14a4c5d4 Thumb2 ADR assembly parsing w/o the .w suffix. 
llvm-svn: 146710
 2011-12-15 23:52:17 +00:00
Eli Friedman
f626b19bda Make sure we correctly note the existence of an i8 immediate for vblendvps and friends, so we compute fixups correctly. PR11586. 
llvm-svn: 146709
 2011-12-15 23:46:18 +00:00
Nick Lewycky
88e64bacfa Move parts of lib/Target that use CodeGen into lib/CodeGen. 
llvm-svn: 146702
 2011-12-15 22:58:58 +00:00
Eli Friedman
7e3cbd0db2 Make check a bit more strict so we don't call ARM_AM::getFP32Imm with a value that isn't a 32-bit value. (This is just to be safe; I don't think this actually causes any issues in practice.) 
llvm-svn: 146700
 2011-12-15 22:56:53 +00:00
Jim Grosbach
30f4b285a6 ARM NEON VCLE is an alias for VCGE w/ the source operands reversed. 
llvm-svn: 146699
 2011-12-15 22:56:33 +00:00
Tony Linthicum
31c6f9b096 Add MCTargetDesc library to Hexagon target 
llvm-svn: 146692
 2011-12-15 22:29:08 +00:00
Jim Grosbach
b79d2a8f50 ARM NEON VTBL/VTBX assembly parsing and encoding. 
llvm-svn: 146691
 2011-12-15 22:27:11 +00:00
Jakob Stoklund Olesen
cd03c93e33 Enable proper constant island alignment by default. 
The code size increase is tiny (< 0.05%) because so little code uses
16-byte constant pool entries.

llvm-svn: 146690
 2011-12-15 22:14:45 +00:00
Chad Rosier
62ebee9859 Add missing zmovl AVX patterns which were causing crashes. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146689
 2011-12-15 22:11:31 +00:00
Jim Grosbach
3ee3c6dc3e Silence warning. 
llvm-svn: 146686
 2011-12-15 21:54:55 +00:00
Jim Grosbach
8ed1253ef3 ARM NEON two-register double spaced register list parsing support. 
llvm-svn: 146685
 2011-12-15 21:44:33 +00:00
Chad Rosier
e74b3b1469 Fix assert in LowerBUILD_VECTOR for v16i16 type on AVX. 
Patch by Elena Demikhovsky <elena.demikhovsky@intel.com>!

llvm-svn: 146684
 2011-12-15 21:34:44 +00:00
Lang Hames
d86b47a279 Fix VSELECT operand order. Was previously backwards, causing bogus vector shift results - <rdar://problem/10559581>. 
llvm-svn: 146671
 2011-12-15 18:57:27 +00:00
Hal Finkel
f480143f08 Ensure that the nop that should follow a bl call in PPC64 ELF actually does 
llvm-svn: 146664
 2011-12-15 17:54:01 +00:00
Richard Osborne
5f2d0e64e0 Pass optLevel to XCoreDAGToDAGISel. 
Patch by Kyriakos Georgiou.

llvm-svn: 146656
 2011-12-15 15:18:35 +00:00
Chad Rosier
dcfc5e1dd0 Use SmallVector/assign(), rather than std::vector/push_back(). 
llvm-svn: 146627
 2011-12-15 01:16:09 +00:00
Chad Rosier
b93733686c Add support for lowering fneg when AVX is enabled. 
rdar://10566486

llvm-svn: 146625
 2011-12-15 01:02:25 +00:00
Bill Wendling
e9bd145105 The saved registers weren't being processed in the correct order. This lead to 
the compact unwind claiming that one register was saved before another, which
isn't all that great in general. Process them in the natural order. Reverse the
list only when necessary for the algorithm.

llvm-svn: 146612
 2011-12-14 23:53:24 +00:00
Jakob Stoklund Olesen
215059cb96 Consider CPE alignment in CreateNewWater(). 
An aligned constant pool entry may require extra alignment padding where
the new water is created.  Take that into account when computing offset.

Also consider the alignment of other constant pool entries when
splitting a basic block.  Alignment padding may make it necessary to
move the split point higher.

llvm-svn: 146609
 2011-12-14 23:48:54 +00:00
Jim Grosbach
b09a003fa6 ARM NEON better assembly operand range checking for lane indices of VLD/VST. 
llvm-svn: 146608
 2011-12-14 23:35:06 +00:00
Jim Grosbach
75db252aee ARM NEON VLD2/VST2 lane indexed assembly parsing and encoding. 
llvm-svn: 146605
 2011-12-14 23:25:46 +00:00
Jim Grosbach
83520a5b70 ARM NEON fix alignment encoding for VST2 w/ writeback. 
Add tests for w/ writeback instruction parsing and encoding.

llvm-svn: 146594
 2011-12-14 21:49:24 +00:00
Jim Grosbach
4c0d6081a1 Nuke old code. Missed in last commit. 
llvm-svn: 146590
 2011-12-14 21:41:32 +00:00
Jim Grosbach
2dac770227 ARM NEON refactor VST2 w/ writeback instructions. 
In addition to improving the representation, this adds support for assembly
parsing of these instructions.

llvm-svn: 146588
 2011-12-14 21:32:11 +00:00
Jim Grosbach
7fe9f4b949 ARM NEON improve factoring a bit. No functional change. 
llvm-svn: 146585
 2011-12-14 20:59:15 +00:00
Evan Cheng
8d5b09811a Model ARM predicated write as read-mod-write. e.g. 
r0 = mov #0
r0 = moveq #1

Then the second instruction has an implicit data dependency on the first
instruction. Sadly I have yet to come up with a small test case that
demonstrate the post-ra scheduler taking advantage of this.

llvm-svn: 146583
 2011-12-14 20:00:08 +00:00
Jim Grosbach
44829ab9d2 ARM NEON VST2 assembly parsing and encoding. 
Work in progress. Parsing for non-writeback, single spaced register lists
works now. The rest have the representations better factored, but still
need more to be able to parse properly.

llvm-svn: 146579
 2011-12-14 19:35:22 +00:00
Jakob Stoklund Olesen
bc1bb8d763 Fix speling and 80-col. 
llvm-svn: 146575
 2011-12-14 18:49:13 +00:00
Akira Hatanaka
3fca32d88e Add support for local dynamic TLS model in LowerGlobalTLSAddress. Direct object 
emission is not supported yet, but a patch that adds the support should follow
soon.

llvm-svn: 146572
 2011-12-14 18:26:41 +00:00
Jim Grosbach
7f0853a3f9 Fix copy/pasto that skipped the 'modify' step. 
llvm-svn: 146571
 2011-12-14 18:12:37 +00:00
Jim Grosbach
87066950b3 ARM/Thumb2 mov vs. mvn alias goes both ways. 
llvm-svn: 146570
 2011-12-14 17:56:51 +00:00
Chad Rosier
879f983406 VFP2 is required for FP loads. Noticed by inspection. 
llvm-svn: 146569
 2011-12-14 17:55:03 +00:00
Chad Rosier
4cb75ebb48 Tidy up. 
llvm-svn: 146568
 2011-12-14 17:32:02 +00:00
Jim Grosbach
54372eef76 ARM/Thumb2 'cmp rn, #imm' alias to cmn. 
When 'cmp rn #imm' doesn't match due to the immediate not being representable,
but 'cmn rn, #-imm' does match, use the latter in place of the former, as
it's equivalent.

rdar://10552389

llvm-svn: 146567
 2011-12-14 17:30:24 +00:00
Chad Rosier
c642144c4e Fix 80-column violation and extraneous brackets. 
llvm-svn: 146566
 2011-12-14 17:26:05 +00:00
Jim Grosbach
628ae663ef ARM assembler support for the target-specific .req directive. 
rdar://10549683

llvm-svn: 146543
 2011-12-14 02:16:11 +00:00
Evan Cheng
68ba5536f3 - Add MachineInstrBundle.h and MachineInstrBundle.cpp. This includes a function 
to finalize MI bundles (i.e. add BUNDLE instruction and computing register def
  and use lists of the BUNDLE instruction) and a pass to unpack bundles.
- Teach more of MachineBasic and MachineInstr methods to be bundle aware.
- Switch Thumb2 IT block to MI bundles and delete the hazard recognizer hack to
  prevent IT blocks from being broken apart.

llvm-svn: 146542
 2011-12-14 02:11:42 +00:00
Jim Grosbach
089ad574d8 Thumb2 assembler aliases for "mov(shifted register)" 
rdar://10549767

llvm-svn: 146520
 2011-12-13 22:45:11 +00:00
Jim Grosbach
bd33fc6efd ARM LDM/STM system instruction variants. 
rdar://10550269

llvm-svn: 146519
 2011-12-13 21:48:29 +00:00
Jim Grosbach
11f15ddaab Thumb2 pre/post indexed stores can be from any non-PC GPR. 
rdar://10549786

llvm-svn: 146518
 2011-12-13 21:10:25 +00:00
Jim Grosbach
b2547b424c Thumb2 tweak for ccout handling in RSB parsing. 
llvm-svn: 146516
 2011-12-13 21:06:41 +00:00
Jim Grosbach
13d3509445 ARM thumb2 parsing of "rsb rd, rn, #0". 
rdar://10549741

llvm-svn: 146515
 2011-12-13 20:50:38 +00:00
Jim Grosbach
dfec87fe2f ARM NEON two-operand aliases for VQDMULH. 
llvm-svn: 146514
 2011-12-13 20:40:37 +00:00
Jim Grosbach
0ba5ba4535 ARM pre-UAL NEG mnemonic for convenience when porting old code. 
llvm-svn: 146511
 2011-12-13 20:23:22 +00:00
Jim Grosbach
1738a66371 ARM add some more pre-UAL VFP mnemonics for convenience when porting old code. 
llvm-svn: 146508
 2011-12-13 20:13:48 +00:00
Jim Grosbach
9e5ef02adb ARM add more 'gas' compatibility aliases for NEON instructions. 
llvm-svn: 146507
 2011-12-13 20:08:32 +00:00