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Commit Graph

168298 Commits

Author SHA1 Message Date
Eli Friedman
e1067659a3 [ARM] Lower llvm.ctlz.i32 to a libcall when clz is not available.
The inline sequence is very long (about 70 bytes on Thumb1), so it's
not really a good idea to inline it, especially when optimizing for
size.

Differential Revision: https://reviews.llvm.org/D47917

llvm-svn: 340458
2018-08-22 21:47:14 +00:00
Scott Linder
c46ffa9c82 [BinaryFormat] Add MessagePack reader/writer
Add support for reading and writing MessagePack, a binary object serialization
format which aims to be more compact than text formats like JSON or YAML.

The specification can be found at
https://github.com/msgpack/msgpack/blob/master/spec.md

Will be used for encoding metadata in AMDGPU code objects.

Differential Revision: https://reviews.llvm.org/D44429

llvm-svn: 340457
2018-08-22 21:42:50 +00:00
Eli Friedman
d02128f555 [SafeStack] Handle unreachable code with safe stack coloring.
Instead of asserting that the function doesn't have any unreachable
code, just ignore it for the purpose of computing liveness.

Differential Revision: https://reviews.llvm.org/D51070

llvm-svn: 340456
2018-08-22 21:38:57 +00:00
Yonghong Song
bd27c2c168 bpf: fix an assertion in BPFAsmBackend applyFixup()
Fix bug https://bugs.llvm.org/show_bug.cgi?id=38643

In BPFAsmBackend applyFixup(), there is an assertion for FixedValue to be 0.
This may not be true, esp. for optimiation level 0.
For example, in the above bug, for the following two
static variables:
  @bpf_map_lookup_elem = internal global i8* (i8*, i8*)*
      inttoptr (i64 1 to i8* (i8*, i8*)*), align 8
  @bpf_map_update_elem = internal global i32 (i8*, i8*, i8*, i64)*
      inttoptr (i64 2 to i32 (i8*, i8*, i8*, i64)*), align 8

The static variable @bpf_map_update_elem will have a symbol
offset of 8 and a FK_SecRel_8 with FixupValue 8 will cause
the assertion if llvm is built with -DLLVM_ENABLE_ASSERTIONS=ON.

The above relocations will not exist if the program is compiled
with optimization level -O1 and above as the compiler optimizes
those static variables away. In the below error message, -O2
is suggested as this is the common practice.

Note that FixedValue = 0 in applyFixup() does exist and is valid,
e.g., for the global variable my_map in the above bug. The bpf
loader will process them properly for map_id's before loading
the program into the kernel.

The static variables, which are not optimized away by compiler,
may have FK_SecRel_8 relocation with non-zero FixedValue.

The patch removed the offending assertion and will issue
a hard error as below if the FixedValue in applyFixup()
is not 0.
  $ llc -march=bpf -filetype=obj fixup.ll
  LLVM ERROR: Unsupported relocation: try to compile with -O2 or above,
      or check your static variable usage

Signed-off-by: Yonghong Song <yhs@fb.com>
llvm-svn: 340455
2018-08-22 21:21:03 +00:00
Heejin Ahn
986b1b55cb [WebAssembly] Don't write SP back when prolog is generated only for EH
Summary:
When we don't actually have stack-allocated variables but need SP only
to support EH, we don't need to write SP back in the epilog, because we
don't bump down the stack pointer.

Reviewers: dschuff

Subscribers: jgravelle-google, sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51114

llvm-svn: 340454
2018-08-22 21:13:49 +00:00
Philip Reames
05de5c7fdc [AST] Add a test for attribute intersection
Already works, but I initially convinced myself it doesn't, so add a test which shows it does.  :)

llvm-svn: 340453
2018-08-22 21:10:56 +00:00
Martin Storsjo
ace715a4e3 [ARM] Avoid injecting constant islands in movw+movt pairs on Windows
On Windows, movw+movt pairs with relocations are handled with a single
relocation that covers them both. Therefore we can't inject anything
between these instructions, otherwise the relocation (which in LLVM
only is treated as the movw instruction's relocation, while the movt
instruction's relocation is dropped) will end up bogus.

These instructions are bundled up until right before the constant
islands pass, making this effectively the only place that can split
them apart.

Differential Revision: https://reviews.llvm.org/D51032

llvm-svn: 340451
2018-08-22 20:34:12 +00:00
Martin Storsjo
f934a89e05 [ARM] Move machine operand target flags to ARMBaseInstrInfo
This makes sure the flags are available for use for thumb MIR as well.

A test that requires this will be added in the next commit.

llvm-svn: 340450
2018-08-22 20:34:06 +00:00
Krzysztof Parzyszek
a83db8d2cb [Hexagon] Enable interleaving in loop vectorizer
llvm-svn: 340447
2018-08-22 20:15:04 +00:00
Eli Friedman
c4518513f4 [ARM] Handle all-ones mask explicitly in targetShrinkDemandedConstant.
This avoids a potential infinite loop setting and unsetting bits in the
mask.

Reduced from a failure on the polly-aosp bot.

Differential Revision: https://reviews.llvm.org/D51066

llvm-svn: 340446
2018-08-22 20:13:45 +00:00
Alina Sbirlea
facf6eb783 Update MemorySSA in LoopSimplifyCFG.
Summary:
Add MemorySSA as a dependency to LoopSimplifyCFG and preserve it.
Disabled by default until all passes preserve MemorySSA.

Reviewers: bogner, chandlerc

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D50911

llvm-svn: 340445
2018-08-22 20:10:21 +00:00
Alina Sbirlea
0cb48ba57d Update MemorySSA in LoopInstSimplify.
Summary:
Add MemorySSA as a depency to LoopInstInstSimplify and preserve it.
Disabled by default until all passes preserve MemorySSA.

Reviewers: chandlerc

Subscribers: sanjoy, jlebar, Prazek, george.burgess.iv, llvm-commits

Differential Revision: https://reviews.llvm.org/D50906

llvm-svn: 340444
2018-08-22 20:05:21 +00:00
Philip Reames
eff472e2cf [AA] Remove a needless variable [NFC]
There's no need to track a seperate variable for argmemonly aliasing.  This falls out naturally of the modinfo union.  Note that we may return earlier than we would have earlier if all arguments are explicitly readnone.  The overall result doesn't change, just how we get there.

llvm-svn: 340443
2018-08-22 19:50:45 +00:00
Craig Topper
d4ada43f34 [X86] Replace (32/64 - n) shift amounts with (neg n) since the shift amount is masked in hardware
Inspired by what AArch64 does for shifts, this patch attempts to replace shift amounts with neg if we can.

This is done directly as part of isel so its as late as possible to avoid breaking some BZHI patterns since those patterns need an unmasked (32-n) to be correct.

To avoid manual load folding and custom instruction selection for the negate. I've inserted new nodes in the DAG above the shift node in topological order.

Differential Revision: https://reviews.llvm.org/D48789

llvm-svn: 340441
2018-08-22 19:39:09 +00:00
Philip Reames
d38b4efbef [AST] Minor whitespace cleanup [NFC]
llvm-svn: 340440
2018-08-22 19:30:46 +00:00
Heejin Ahn
21e1e2b060 [WebAssembly] Remove MachineFrameInfo arg from checking functions (NFC)
Summary:
There are several functions in the form of `has***` or `needs***` in
`WebAssemblyFrameLowering` and its `MachineFrameInfo` argument can be
obtained from `MachineFunction` so it is not necessarily has to be
passed from a caller. Also, it is more in line with other overriden
fuctions like `hasBP` or `hasReservedCallFrame`, which also take only
`MachineFunction` argument.

Reviewers: dschuff

Subscribers: sbc100, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51116

llvm-svn: 340438
2018-08-22 18:53:48 +00:00
Chris Bieneman
ce46b06c17 [CMake] Remove unneeded and outdated policy
This was needed way back because we didn't properly handle that the SOURCES property of a target could have things that weren't source files to compile. Almost 2 years ago Takumi fixed that, and now CMake is throwing warnings that we should get off the old behavior.

llvm-svn: 340436
2018-08-22 18:41:14 +00:00
Chris Bieneman
fde8ce5023 [CMake] Use LLVM_ENABLE_IDE instead of CMAKE_CONFIGURATION_TYPES
There are several places where we use CMAKE_CONFIGURATION_TYPES to determine if we are using an IDE generator and in turn decide not to generate some of the convenience targets (like all the install-* and check-llvm-* targets). This decision is made because IDEs don't always deal well with the thousands of targets LLVM can generate.

This approach does not work for Visual Studio 15's new CMake integration. Because VS15 uses a Ninja generator, it isn't a multi-configuration build, and generating all these extra targets mucks up the UI and adds little value.

With this change we still don't generate these targets by default for Visual Studio and Xcode generators, and LLVM_ENABLE_IDE becomes a switch that can be enabled on the VS15 CMake builds, to improve the IDE experience.

llvm-svn: 340435
2018-08-22 18:40:24 +00:00
Craig Topper
60505cd1aa [X86] In OptimizeLEAs pass, check that the key is in the LEAs map before accessing
When the key is not already in the map, the access operator[] creates an empty value and grows the map.
Resizing a map is very slow, so this needs to be avoided.

Found with csmith + asserts.

May help with
https://bugs.llvm.org/show_bug.cgi?id=25843

Patch by Tom Rix.

Differential Revision: https://reviews.llvm.org/D50780

llvm-svn: 340434
2018-08-22 18:24:13 +00:00
Heejin Ahn
70e93950c8 [WebAssembly] Add hasSideEffects flag to catch instructions
Summary:
`catch` instruction certainly has rather huge side effects and the flag
was missing. At the moment this does not change any unit tests we
currently have.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D50919

llvm-svn: 340433
2018-08-22 18:22:45 +00:00
Vedant Kumar
d10dbb804e [CodeGenPrepare] Set debug locs when folding a comparison into a uadd.with.overflow
CGP can replace a branch + select with a uadd.with.overflow. Teach it to
set debug locations as it does this.

llvm-svn: 340432
2018-08-22 18:15:03 +00:00
Matt Davis
bba94ca910 [llvm-mca] Clean up a comment about the Context class. NFC.
llvm-svn: 340431
2018-08-22 18:03:58 +00:00
George Burgess IV
bad97b0986 [MemorySSA] Move two simple getters; NFC
We're calling these functions quite a bit from outside of MemorySSA.cpp
now. Given that they're relatively simple one-liners, I think the style
preference is to have them inline.

llvm-svn: 340430
2018-08-22 18:02:46 +00:00
Aditya Nandakumar
436a04bdef [GISel]: Add legalization support for widening bit counting operations
https://reviews.llvm.org/D51053

Added legalization for WidenScalar of various bitcounting opcodes.

Reviewed by arsenm.

llvm-svn: 340429
2018-08-22 17:59:18 +00:00
Sanjay Patel
3423a22a85 [x86] add tests for load scalar + insertelement; NFC
llvm-svn: 340425
2018-08-22 17:46:28 +00:00
Sam Clegg
29a6ddeafd [WebAssembly] Ensure relocation entries are ordered by offset
wasm-lld expects relocation entries to be sorted by offset.  In most
cases llvm produces them in order, but the CODE section (which combines
many MCSections) is an exception because we order the functions in
Symbol order, not in section order.  What is more, its not clear weather
`recordRelocation` is guaranteed to be called in offset order so this
sort of most likely needed in the general case too.

Differential Revision: https://reviews.llvm.org/D51065

llvm-svn: 340423
2018-08-22 17:27:31 +00:00
Matt Davis
1e183f4e6a [llvm-mca] Remove unused decl. NFC.
llvm-svn: 340422
2018-08-22 17:15:25 +00:00
Samuel Pitoiset
d11ff9dda6 AMDGPU: bump AS.MAX_COMMON_ADDRESS to 6 since 32-bit addr space
32-bit constant address space is declared as 6, so the
maximum number of address spaces is 6, not 5.

Fixes "LLVM ERROR: Pointer address space out of range".

v5: rename MAX_COMMON_ADDRESS to MAX_AMDGPU_ADDRESS
v4: - fix compilation issues
    - fix out of bounds access
v3: use static_assert()
v2: add a very simple test for 32-bit addr space

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106630
llvm-svn: 340417
2018-08-22 16:08:48 +00:00
Samuel Pitoiset
a084b54d47 AMDGPU: fix existing alias rules for constant and global
Constant and global may alias, also one rules table wasn't
ordered correctly.

Pinpointed by Matt.

v2: add a test with swapped parameters
llvm-svn: 340416
2018-08-22 16:08:43 +00:00
Simon Pilgrim
a188ef13f1 [X86][SSE] LowerMULH vXi8 - use SSE shifts directly.
We know these vXi16 extended cases are legal constant splat shifts.

llvm-svn: 340414
2018-08-22 15:37:11 +00:00
Sam Parker
59400754bc [ARM] Rotated operand patterns for *xtb16
Add intrinsic isel patterns for sxtb16, sxtab16, uxtb16 and uxtab16
so that they can perform a ror.

Differential Revision: https://reviews.llvm.org/D51034

llvm-svn: 340405
2018-08-22 12:58:36 +00:00
David Green
61ff754920 [AArch64] Add Tiny Code Model for AArch64
This adds the plumbing for the Tiny code model for the AArch64 backend. This,
instead of loading addresses through the normal ADRP;ADD pair used in the Small
model, uses a single ADR. The 21 bit range of an ADR means that the code and
its statically defined symbols need to be within 1MB of each other.

This makes it mostly interesting for embedded applications where we want to fit
as much as we can in as small a space as possible.

Differential Revision: https://reviews.llvm.org/D49673

llvm-svn: 340397
2018-08-22 11:31:39 +00:00
Matt Arsenault
7cfa9a2529 AMDGPU: Fix not respecting byval alignment in call frame setup
This was hackily adding in the 4-bytes reserved for the callee's
emergency stack slot. Treat it like a normal stack allocation
so we get the correct alignment padding behavior. This fixes
an inconsistency between the caller and callee.

llvm-svn: 340396
2018-08-22 11:09:45 +00:00
Andrea Di Biagio
208015540d [llvm-mca] Improved code comments and moved some method definitions from Scheduler.h to Scheduler.cpp. NFC
llvm-svn: 340395
2018-08-22 10:23:28 +00:00
Simon Pilgrim
0ee0efc180 [X86][SSE] Add sdiv test case from PR38658
llvm-svn: 340393
2018-08-22 09:47:12 +00:00
Stefan Maksimovic
7a65ab4d76 [mips] Handle missing CondCodes
Add patterns for unhandled CondCode enumerables:
SETEQ, SETGE, SETGT, SETLE, SETLT, SETNE.

Stated at the ISD::CondCode enum declaration:
`All of these (except for the 'always folded ops')
should be handled for floating point.`

Add patterns which use these nodes, same as corresponding
'ordered' CondCode nodes.

Referring to 'Ordered means that neither operand is a QNAN'
we assume it is safe to match ex. SETLT node to the same
instruction as SETOLT.

Differential Revision: https://reviews.llvm.org/D50757

llvm-svn: 340392
2018-08-22 09:34:44 +00:00
Dean Michael Berris
f9e1fbc647 [XRay] Refactor file header reading (NFC)
Summary:
This patch moves out the definition of the XRay log file header from
binary logs into its own header and implementation file.

This is one part of the refactoring being done in D50441.

Reviewers: eizan

Subscribers: mgorny, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D51086

llvm-svn: 340389
2018-08-22 07:37:55 +00:00
Philip Reames
945d43be81 [AST] Fix a whitespace typo [NFC]
llvm-svn: 340384
2018-08-22 03:36:42 +00:00
Philip Reames
bc41d290af [AST] Reorder code to reduce a future patch diff [NFC]
llvm-svn: 340383
2018-08-22 03:33:55 +00:00
Philip Reames
d401425eb2 [AST] Move a function definition into the cpp [NFC]
llvm-svn: 340382
2018-08-22 03:32:52 +00:00
Max Kazantsev
c8eea01630 [GuardWidening] Ignore guards with trivial conditions
Guard widening should not spend efforts on dealing with guards with trivial true/false conditions.
Such guards can easily be eliminated by any further cleanup pass like instcombine. However we
should not unconditionally delete them because it may be profitable to widen other conditions
into such guards.

Differential Revision: https://reviews.llvm.org/D50247
Reviewed By: fedor.sergeev

llvm-svn: 340381
2018-08-22 02:40:49 +00:00
Fangrui Song
8c95eeae9d [gold] -thinlto-object-suffix-replace: don't append new suffix if path does not end with old suffix
Summary: This is to be consistent with lld behavior since rLLD340364.

Reviewers: tejohnson

Reviewed By: tejohnson

Subscribers: steven_wu, eraman, mehdi_amini, inglorion, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51060

llvm-svn: 340380
2018-08-22 02:11:36 +00:00
Vedant Kumar
5602b833c9 [CodeGenPrepare] Set debug loc when widening a switch condition
Set a debug location on the cast instruction used to widen a switch
condition.

llvm-svn: 340379
2018-08-22 01:23:31 +00:00
Bob Haarman
2be365cbce [Support][CachePruning] prune least recently accessed files first
Summary:
Before this change, pruning order was based on size. This changes it
to be based on time of last use instead, preferring to keep recently
used files and prune older ones.

Reviewers: pcc, rnk, espindola

Reviewed By: rnk

Subscribers: emaste, arichardson, hiraditya, steven_wu, dexonsmith, llvm-commits

Differential Revision: https://reviews.llvm.org/D51062

llvm-svn: 340374
2018-08-22 00:52:16 +00:00
Heejin Ahn
5835a4ffcf [WebAssembly] Fix typos in mem.grow/memory.grow opcodes
This should be not 0x3f but 0x40.

llvm-svn: 340373
2018-08-22 00:33:34 +00:00
Heejin Ahn
b3bb3dc028 [WebAssembly] Change comments on SP writing back (NFC)
Summary: We now write back not to memory but to __stack_pointer global.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D51074

llvm-svn: 340372
2018-08-22 00:20:02 +00:00
Vedant Kumar
c0dd251e86 [CodeGenPrepare] Set debug locations when splitting selects
When splitting a select into a diamond, set debug locations on
newly-created branch instructions and phi nodes.

llvm-svn: 340371
2018-08-22 00:10:37 +00:00
Vedant Kumar
8314ccb02a [CodeGenPrepare] Clean up dbg.value use-before-def as late as possible
CodeGenPrepare has a strategy for moving dbg.values so that a value's
definition always dominates its debug users. This cleanup was happening
too early (before certain CGP transforms were run), resulting in some
dbg.value use-before-def errors.

Perform this cleanup as late as possible to avoid use-before-def.

llvm-svn: 340370
2018-08-21 23:43:08 +00:00
Vedant Kumar
a5b0ee143f [CodeGenPrepare] Pre-commit debug info test for optimizeSelectInst
This test shows that optimizeSelectInst splits a select and sinks a
`fdiv` operation to one side of the diamond. However, the dbg.value for
the operation isn't moved.

llvm-svn: 340369
2018-08-21 23:42:53 +00:00
Vedant Kumar
b5a8c81ac9 [CodeGenPrepare] Scan past debug intrinsics to find select candidates (NFC)
In optimizeSelectInst, when scanning for candidate selects to rewrite
into branches, scan past debug intrinsics. This makes the debug-enabled
and non-debug paths through optimizeSelectInst more congruent.

NFC because every select is eventually visited either way.

llvm-svn: 340368
2018-08-21 23:42:38 +00:00