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Commit Graph

18233 Commits

Author SHA1 Message Date
Jim Grosbach
3eb4f0de5e Update comments. These are for assembler, too.
llvm-svn: 135107
2011-07-13 23:33:10 +00:00
Owen Anderson
c68f12ff30 Add a target-indepedent entry to MCInstrDesc to describe the encoded size of an opcode. Switch ARM over to using that rather than its own special MCInstrDesc bits.
llvm-svn: 135106
2011-07-13 23:22:26 +00:00
Bill Wendling
e896e46a8c Add code to handle a "frameless" unwind stack.
The frameless unwind stack has a special encoding, the algorithm for which is in
"permuteEncode".

llvm-svn: 135103
2011-07-13 23:03:31 +00:00
Jim Grosbach
c0ec4205e2 ARM Assembler support for DBG instruction.
Add range checking and testing for parsing and encoding of DBG instruction.

llvm-svn: 135102
2011-07-13 22:59:38 +00:00
Jim Grosbach
c9e49f3b51 Revert 135093. Think-o.
llvm-svn: 135094
2011-07-13 22:06:11 +00:00
Jim Grosbach
545a3f4802 Correct range for thumb co-processor immediate
llvm-svn: 135093
2011-07-13 22:03:11 +00:00
Jim Grosbach
fd2ebb4552 Range checking for CDP[2] immediates.
llvm-svn: 135092
2011-07-13 22:01:08 +00:00
Bruno Cardoso Lopes
c0401dddf7 Make X86ISD::ANDNP more general and Codegen 256-bit VANDNP. A more
general version of X86ISD::ANDNP also opened the room for a little bit
of refactoring.

llvm-svn: 135088
2011-07-13 21:36:51 +00:00
Bruno Cardoso Lopes
b98f50da03 The target specific node PANDN name is misleading. That happens because
it's later selected to a ANDNPD/ANDNPS instruction instead of the PANDN
instruction. Rename it.

llvm-svn: 135087
2011-07-13 21:36:47 +00:00
Jim Grosbach
76ba2e7e9c Cleanup Thumb co-processor instructions a bit.
Combine redundant base classes and such. No indended functional change.

llvm-svn: 135085
2011-07-13 21:35:10 +00:00
Eli Friedman
30d557cc28 Make sure we don't combine a large displacement and a frame index in the same addressing mode on x86-64. It can overflow, leading to a crash/miscompile.
<rdar://problem/9763308>

llvm-svn: 135084
2011-07-13 21:29:53 +00:00
Jim Grosbach
385d9a3e57 Parameterize away the ARM T1Cop class.
llvm-svn: 135082
2011-07-13 21:17:59 +00:00
Jim Grosbach
d3b15141b8 Fix predicates for Thumb co-processor instructions.
They're all Thumb2 only, not just some of them. More refactoring cleanup
coming.

llvm-svn: 135081
2011-07-13 21:14:23 +00:00
Eli Friedman
e0a117fbdf Refactor out checking for displacements on x86-64 addressing modes. No functionality change. Refactoring in preparation for an additional safety check in FoldOffsetIntoAddress.
Part of <rdar://problem/9763308>.

llvm-svn: 135079
2011-07-13 20:44:23 +00:00
Jim Grosbach
93cf7d8372 Fix encoding for ARM BXJ instruction.
llvm-svn: 135077
2011-07-13 20:25:01 +00:00
Jim Grosbach
4ca79b8d2c Fix encoding of predicate bits on ARM BX_pred.
llvm-svn: 135076
2011-07-13 20:21:31 +00:00
Jim Grosbach
0caa098513 Range checking for 16-bit immediates in ARM assembly.
llvm-svn: 135071
2011-07-13 20:10:10 +00:00
Evan Cheng
7bdc771798 Fix up TargetLoweringObjectFile ctors to properly initialize fields.
llvm-svn: 135068
2011-07-13 19:54:59 +00:00
Jim Grosbach
ab030d8a81 Give the ARM BKPT instruction the right operand type.
The immediate is of limited range and the operand type should reflect that.

llvm-svn: 135066
2011-07-13 19:24:09 +00:00
Jim Grosbach
9e021b5281 Add tests for ARM parsing of 'BKPT' instruction.
llvm-svn: 135063
2011-07-13 19:17:36 +00:00
Jim Grosbach
5c366bfb36 Improve ARM assembly parsing diagnostics a bit.
Catch potential cascading errors on a malformed so_reg operand and bail after
the first error.

Add some tests for the diagnostics we do want.

llvm-svn: 135055
2011-07-13 18:49:30 +00:00
Jim Grosbach
7dbb39dffa Destination register operand is optional for ADC and SBC ARM.
llvm-svn: 135052
2011-07-13 17:57:17 +00:00
Jim Grosbach
5db1296fcd Flesh out ARM Parser support for shifted-register operands.
Now works for parsing register shifted register and register shifted
immediate arithmetic instructions, including the 'rrx' rotate with extend.

llvm-svn: 135049
2011-07-13 17:50:29 +00:00
Jim Grosbach
bcc9f6f31a 80 columns.
llvm-svn: 135047
2011-07-13 17:25:55 +00:00
Jim Grosbach
e0fc4019f9 Update MCParsedAsmOperand debug methods.
Update the debug output interface for MCParsedAsmOperand to have a print()
method which takes an output stream argument, an << operator which invokes
the print method using the given stream, and a dump() method which prints
the operand to the dbgs() stream. This makes the interface more consistent
with the rest of LLVM, and more convenient to use at the debugger command
line.

llvm-svn: 135043
2011-07-13 15:34:57 +00:00
Jay Foad
88fb4f4597 Convert InsertValueInst and ExtractValueInst APIs to use ArrayRef.
llvm-svn: 135040
2011-07-13 10:26:04 +00:00
Evan Cheng
ddc415a907 Add an entry.
llvm-svn: 135024
2011-07-13 01:33:00 +00:00
Bruno Cardoso Lopes
cb49278ad6 AVX Codegen support for 256-bit versions of vandps, vandpd, vorps, vorpd, vxorps, vxorpd
llvm-svn: 135023
2011-07-13 01:15:33 +00:00
Bill Wendling
e6de1eeb86 Don't emit the FDE end label if the last thing emitted was a compact unwind and
not the FDE

llvm-svn: 135020
2011-07-13 00:49:09 +00:00
Eli Friedman
8c4106f2a5 Add an assert (which should never trigger) that triggers on a testcase I'm looking at.
llvm-svn: 135018
2011-07-13 00:44:29 +00:00
Evan Cheng
37ff73dfaf Improve codegen for select's:
if (x != 0) x = 1
if (x == 1) x = 1

Previous codegen looks like this:
        mov     r1, r0
        cmp     r1, #1
        mov     r0, #0
        moveq   r0, #1

The naive lowering select between two different values. It should recognize the
test is equality test so it's more a conditional move rather than a select:
        cmp     r0, #1
        movne   r0, #0

rdar://9758317

llvm-svn: 135017
2011-07-13 00:42:17 +00:00
Bill Wendling
78fce7597f Assign variable before we test it.
llvm-svn: 135015
2011-07-13 00:23:39 +00:00
Bill Wendling
d61dd044e1 Fix obvious think-o.
llvm-svn: 135014
2011-07-13 00:20:09 +00:00
Bill Wendling
9e1528dea4 Clean up the handling of an EBP/RBP unwind frame pointer. In particular, don't
assert when the frame pointer is -1 (i.e., the function is "frameless").

Still to do: "frameless" unwind information.

llvm-svn: 135013
2011-07-13 00:16:14 +00:00
Bill Wendling
bd3639ccc1 There is a cyclic dependency between MC and Target if this method is out-of-line.
llvm-svn: 135006
2011-07-12 22:35:01 +00:00
Jay Foad
cbe48cd2ac Second attempt at de-constifying LLVM Types in FunctionType::get(),
StructType::get() and TargetData::getIntPtrType().

llvm-svn: 134982
2011-07-12 14:06:48 +00:00
Tobias Grosser
449d23f471 Remove IntegerType constness from TargetData
llvm-svn: 134978
2011-07-12 11:36:58 +00:00
Bill Wendling
6bcdd65b95 Revert r134893 and r134888 (and related patches in other trees). It was causing
an assert on Darwin llvm-gcc builds.

Assertion failed: (castIsValid(op, S, Ty) && "Invalid cast!"), function Create, file /Users/buildslave/zorg/buildbot/smooshlab/slave-0.8/build.llvm-gcc-i386-darwin9-RA/llvm.src/lib/VMCore/Instructions.cpp, li\
ne 2067.
etc.

http://smooshlab.apple.com:8013/builders/llvm-gcc-i386-darwin9-RA/builds/2354

--- Reverse-merging r134893 into '.':
U    include/llvm/Target/TargetData.h
U    include/llvm/DerivedTypes.h
U    tools/bugpoint/ExtractFunction.cpp
U    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/ARM/ARMGlobalMerge.cpp
U    lib/Target/TargetData.cpp
U    lib/VMCore/Constants.cpp
U    lib/VMCore/Type.cpp
U    lib/VMCore/Core.cpp
U    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Instrumentation/ProfilingUtils.cpp
U    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/CodeGen/SjLjEHPrepare.cpp
--- Reverse-merging r134888 into '.':
G    include/llvm/DerivedTypes.h
U    include/llvm/Support/TypeBuilder.h
U    include/llvm/Intrinsics.h
U    unittests/Analysis/ScalarEvolutionTest.cpp
U    unittests/ExecutionEngine/JIT/JITTest.cpp
U    unittests/ExecutionEngine/JIT/JITMemoryManagerTest.cpp
U    unittests/VMCore/PassManagerTest.cpp
G    unittests/Support/TypeBuilderTest.cpp
U    lib/Target/MBlaze/MBlazeIntrinsicInfo.cpp
U    lib/Target/Blackfin/BlackfinIntrinsicInfo.cpp
U    lib/VMCore/IRBuilder.cpp
G    lib/VMCore/Type.cpp
U    lib/VMCore/Function.cpp
G    lib/VMCore/Core.cpp
U    lib/VMCore/Module.cpp
U    lib/AsmParser/LLParser.cpp
U    lib/Transforms/Utils/CloneFunction.cpp
G    lib/Transforms/Utils/CodeExtractor.cpp
U    lib/Transforms/Utils/InlineFunction.cpp
U    lib/Transforms/Instrumentation/GCOVProfiling.cpp
U    lib/Transforms/Scalar/ObjCARC.cpp
U    lib/Transforms/Scalar/SimplifyLibCalls.cpp
U    lib/Transforms/Scalar/MemCpyOptimizer.cpp
G    lib/Transforms/IPO/DeadArgumentElimination.cpp
U    lib/Transforms/IPO/ArgumentPromotion.cpp
U    lib/Transforms/InstCombine/InstCombineCompares.cpp
U    lib/Transforms/InstCombine/InstCombineAndOrXor.cpp
U    lib/Transforms/InstCombine/InstCombineCalls.cpp
U    lib/CodeGen/DwarfEHPrepare.cpp
U    lib/CodeGen/IntrinsicLowering.cpp
U    lib/Bitcode/Reader/BitcodeReader.cpp

llvm-svn: 134949
2011-07-12 01:15:52 +00:00
Evan Cheng
b25cb9755b Most MCCodeEmitter's don't meed MCContext.
llvm-svn: 134922
2011-07-11 21:24:15 +00:00
Jim Grosbach
fae61bb435 Fix recognition of ARM 'adcs' mnemonic.
The 'CS' is not a predication suffix in this case.

llvm-svn: 134903
2011-07-11 17:09:57 +00:00
Jim Grosbach
93f2ebb5e7 Simplify printing of ARM shifted immediates.
Print shifted immediate values directly rather than as a payload+shifter
value pair. This makes for more readable output assembly code, simplifies
the instruction printer, and is consistent with how Thumb immediates are
 displayed.

llvm-svn: 134902
2011-07-11 16:48:36 +00:00
Jay Foad
0ec904296e De-constify Types in StructType::get() and TargetData::getIntPtrType().
llvm-svn: 134893
2011-07-11 09:56:20 +00:00
Jay Foad
d618fa83b7 De-constify Types in FunctionType::get().
llvm-svn: 134888
2011-07-11 07:56:41 +00:00
Evan Cheng
1346a63a0f - Eliminate MCCodeEmitter's dependency on TargetMachine. It now uses MCInstrInfo
and MCSubtargetInfo.
- Added methods to update subtarget features (used when targets automatically
  detect subtarget features or switch modes).
- Teach X86Subtarget to update MCSubtargetInfo features bits since the
  MCSubtargetInfo layer can be shared with other modules.
- These fixes .code 16 / .code 32 support since mode switch is updated in
  MCSubtargetInfo so MC code emitter can do the right thing.

llvm-svn: 134884
2011-07-11 03:57:24 +00:00
Cameron Zwarich
ff18692885 Fix <rdar://problem/9751331>.
llvm-svn: 134882
2011-07-11 01:29:42 +00:00
Jakub Staszak
3e40788ce3 Use BranchProbability instead of floating points in IfConverter.
llvm-svn: 134858
2011-07-10 02:58:07 +00:00
Chris Lattner
a106725fc5 Land the long talked about "type system rewrite" patch. This
patch brings numerous advantages to LLVM.  One way to look at it
is through diffstat:
 109 files changed, 3005 insertions(+), 5906 deletions(-)

Removing almost 3K lines of code is a good thing.  Other advantages
include:

1. Value::getType() is a simple load that can be CSE'd, not a mutating
   union-find operation.
2. Types a uniqued and never move once created, defining away PATypeHolder.
3. Structs can be "named" now, and their name is part of the identity that
   uniques them.  This means that the compiler doesn't merge them structurally
   which makes the IR much less confusing.
4. Now that there is no way to get a cycle in a type graph without a named
   struct type, "upreferences" go away.
5. Type refinement is completely gone, which should make LTO much MUCH faster
   in some common cases with C++ code.
6. Types are now generally immutable, so we can use "Type *" instead 
   "const Type *" everywhere.

Downsides of this patch are that it removes some functions from the C API,
so people using those will have to upgrade to (not yet added) new API.  
"LLVM 3.0" is the right time to do this.

There are still some cleanups pending after this, this patch is large enough
as-is.

llvm-svn: 134829
2011-07-09 17:41:24 +00:00
Evan Cheng
a8ec7e0538 Revert accidental commit.
llvm-svn: 134800
2011-07-09 06:26:27 +00:00
Evan Cheng
c9e252df68 Change createAsmParser to take a MCSubtargetInfo instead of triple,
CPU, and feature string. Parsing some asm directives can change
subtarget state (e.g. .code 16) and it must be reflected in other
modules (e.g. MCCodeEmitter). That is, the MCSubtargetInfo instance
must be shared.

llvm-svn: 134795
2011-07-09 05:47:46 +00:00
Eli Friedman
1f8926e94d Really force on 64bit for 64-bit targets. Should fix remaining failures on unknown x86/non-x86 targets.
llvm-svn: 134773
2011-07-08 23:43:01 +00:00