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Commit Graph

213718 Commits

Author SHA1 Message Date
Abhina Sreeskantharajan
3f0b170fdd [SystemZ][z/OS][Windows] Add new OF_TextWithCRLF flag and use this flag instead of OF_Text
Problem:
On SystemZ we need to open text files in text mode. On Windows, files opened in text mode adds a CRLF '\r\n' which may not be desirable.

Solution:
This patch adds two new flags

  - OF_CRLF which indicates that CRLF translation is used.
  - OF_TextWithCRLF = OF_Text | OF_CRLF indicates that the file is text and uses CRLF translation.

Developers should now use either the OF_Text or OF_TextWithCRLF for text files and OF_None for binary files. If the developer doesn't want carriage returns on Windows, they should use OF_Text, if they do want carriage returns on Windows, they should use OF_TextWithCRLF.

So this is the behaviour per platform with my patch:

z/OS:
OF_None: open in binary mode
OF_Text : open in text mode
OF_TextWithCRLF: open in text mode

Windows:
OF_None: open file with no carriage return
OF_Text: open file with no carriage return
OF_TextWithCRLF: open file with carriage return

The Major change is in llvm/lib/Support/Windows/Path.inc to only set text mode if the OF_CRLF is set.
```
  if (Flags & OF_CRLF)
    CrtOpenFlags |= _O_TEXT;
```

These following files are the ones that still use OF_Text which I left unchanged. I modified all these except raw_ostream.cpp in recent patches so I know these were previously in Binary mode on Windows.
./llvm/lib/Support/raw_ostream.cpp
./llvm/lib/TableGen/Main.cpp
./llvm/tools/dsymutil/DwarfLinkerForBinary.cpp
./llvm/unittests/Support/Path.cpp
./clang/lib/StaticAnalyzer/Core/HTMLDiagnostics.cpp
./clang/lib/Frontend/CompilerInstance.cpp
./clang/lib/Driver/Driver.cpp
./clang/lib/Driver/ToolChains/Clang.cpp

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D99426
2021-04-06 07:23:31 -04:00
Kerry McLaughlin
92b30fa263 [LoopVectorize] Change the identity element for FAdd
Changes getRecurrenceIdentity to always return a neutral value of -0.0 for FAdd.

Reviewed By: dmgreen, spatel

Differential Revision: https://reviews.llvm.org/D98963
2021-04-06 12:13:43 +01:00
Florian Hahn
99c48b5190 [VPlan] Print VPValue operands for VPWidenPHI if possible.
For VPWidenPHIRecipes that model all incoming values as VPValue
operands, print those operands instead of printing the original PHI.

D99294 updates recipes of reduction PHIs to use the VPValue for the
incoming value from the loop backedge, making use of this new printing.
2021-04-06 12:11:21 +01:00
Dmitry Preobrazhensky
546b76abf9 [AMDGPU][MC][GFX9] Corrected SMEM decoding
Corrected SMEM decoding when IMM=0 and OFFSET>127

Fixed bug 49819 (https://bugs.llvm.org/show_bug.cgi?id=49819)

Differential Revision: https://reviews.llvm.org/D99804
2021-04-06 14:10:46 +03:00
Simon Pilgrim
d50aefd3c1 [CostModel][X86] Improve accuracy of vXi8 multiply reduction costs
After rG47321c311bdbe0145b9bf45d822185c37b19fa50 we promote vXi8 reductions to vXi16 to create a much faster PMULLW mul reduction, followed by a (free) truncation. This avoids the high cost of repeated vXi8 multiplications (which extend+multiply+truncate to/from vXi16 types....).

Fixes the missing vXi8 mul reduction vectorization in PR42674 (Comment #20) 'mul16' test case.
2021-04-06 11:53:22 +01:00
Jay Foad
d2ae27100c [AMDGPU] Regenerate checks to fix prefixes broken in D96340. NFC. 2021-04-06 11:43:53 +01:00
Thomas Preud'homme
ea67d83caf [test, AArch64] Fix use of var defined in CHECK-NOT
LLVM test CodeGen/AArch64/aarch64-tbz.ll tries to check for the absence
of a sequence of instructions with several CHECK-NOT with one of those
directives using a variable defined in another. However CHECK-NOT are
checked independently so that is using a variable defined in a pattern
that should not occur in the input.

This commit removes the definition and uses of variable to check each
line independently, making the check stronger than the current one. It
also removes unnecessary regex match for labels.

Reviewed By: dmgreen

Differential Revision: https://reviews.llvm.org/D99602
2021-04-06 10:45:08 +01:00
Simon Pilgrim
46491192bc [PhaseOrdering] Add PR45687 test coverage
This is a mixture of instcombine/simplfycfg/instcombine to recognise and then remove the abs pattern
2021-04-06 10:31:42 +01:00
madhur13490
377aa4b4a7 [IR] Ignore bitcasts of function pointers which are only used as callees in callbase instruction
This patch enhances hasAddressTaken() to ignore bitcasts as a
callee in callbase instruction. Such bitcast usage doesn't really take
the address in a useful meaningful way.

Reviewed By: rampitec

Differential Revision: https://reviews.llvm.org/D98884
2021-04-06 09:23:46 +00:00
Simon Pilgrim
8cd06abbb1 [KnownBits] Rename KnownBits::computeForMul to KnownBits::mul. NFCI.
As promised in D98866
2021-04-06 10:11:41 +01:00
Sjoerd Meijer
334683ea40 [AArch64] Default to zero-cycle-zeroing FP registers
It is generally beneficial to prefer "movi d0, #0" over "fmov s0, wzr" as this
is most efficient across all cores; it is recognised as a zeroing idiom. For
newer cores, fmov instructions can also be eliminated early and there is no
difference with movi, but some implementations lack this so is not true for
other/older cores. Thus this standardises on using movi as this should always
gives the same or better performance than the fmov with wzr.

Differential Revision: https://reviews.llvm.org/D99586
2021-04-06 09:47:50 +01:00
Sam Parker
fe1910b380 [NFC][WebAssembly] Removed mangled name from test. 2021-04-06 08:55:27 +01:00
Sjoerd Meijer
febbc440a6 [AArch64] Use 64-bit movi for zeroing halfs/floats
This was using the .2d variant which zeros 128 bits, but using the .2s variant
that zeros 64 bits is faster on some cores.

This is a prep step for D99586 to always using movi for zeroing floats.

Differential Revision: https://reviews.llvm.org/D99710
2021-04-06 08:42:13 +01:00
Jay Foad
4cec125a5f [AMDGPU] Add some missing testing for new subtargets gfx90a and gfx90c
Differential Revision: https://reviews.llvm.org/D99647
2021-04-06 08:38:59 +01:00
Yevgeny Rouban
16e6aca928 [NewPM] Fix unused lambda capture build error
Fixes commit 39e3e3aa51d: Redesign of PreserveCFG Checker
2021-04-06 13:14:16 +07:00
Yevgeny Rouban
7d89a8898f [NewPM] Redesign of PreserveCFG Checker
The reason for the NewPM redesign is described in the commit
  cba3e783389a: [NewPM] Disable PreservedCFGChecker ...

The checker introduces an internal custom CFG analysis that tracks
current up-to date CFG snapshot. The analysis is invalidated along
any other CFG related analysis (the key is CFGAnalyses). If the CFG
analysis is not invalidated at a functional pass exit then the checker
asserts that the CFG snapshot taken from this analysis is equals to
a snapshot of the current CFG.

Along the way:
- the function CFG::printDiff() is simplified by removing function
  name calculation. The name is printed by the caller;
- fixed CFG invalidated condition (see CFG::invalidate());
- StandardInstrumentations::registerCallbacks() gets additional
  optional parameter of type FunctionAnalysisManager*, which is
  needed by the checker to get the custom CFG analysis;
- several PM related tests updated to explicitly set
  -verify-cfg-preserved=1 as they need.

This patch is safe to land as the CFGChecker is left switched off
(the options -verify-cfg-preserved is false by default). It will be
switched on by a separate patch to minimize possible reverts.

Reviewed By: skatkov, kuhar

Differential Revision: https://reviews.llvm.org/D91327
2021-04-06 12:35:49 +07:00
Serguei Katkov
6b7e7aec4f [Statepoint] Factor-out utility function to get non-foldable area of STATEPOINT like instructions. NFC
Reviewers: reames, dantrushin
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D99875
2021-04-06 11:44:37 +07:00
Yevgeny Rouban
5ba39df635 [NewPM] Change tests to run them without PreserveCFGChecker. NFC
Change several pass sequence sensitive tests to be indifferent
to the PreserveCFGChecker by explicitly settting the option
-verify-cfg-preserved=0. It is a preparation step that allows
a redesign of PreserveCFGChecker.

Reviewed By: skatkov

Differential Revision: https://reviews.llvm.org/D99878
2021-04-06 11:33:07 +07:00
Craig Topper
a6d1d552c3 [RISCV] When custom iseling masked stores, copy the mask into V0 instead of virtual register.
I missed a few intrinsics in 3dd4aa7d09599507d1f801ffe4bec4c9eebbb8da
when I did this for masked loads and masked segment loads/stores.

Found while trying to share more code between these custom isel
functions.
2021-04-05 21:28:32 -07:00
Philip Reames
a0ffcb69ee Comment adjustments for a rename 2021-04-05 21:07:42 -07:00
Arthur Eubanks
0c2e18141e [SROA] Allow SROA on pointers with invariant group intrinsic uses
When we are able to SROA an alloca, we know all uses of it, meaning we
don't have to preserve the invariant group intrinsics and metadata.

It's possible that we could lose information regarding redundant
loads/stores, but that's unlikely to have any real impact since right
now the only user is Clang and vtables.

Reviewed By: rnk

Differential Revision: https://reviews.llvm.org/D99760
2021-04-05 19:53:40 -07:00
Philip Reames
103039b1aa Exact ashr/lshr don't loose any set bits and are thus trivially invertible
Use that fact to improve isKnownNonEqual.
2021-04-05 19:22:36 -07:00
Philip Reames
7f5ff4ee52 Address minor post commit feedback on 0e59dd 2021-04-05 18:22:17 -07:00
Stanislav Mekhanoshin
87c12ebe40 Copy syncscope when expanding atomicrmw into cmpxchg loop
Fixes: SWDEV-280070

Differential Revision: https://reviews.llvm.org/D99902
2021-04-05 17:29:38 -07:00
Craig Topper
36fcdf34d3 [RISCV] Add more RV32 vslide1up intrinsic test cases. NFC
For some reason we only had 1 test case. This synchronizes the
test with vslide1down so we have the same number of tests for both.
2021-04-05 17:03:52 -07:00
Sanjay Patel
032ed4beee [InstSimplify] fix potential miscompile in select value equivalence
This is the sibling fix to c590a9880d7a -
as there, we can't subsitute a vector value the equality
compare replacement that we are trying requires that the
comparison is true for the entire value. Vector select
can be partly true/false.
2021-04-05 16:52:34 -04:00
Sanjay Patel
630cc8363b [InstSimplify] add test for vector select with operand replacement; NFC
We need a sibling fix to c590a9880d7a
( https://llvm.org/PR49832 ) to avoid miscompiling.
2021-04-05 16:52:34 -04:00
Craig Topper
fdd4f2e31d [RISCV] Add SDTCisInt to the SDTRVVSlide1 since it is only used for vslide1up.vx/vslide1down.vx.
The scalar type is already marked as XLenVT. The floating point
version would need a different rule.
2021-04-05 13:03:39 -07:00
Craig Topper
1a8b6d3c88 [RISCV] Split RISCVISD::VMV_S_XF_VL into separate integer and FP.
It's a bit silly, but it allows us to write stricter type
constraints for isel. There's still some extra type checks in
the generated table due to some type interference limitations
around HWMode.
2021-04-05 12:57:35 -07:00
Philip Reames
5c362c1cd5 Fix copy paste errors in tests from be11bd1e
Several of these weren't testing what was intented.
2021-04-05 12:38:36 -07:00
Philip Reames
25318785e3 Extract a helper for figuring out if an operator is invertible [nfc]
For use in an uncoming patch.  Left out the phi case (which could otherwise fit in this framework) as it would cause infinite recursion in said patch.  We can probably also leverage this in instcombine to ensure we keep the two sets of related analysis and transforms in sync.
2021-04-05 12:14:21 -07:00
Philip Reames
126765f727 [tests] Precommmit tests for reasoning about equality of recurrences 2021-04-05 12:14:05 -07:00
Craig Topper
ad7dfa3912 [RISCV] Move VSLIDE1UP_VX pattern out of a loop that includes FP types.
FP would need VFSLIDE1UP_VF which uses an FP register.
2021-04-05 12:05:54 -07:00
Ricky Taylor
fa9c348cc4 [M68k] Add support for Motorola literal syntax to AsmParser
These look like $00A0cf for hex and  %001010101 for binary. They are used in Motorola assembly syntax.

Differential Revision: https://reviews.llvm.org/D98519
2021-04-05 20:02:29 +01:00
Jennifer Yu
925535c5ef [OPENMP51]Initial support for nocontext clause.
Added basic parsing/sema/serialization support for the 'nocontext' clause.

Differential Revision: https://reviews.llvm.org/D99848
2021-04-05 11:45:49 -07:00
Nico Weber
03c7f6ee36 [gn build] (manually) port 0116d04d04f2 2021-04-05 14:12:58 -04:00
Tom Stellard
c476e3c118 Revert "llvm-shlib: Create object libraries for each component and link against them"
This reverts commit 43ceb74eb1a5801662419fb66a6bf0d5414f1ec5.

This caused some build failures: https://bugs.llvm.org/show_bug.cgi?id=49818
2021-04-05 10:46:19 -07:00
Tom Stellard
c0e85d9efc Revert "Fix build rules for LLVM_WITH_Z3 after D95727"
This reverts commit d66f9c4f1e83e69abf75f97cb5f8fd1dc9422357.

This was a follow up fix for 43ceb74eb1a5801662419fb66a6bf0d5414f1ec5, which
will be reverted.
2021-04-05 10:46:19 -07:00
Cyndy Ishida
eff160f3ab [TextAPI] move source code files out of subdirectory, NFC
TextAPI/ELF has moved out into InterfaceStubs, so theres no longer a
need to seperate out TextAPI between formats.

Reviewed By: ributzka, int3, #lld-macho

Differential Revision: https://reviews.llvm.org/D99811
2021-04-05 10:24:42 -07:00
LLVM GN Syncbot
05484c625c [gn build] Port 9b3df78b4c2a 2021-04-05 17:21:14 +00:00
Ta-Wei Tu
aa38fab0ab [LoopFusion] Bails out if only the second candidate is guarded (PR48060)
If only the second candidate loop is guarded while the first one is not, fusioning
two loops might not be valid but this check is currently missing.

Fixes https://bugs.llvm.org/show_bug.cgi?id=48060

Reviewed By: sidbav

Differential Revision: https://reviews.llvm.org/D99716
2021-04-06 01:08:56 +08:00
Fraser Cormack
c549b5e763 [RISCV] Add support for bitcasts between scalars and fixed-length vectors
This patch supports bitcasts from scalar types to fixed-length vectors
and vice versa. It custom-lowers and custom-legalizes them to
EXTRACT_VECTOR_ELT/INSERT_VECTOR_ELT operations, using a single-element
vectors to hold the scalar where appropriate.

Previously, some of these would fail to select, others would be expanded
through stack loads and stores. Effort was made to ensure the codegen
avoids the stack for both legal and illegal scalar types.

Some of the codegen could be improved, but on first glance it looks like
a general optimization of EXTRACT_VECTOR_ELT when extracting an i64
element on RV32.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D99667
2021-04-05 17:21:55 +01:00
Sanjay Patel
023bb4eb4e [InstCombine] fix potential miscompile in select value equivalence
As shown in the example based on:
https://llvm.org/PR49832
...and the existing test, we can't substitute
a vector value because the equality compare
replacement that we are attempting requires
that the comparison is true for the entire
value. Vector select can be partly true/false.
2021-04-05 12:25:40 -04:00
Sanjay Patel
ec094e0dd0 [InstCombine] add test for miscompile from select value equivalence; NFC
The new test is reduced from:
https://llvm.org/PR49832
...but we already show a potential miscompile in the existing test too.
2021-04-05 12:25:40 -04:00
John Paul Adrian Glaubitz
eb59dc67d9 [M68k] Mark public functions with the LLVM_EXTERNAL_VISIBILITY macro
In 0dbcb3639451, most most target symbols were made hidden by default
with the public ones marked with LLVM_EXTERNAL_VISIBILITY. When the
M68k target was added, this particular change was forgotten so that
external tools cannot make use of the public M68k target functions
in libLLVM.so. Thus, add the missing LLVM_EXTERNAL_VISIBILITY macro
to all public target functions in the M68k backend.

Differential Revision: https://reviews.llvm.org/D99869
2021-04-05 09:24:30 -07:00
Fraser Cormack
e445bcb7b3 [RISCV] Expand scalable-vector truncstores and extloads
Caught in internal testing, these operations are assumed legal by
default, even for scalable vector types. Expand them back into separate
truncations and stores, or loads and extensions.

Also add explicit fixed-length vector tests for these operations, even
though they should have been correct already.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D99654
2021-04-05 17:03:45 +01:00
Alexey Bataev
1e67d9efd7 [SLP]Improve vectorization of the CmpInst instructions.
During vectorization better to postpone the vectorization of the CmpInst
instructions till the end of the basic block. Otherwise we may vectorize
it too early and may miss some vectorization patterns, like reductions.

Reworked part of D57059

Differential Revision: https://reviews.llvm.org/D99796
2021-04-05 06:22:51 -07:00
Paul C. Anagnostopoulos
8c9238aaa1 [TableGen] [docs] Correct a couple of mistakes; use 'true' and 'false' in examples
Differential Revision: https://reviews.llvm.org/D99800
2021-04-05 09:15:58 -04:00
Alex Orlov
dac2590aaa * NFC. Refactored DIPrinter for better support of new print styles.
This patch introduces a DIPrinter interface to implement by different output style printer implementations. DIPrinterGNU and DIPrinterLLVM implement the GNU and LLVM output style printing respectively. No functional changes.

This refactoring clarifies and simplifies the code, and makes a new output style addition easier.

Reviewed By: jhenderson, dblaikie

Differential Revision: https://reviews.llvm.org/D98994
2021-04-05 15:40:41 +04:00
Fraser Cormack
9ae8059434 [RISCV] Add a test showing incorrect codegen
This patch adds a test which shows how the compiler incorrectly sets the
size and alignment of a stack object used to indirectly pass vector
types to functions.

In the particular example, the test passes a <4 x i8> vector type to a
function and creates a stack object of size and alignment equal to 4
bytes. However, the code generated to set up that parameter has been
scalarized and stores each element as individual XLEN-sized values. Thus
on RV32 this stores 16 bytes and on RV64 32 bytes, both of which clobber
the stack. Similarly, the alignment is set up as the alignment
of the vector type, which is not necessarily the natural alignment of XLEN.

Reviewed By: luismarques

Differential Revision: https://reviews.llvm.org/D95025
2021-04-05 11:51:03 +01:00