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Commit Graph

103137 Commits

Author SHA1 Message Date
Rafael Espindola
3f55efbe16 Trivial simplification. No functionality change.
llvm-svn: 207967
2014-05-05 14:18:16 +00:00
Michael Zolotukhin
3a7555adfc Add regression test for r207692.
llvm-svn: 207966
2014-05-05 14:05:25 +00:00
Patrik Hagglund
e8843303a9 Fix gcc -pedantic warning in lto.cpp.
llvm-svn: 207959
2014-05-05 12:24:08 +00:00
Simon Atanasyan
45cc3aaae1 Add range access to ELFFile's sections collection.
llvm-svn: 207952
2014-05-05 06:48:34 +00:00
Saleem Abdulrasool
45ef2e0451 CodeGen: correct memset emittance for WoA
Windows on ARM does not conform to AEABI.  However, memset would be emitted
using the AEABI signature, resulting in inverted parameters.  Handle this
special case appropriately.

llvm-svn: 207943
2014-05-04 23:13:21 +00:00
Saleem Abdulrasool
023a695700 CodeGen: strengthen WoA AEABI avoidance tests
Add additional test cases for WoA AEABI avoidance checking.

llvm-svn: 207942
2014-05-04 23:13:18 +00:00
Saleem Abdulrasool
bca668b81f MC: support FK_SecRel_4 for Windows on ARM
Add handling for FK_SecRel_4 (4-byte section relative relocations).  These are
used by the generation of DWARF debug information (the abbrevations use section
relative relocations).  This will also be used in generation of CodeView line
tables.

llvm-svn: 207941
2014-05-04 23:13:15 +00:00
Benjamin Kramer
8125aa2cd4 LoopUnroll: If we're doing partial unrolling, use the PartialThreshold to limit unrolling.
Otherwise we use the same threshold as for complete unrolling, which is
way too high. This made us unroll any loop smaller than 150 instructions
by 8 times, but only if someone specified -march=core2 or better,
which happens to be the default on darwin.

llvm-svn: 207940
2014-05-04 19:12:38 +00:00
Arnold Schwaighofer
d752a09f8b SLPVectorizer: Bring back the insertelement patch (r205965) with fixes
When can't assume a vectorized tree is rooted in an instruction. The IRBuilder
could have constant folded it. When we rebuild the build_vector (the series of
InsertElement instructions) use the last original InsertElement instruction. The
vectorized tree root is guaranteed to be before it.

Also, we can't assume that the n-th InsertElement inserts the n-th element into
a vector.

This reverts r207746 which reverted the revert of the revert of r205018 or so.

Fixes the test case in PR19621.

llvm-svn: 207939
2014-05-04 17:10:15 +00:00
Elena Demikhovsky
52b1f22e9c AVX-512: minor change in rndscale intrinsic
llvm-svn: 207937
2014-05-04 13:35:37 +00:00
Chandler Carruth
2ccafe8399 [LCG] Add the last (and most complex) of the edge insertion mutation
operations on the call graph. This one forms a cycle, and while not as
complex as removing an internal edge from an SCC, it involves
a reasonable amount of work to find all of the nodes newly connected in
a cycle.

Also somewhat alarming is the worst case complexity here: it might have
to walk roughly the entire SCC inverse DAG to insert a single edge. This
is carefully documented in the API (I hope).

llvm-svn: 207935
2014-05-04 09:38:32 +00:00
Chandler Carruth
20f34b4890 [LCG] Reorder the tests to be a bit more logical: inter-SCC mutation
before intra-SCC mutation, insertion before removal.

No functionality changed.

llvm-svn: 207934
2014-05-04 09:38:23 +00:00
Saleem Abdulrasool
d9cd5486e9 X86: further range-loopify AsmPrinter
Use more range loops in the X86AsmPrinter.  NFC.

llvm-svn: 207928
2014-05-04 01:54:17 +00:00
Saleem Abdulrasool
53f4c01738 X86: remove X86COFFMachineModuleInfo
Remove dead code.  This is vestigial after r98384.

llvm-svn: 207927
2014-05-04 01:54:12 +00:00
Saleem Abdulrasool
edfd1818df X86: repair export compatibility with MinGW/cygwin
Both MinGW and cygwin (i686) construct export directives without the global
leader prefix.  This is mostly due to the fact that they use GNU ld which does
not correctly handle the export directive.  This apparently has been been broken
for a while.  However, this was recently reported as being broken by
mingwandroid and diorcety of the msys2 project.

Remove the global leader prefix if targeting MinGW or cygwin, otherwise, retain
the global leader prefix.  Add an explicit test for cygwin's behaviour of export
directives.

llvm-svn: 207926
2014-05-04 00:03:48 +00:00
Saleem Abdulrasool
f061e56242 X86: refactor export directive generation
Create a helper function to generate the export directive.  This was previously
duplicated inline to handle export directives for variables and functions.  This
also enables the use of range-based iterators for the generation of the
directive rather than the traditional loops.  NFC.

llvm-svn: 207925
2014-05-04 00:03:41 +00:00
David Majnemer
b88715fa63 IR: Cleanup AttributeSet::get for AttrBuilder
We don't modify the AttrBuilder in AttributeSet::get, make the reference
argument const.

llvm-svn: 207924
2014-05-03 23:00:35 +00:00
Juergen Ributzka
b855191ef0 [TBAA] Fix handling of mixed TBAA (path-aware and non-path-aware TBAA).
This fix simply ensures that both metadata nodes are path-aware before
performing path-aware alias analysis.

This issue isn't normally triggered in LLVM, because we perform an autoupgrade
of the TBAA metadata to the new format when reading in LL or BC files. This
issue only appears when a client creates the IR manually and mixes old and new
TBAA metadata format.

This fixes <rdar://problem/16760860>.

llvm-svn: 207923
2014-05-03 22:32:52 +00:00
Rafael Espindola
bb77d317cd Fix pr19645.
The fix itself is fairly simple: move getAccessVariant to MCValue so that we
replace the old weak expression evaluation with the far more general
EvaluateAsRelocatable.

This then requires that EvaluateAsRelocatable stop when it finds a non
trivial reference kind. And that in turn requires the ELF writer to look
harder for weak references.

Last but not least, this found a case where we were being bug by bug
compatible with gas and accepting an invalid input. I reported pr19647
to track it.

llvm-svn: 207920
2014-05-03 19:57:04 +00:00
Joey Gouly
48d50f02a1 [ARM64] Correctly select ANDWri in FastISel.
http://reviews.llvm.org/D3598

llvm-svn: 207917
2014-05-03 17:27:06 +00:00
Benjamin Kramer
fbeb105fa6 SLPVectorizer: Lazily allocate the map for block numbering.
There is no point in creating it if we're not going to vectorize
anything. Creating the map is expensive as it creates large values.
No functionality change.

llvm-svn: 207916
2014-05-03 15:50:37 +00:00
Rafael Espindola
f3c045d9ca Rename member variable to try to fix the bots.
llvm-svn: 207915
2014-05-03 15:28:13 +00:00
Alp Toker
2b9b5f6676 Update docs still mentioning LLVM_ENABLE_CXX11
C++11 is now required.

llvm-svn: 207914
2014-05-03 15:10:04 +00:00
Rafael Espindola
6884239aa9 Move LTOModule and LTOCodeGenerator to the llvm namespace.
llvm-svn: 207911
2014-05-03 14:59:52 +00:00
Rafael Espindola
dc579d7111 Style fix: don't duplicate the method names.
llvm-svn: 207910
2014-05-03 14:46:47 +00:00
Rafael Espindola
c154780200 Style update: don't duplicate comments, they were getting out of sync.
llvm-svn: 207909
2014-05-03 14:34:48 +00:00
Yaron Keren
cfca49d424 Updated Doxygen link for InstIterator.h.
llvm-svn: 207906
2014-05-03 12:06:13 +00:00
Simon Atanasyan
8e7afa2069 [ELFYAML] Group ELF header falgs to target specific blocks. Handle flags
which are corresponding to the current target read from the ELF file.

This fix cannot be tested until obj2yaml does not support ELF format.

llvm-svn: 207905
2014-05-03 11:39:50 +00:00
Simon Atanasyan
390fcb6adf [ELFYAML] Add more SHT_xxx flags to the YAML section type mapping.
llvm-svn: 207904
2014-05-03 11:39:44 +00:00
Yaron Keren
18e58e8a43 InstIterator.h lives in llvm/IR.
llvm-svn: 207903
2014-05-03 11:30:49 +00:00
Karthik Bhat
4591b173c7 Vectorize intrinsic math function calls in SLPVectorizer.
This patch adds support to recognize and vectorize intrinsic math functions in SLPVectorizer.
Review: http://reviews.llvm.org/D3560 and http://reviews.llvm.org/D3559

llvm-svn: 207901
2014-05-03 09:59:54 +00:00
Adam Nemet
00bf90b067 [LSR] Add llc testcase for r207271/r207569.
See PR19608 for the details but to summarize it was easy to modify the .ll
file to get the desired def-use ordering.

llvm-svn: 207887
2014-05-02 23:49:01 +00:00
David Blaikie
5f72874fd2 Try simplifying LexicalScopes ownership again.
Committed initially in r207724-r207726 and reverted due to compiler-rt
crashes in r207732.

Instead, fix this harder with unordered_map and store the LexicalScopes
by value in the map. This did necessitate moving the definition of
LexicalScope above the definition of LexicalScopes.

Let's see how the buildbots/compilers tolerate unordered_map::emplace +
std::piecewise_construct + std::forward_as_tuple...

llvm-svn: 207876
2014-05-02 22:21:05 +00:00
Chandler Carruth
adc216d983 [sanitizers] Propagate the sanitizer options through to the lit context.
This makes it *really* easy to debug leaks FYI:

ASAN_OPTIONS=detect_leaks=1 ./bin/llvm-lit -v <path to test>

llvm-svn: 207874
2014-05-02 21:47:35 +00:00
Benjamin Kramer
bc327c6bd3 Satisfy GCC's urgent need for parentheses around ‘&&’ within ‘||’.
llvm-svn: 207871
2014-05-02 21:28:49 +00:00
Rafael Espindola
80a04ddb6b Aliases are always definitions. Delete dead code.
llvm-svn: 207869
2014-05-02 21:10:48 +00:00
Eric Christopher
b8d435f9a6 Clean up constructor logic and member access for LoopVectorizeHints.
There are public functions that mutate various members as well as
another private member already, so make all the members private to
avoid the discontinuity and add accessors for the values. Should
be no functional change.

llvm-svn: 207868
2014-05-02 20:40:04 +00:00
Justin Bogner
12ebcd3338 llvm-cov: Fix handling of line zero appearing in a line table
Reading line tables in llvm-cov was pretty broken, but would happen to
work as long as no line in the table was 0. It's not clear to me
whether a line of zero *should* show up in these tables, but deciding
to read a string in the middle of the line table is certainly the
wrong thing to do if it does.

I've also added some comments, as trying to figure out what this block
of code was doing was fairly unpleasant.

llvm-svn: 207866
2014-05-02 20:01:24 +00:00
Daniel Sanders
dd6b082c7d [tablegen] !strconcat accepts more than two arguments but this wasn't documented or tested.
Summary:
* Updated the documentation
* Added a test for >2 arguments
* Added a check for the lexical concatenation
* Made the existing test a bit stricter.

Reviewers: t.p.northover

Reviewed By: t.p.northover

Subscribers: t.p.northover, llvm-commits

Differential Revision: http://reviews.llvm.org/D3485

llvm-svn: 207865
2014-05-02 19:25:52 +00:00
Rafael Espindola
0e9ae87185 Remove dead declaration.
llvm-svn: 207857
2014-05-02 18:37:07 +00:00
Nico Weber
fdced47a40 Teach GlobalDCE how to remove empty global_ctor entries.
This moves most of GlobalOpt's constructor optimization
code out of GlobalOpt into Transforms/Utils/CDtorUtils.{h,cpp}. The
public interface is a single function OptimizeGlobalCtorsList() that
takes a predicate returning which constructors to remove.

GlobalOpt calls this with a function that statically evaluates all
constructors, just like it did before. This part of the change is
behavior-preserving.

Also add a call to this from GlobalDCE with a filter that removes global
constructors that contain a "ret" instruction and nothing else – this
fixes PR19590.

llvm-svn: 207856
2014-05-02 18:35:25 +00:00
Akira Hatanaka
f64b00f1d7 [GVN] Pass the phi-translated address of a load instead of the untranslated
address to AnalyzeLoadFromClobberingLoad. This fixes a bug in load-PRE where
PRE is applied to a load that is not partially redundant.

<rdar://problem/16638765>.

llvm-svn: 207853
2014-05-02 17:59:17 +00:00
Saleem Abdulrasool
7a571c0be3 MC: place .file records into the correct section
.file records are supposed to have a section identifier of 65534
(IMAGE_SCN_DEBUG) rather than 0.  This is spelt out clearly within the PE/COFF
specification.  Fix this minor oversight with the implementation for support for
.file records.

llvm-svn: 207851
2014-05-02 17:45:24 +00:00
Tim Northover
4aa1f54c61 DAGCombine: prevent formation of illegal ConstantFP nodes.
llvm-svn: 207850
2014-05-02 17:25:02 +00:00
Benjamin Kramer
b0e4e7faba Add a description for AMD's bdver4 (aka Excavator).
This is just bdver3 + AVX2 + BMI2.

llvm-svn: 207847
2014-05-02 15:47:07 +00:00
Tom Stellard
7831477f20 R600/SI: Add processor type for Mullins.
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
Signed-off-by: Samuel Li <samuel.li@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
llvm-svn: 207846
2014-05-02 15:41:49 +00:00
Tom Stellard
18ca382db4 R600: Expand vector sin and cos.
v2: move code to AMDGPUISelLowering.cpp
    squash with tests (both EG and SI)

Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu>
llvm-svn: 207845
2014-05-02 15:41:47 +00:00
Tom Stellard
05e86018ff R600: Expand TruncStore i64 -> {i16,i8}
llvm-svn: 207844
2014-05-02 15:41:46 +00:00
Tom Stellard
94494bca4d R600/SI: Only create one instruction when spilling/restoring register v3
The register spiller assumes that only one new instruction is created
when spilling and restoring registers, so we need to emit pseudo
instructions for vector register spills and lower them after
register allocation.

v2:
  - Fix calculation of lane index
  - Extend VGPR liveness to end of program.

v3:
  - Use SIMM16 field of S_NOP to specify multiple NOPs.

https://bugs.freedesktop.org/show_bug.cgi?id=75005

llvm-svn: 207843
2014-05-02 15:41:42 +00:00
Tim Northover
ab17e77d87 AArch64/ARM64: add patterns for post-indexed ST1 ops.
llvm-svn: 207840
2014-05-02 14:54:27 +00:00