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Commit Graph

182334 Commits

Author SHA1 Message Date
Tom Stellard
3fff9910e9 Add github-release.py script
Summary:
This script can be used for uploading relases sources and binaries
to github.

Reviewers: hans

Reviewed By: hans

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D64841

llvm-svn: 366977
2019-07-25 01:43:36 +00:00
Chen Zheng
6fb3c7639a [PowerPC] exclude more icmps in LSR which is converted in later hardware loop pass
Differential Revision: https://reviews.llvm.org/D64795

llvm-svn: 366976
2019-07-25 01:22:08 +00:00
Jonas Devlieghere
5b8285a35a [FileCollector] Update unit test to match coding style.
I changed the FileCollector coding style but didn't update the
corresponding unit test.

llvm-svn: 366973
2019-07-25 00:46:58 +00:00
Shoaib Meenai
02aa65e266 [llvm-lipo] Implement alignment function in -create
Summary:
Removes hard coded valuse for alignment in -create.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D64871

llvm-svn: 366970
2019-07-25 00:29:19 +00:00
Shoaib Meenai
77be4dc99b [Object] Add public MaxSectionAlignment to MachOUniversal
Change MAXSECTALIGN to a public MaxSectionAlignment in MachOUniversal.
Will be used in a follow-up.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D65117

llvm-svn: 366969
2019-07-25 00:29:13 +00:00
Shoaib Meenai
82cff4a870 [llvm-lipo] Add test for -verify_archs
Add test to verify clean failure, exit code 1 for valid architecture not
present in the universal binary.

Patch by Anusha Basana <anusha.basana@gmail.com>

Differential Revision: https://reviews.llvm.org/D65251

llvm-svn: 366968
2019-07-25 00:29:07 +00:00
Jonas Devlieghere
e8a86a9c78 [FileCollector] Change coding style from LLDB to LLVM (NFC)
This patch changes the coding style of the FileCollector from the LLDB
to the LLVM coding style. Alex recently lifted it into LLVM and I
volunteered to do the conversion.

llvm-svn: 366966
2019-07-25 00:17:39 +00:00
Francis Visoiu Mistrih
ec43ff8462 [Remarks][NFC] Rename remarks::Parser to remarks::RemarkParser
llvm-svn: 366965
2019-07-25 00:16:56 +00:00
Philip Reames
9d0871d80e [docs] Split out a section on LoopInfo in the new loop documentation
llvm-svn: 366964
2019-07-24 23:46:13 +00:00
Eli Friedman
84750c2af6 [ARM] Remove dead code from ARMConstantIslands.
tLDRHi is not a pc-relative load; it can't directly refer to a
constant pool or jump table.

llvm-svn: 366963
2019-07-24 23:36:14 +00:00
Evandro Menezes
053a6bc197 [InstCombine] Swap order of checks to improve compile time (NFC)
llvm-svn: 366962
2019-07-24 23:31:04 +00:00
Philip Reames
8639011900 Apply a few more reviewer suggestions from D65164
llvm-svn: 366961
2019-07-24 23:30:56 +00:00
Philip Reames
1603cb1137 Define some basic terminology around loops in our documentation
I've noticed a lot of confusion around this area recently with key terms being misused in a number of threads. To help reign that in, let's go ahead and document the current terminology and meaning thereof.

My hope is to grow this over time into a broader discussion of canonical loop forms - yes, there are more than one ... many more than one - but for the moment, simply having the key terminology is a good stopping place.

Note: I am landing this *without* an LGTM.  All feedback so far has been positive, and trying to apply all of the suggested changes/extensions would cause the review to never end.  Instead, I decided to land it with the obvious fixes made based on reviewer comments, then iterate from there.

Differential Revision: https://reviews.llvm.org/D65164

llvm-svn: 366960
2019-07-24 23:24:13 +00:00
Jessica Paquette
6140066b7c [AArch64][GlobalISel] Select immediate modes for ADD when selecting G_GEP
Before, we weren't able to select things like this for G_GEP:

add	x0, x8, #8

And instead we'd materialize the 8.

This teaches GISel to do that. It gives some considerable code size savings
on 252.eon-- about 4%!

Differential Revision: https://reviews.llvm.org/D65248

llvm-svn: 366959
2019-07-24 23:11:01 +00:00
Alex Lorenz
154c8bf18d Fix unittest build issue in r366956
I marked the fields as private, but they're needed by the unittest.
I'll have to fix that up separarely in a follow-up.

llvm-svn: 366958
2019-07-24 23:10:35 +00:00
Amara Emerson
02b3ca4b24 [AArch64][GlobalISel] Don't try to use GISel if subtarget doesn't have neon or fp.
Throughout the legalizerinfo we currently make the assumption that the target
has neon and FP target features available. Fixing it will require a refactor of
the whole thing, so until then make sure we fall back.

Works around PR42734

Differential Revision: https://reviews.llvm.org/D65244

llvm-svn: 366957
2019-07-24 23:00:04 +00:00
Alex Lorenz
cd5b009eb3 [Support] move FileCollector from LLDB to llvm/Support
The file collector class is useful for creating reproducers,
not just for LLDB, but for other tools as well in LLVM/Clang.

Differential Revision: https://reviews.llvm.org/D65237

llvm-svn: 366956
2019-07-24 22:59:20 +00:00
Roman Lebedev
a0525b084a [Codegen] (X & (C l>>/<< Y)) ==/!= 0 --> ((X <</l>> Y) & C) ==/!= 0 fold
Summary:
This was originally reported in D62818.
https://rise4fun.com/Alive/oPH

InstCombine does the opposite fold, in hope that `C l>>/<< Y` expression
will be hoisted out of a loop if `Y` is invariant and `X` is not.
But as it is seen from the diffs here, if it didn't get hoisted,
the produced assembly is almost universally worse.

Much like with my recent "hoist add/sub by/from const" patches,
we should get almost universal win if we hoist constant,
there is almost always an "and/test by imm" instruction,
but "shift of imm" not so much, so we may avoid having to
materialize the immediate, and thus need one less register.
And since we now shift not by constant, but by something else,
the live-range of that something else may reduce.

Special care needs to be applied not to disturb x86 `BT` / hexagon `tstbit`
instruction pattern. And to not get into endless combine loop.

Reviewers: RKSimon, efriedma, t.p.northover, craig.topper, spatel, arsenm

Reviewed By: spatel

Subscribers: hiraditya, MaskRay, wuzish, xbolva00, nikic, nemanjai, jvesely, wdng, nhaehnle, javed.absar, tpr, kristof.beyls, jsji, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D62871

llvm-svn: 366955
2019-07-24 22:57:22 +00:00
Jessica Paquette
8ee06aa75f [AArch64][GlobalISel] Fold G_MUL into XRO load addressing mode when possible
If we have a G_MUL, and either the LHS or the RHS of that mul is the legal
shift value for a load addressing mode, we can fold it into the load.

This gives some code size savings on some SPEC tests. The best are around 2%
on 300.twolf and 3% on 254.gap.

Differential Revision: https://reviews.llvm.org/D65173

llvm-svn: 366954
2019-07-24 22:49:42 +00:00
Peter Collingbourne
633f234017 IR: Teach GlobalIndirectSymbol::getBaseObject() to handle more kinds of expressions.
For aliases, any expression that lowers at the MC level to global_object or
global_object+constant is valid at the object file level. getBaseObject()
should return a result if the aliasee ends up being of that form even if
the IR used to produce it is somewhat unconventional.

Note that this is different from what stripInBoundsOffsets() and that family
of functions is doing. Those functions are concerned about semantic properties
of IR, whereas here we only care about the lowering result.

Therefore reimplement getBaseObject() in a way that matches the lowering
result. This fixes a crash when producing a summary for aliases such as
that in the included test case.

Differential Revision: https://reviews.llvm.org/D65115

llvm-svn: 366952
2019-07-24 22:23:05 +00:00
Amara Emerson
b80667ca96 [GlobalISel] Support for inlining memcpy, memset and memmove calls.
This introduces a new family of combiner helper routines that re-use the
target specific cost model from SelectionDAG, and generate inline implementations
of the memcpy family of intrinsics.

The combines are only enabled at optimization levels higher than -O0, and give
very substantial performance improvements.

Differential Revision: https://reviews.llvm.org/D65167

llvm-svn: 366951
2019-07-24 22:17:31 +00:00
Sanjay Patel
62ec609d2c [Transforms] move copying of load metadata to helper function; NFC
There's another proposed load combine that can make use of this code
in D64432.

llvm-svn: 366949
2019-07-24 22:11:11 +00:00
Evandro Menezes
28cf7a6fce [CodeGen] Add missing comment (NFC)
Add similar comments on the load limits pertaining to `memcmp()` similar to
those for other string functions.

llvm-svn: 366947
2019-07-24 21:45:14 +00:00
Francis Visoiu Mistrih
16abf654fa [Remarks] Add support for serializing metadata for every remark streamer
This allows every serializer format to implement metaSerializer() and
return the corresponding meta serializer.

llvm-svn: 366946
2019-07-24 21:29:44 +00:00
Craig Topper
d36f393266 [InstCombine] Teach foldOrOfICmps to allow icmp eq MIN_INT/MAX to be part of a range comparision. Similar for foldAndOfICmps
We can treat icmp eq X, MIN_UINT as icmp ule X, MIN_UINT and allow
it to merge with icmp ugt X, C. Similar for the other constants.

We can do simliar for icmp ne X, (U)INT_MIN/MAX in foldAndOfICmps. And we already handled UINT_MIN there.

Fixes PR42691.

Differential Revision: https://reviews.llvm.org/D65017

llvm-svn: 366945
2019-07-24 20:57:29 +00:00
Amara Emerson
ee4771011f [AArch64][GlobalISel] Fix a crash during s128 G_ICMP legalization due to r366317.
r366317 added a legalization for s128 G_ICMP narrow scalar which tried to hard
code the result type of the new legalized G_SELECT. Change this to instead use
type of the original G_ICMP result and allow the target to legalize it if necessary
later.

llvm-svn: 366943
2019-07-24 20:46:42 +00:00
David Bolvansky
bb6af70210 Let CorrelatedValuePropagation preserve LazyValueInfo
Summary:
This patch makes CorrelatedValuePropagation preserve LazyValueInfo by adding LazyValueInfo::eraseValue & calling it whenever an instruction is erased.

Passes `make check` , test-suite, and SPECrate 2017.

Patch by aqjune (Juneyoung Lee)

Reviewers: reames, mzolotukhin

Reviewed By: reames

Subscribers: xbolva00, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D59349

llvm-svn: 366942
2019-07-24 20:27:32 +00:00
Francis Visoiu Mistrih
53daa4154e [Remarks][NFC] Rename remarks::Serializer to remarks::RemarkSerializer
llvm-svn: 366939
2019-07-24 19:47:57 +00:00
Stanislav Mekhanoshin
ef9ad9459d [AMDGPU] Increase kernel padding
To support prefetch mode 3 we need to pad current
cacheline and fill 3 cachelines after. Current padding
is only sufficient for mode 2.

Differential Revision: https://reviews.llvm.org/D65236

llvm-svn: 366938
2019-07-24 19:40:13 +00:00
JF Bastien
4d0ba881ae Revert "[yaml2obj] - Allow custom fields for the SHT_UNDEF sections."
It fails on macOS with the following error:
  https://reviews.llvm.org/D65140#1599522

llvm-svn: 366937
2019-07-24 18:29:33 +00:00
Simon Pilgrim
4686b922d2 Fix signed/unsigned comparison warning. NFCI.
llvm-svn: 366935
2019-07-24 17:44:22 +00:00
David Green
e0ad51cc5a [ARM] Rewrite how VCMP are lowered, using a single node
This removes the VCEQ/VCNE/VCGE/VCEQZ/etc nodes, just using two called VCMP and
VCMPZ with an extra operand as the condition code. I believe this will make
some combines simpler, allowing us to just look at these codes and not the
operands. It also helps fill in a missing VCGTUZ MVE selection without adding
extra nodes for it.

Differential Revision: https://reviews.llvm.org/D65072

llvm-svn: 366934
2019-07-24 17:36:47 +00:00
Simon Pilgrim
69d44318a3 [DAGCombine] matchBinOpReduction - add partial reduction matching
This patch adds support for recognizing cases where a larger vector type is being used to reduce just the elements in the lower subvector:

e.g. <8 x i32> reduction pattern in a <16 x i32> vector:

<4,5,6,7,u,u,u,u,u,u,u,u,u,u,u,u>
<2,3,u,u,u,u,u,u,u,u,u,u,u,u,u,u>
<1,u,u,u,u,u,u,u,u,u,u,u,u,u,u,u>

matchBinOpReduction returns the lower extracted subvector in such cases, assuming isExtractSubvectorCheap accepts the extraction.

I've only enabled it for X86 reduction sums so far. I intend to enable it for the bitop/minmax cases in future patches, and eventually I think its worth turning it on all the time. This is mainly just a case of ensuring calls to matchBinOpReduction don't make assumptions on the vector width based on the original vector extraction.

Fixes the x86 partial reduction sum cases in PR33758 and PR42023.

Differential Revision: https://reviews.llvm.org/D65047

llvm-svn: 366933
2019-07-24 17:29:56 +00:00
David Green
eba190e4cc [ARM] Disable MVE fptosi and friends
The prevents us from trying to convert an i1 predicate vector to a float, or
vice-versa. Better patterns are possible, which will follow in a subsequent
commit. For now we just expand them.

Differential Revision: https://reviews.llvm.org/D65066

llvm-svn: 366931
2019-07-24 17:26:26 +00:00
Jessica Paquette
f1fd3e8f57 [AArch64][GlobalISel] Make vector dup optimization look at last elt of ZeroVec
Fix an off-by-one error which made us not look at the last element of the
zero vector. This caused a miscompile in 188.ammp.

Differential Revision: https://reviews.llvm.org/D65168

llvm-svn: 366930
2019-07-24 17:18:51 +00:00
David Green
f34d42dd10 [ARM] More MVE compare vector splat combines for ANDs
Adds some extra r register compare combines, this time for ANDs.

Differential Revision: https://reviews.llvm.org/D65062

llvm-svn: 366928
2019-07-24 17:08:09 +00:00
Nico Weber
2092468e87 gn build: Merge r366919
llvm-svn: 366927
2019-07-24 17:04:44 +00:00
David Bolvansky
48f8b27060 [InstCombine] Adjusted pow-exp tests for Windows [NFC]
Summary: https://bugs.llvm.org/show_bug.cgi?id=42740

Reviewers: efriedma, hans

Reviewed By: hans

Subscribers: spatel, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65220

llvm-svn: 366925
2019-07-24 17:01:20 +00:00
David Green
3f6a7907da [ARM] MVE compare vector splat combine
MVE VCMP instructions can use a general purpose register as the second operand.
This adds the combines for it, selecting from a compare of a vdup.

Differential Revision: https://reviews.llvm.org/D65061

llvm-svn: 366924
2019-07-24 16:58:41 +00:00
Yuanfang Chen
51565ab30b [llvm-objdump] Emit warning if --start-address/--stop-address specify range outside file's address range.
NB: the warning is about the input file itself regardless of the options used
such as `-r`, `-s` etc..

https://bugs.llvm.org/show_bug.cgi?id=41911

Reviewers: jhenderson, grimar, MaskRay, rupprecht

Reviewed by: MaskRay, jhenderson

Differential Revision: https://reviews.llvm.org/D64779

llvm-svn: 366923
2019-07-24 16:55:30 +00:00
Simon Pilgrim
36403c5872 [SelectionDAG] makeEquivalentMemoryOrdering - early out for equal chains (PR42727)
If we are already using the same chain for the old/new memory ops then just return.

Fixes PR42727 which had getLoad() reusing an existing node.

llvm-svn: 366922
2019-07-24 16:53:14 +00:00
Dmitry Preobrazhensky
dcd60909f3 [AMDGPU][MC][GFX10] Enabled GFX10 assembly with arbitrary wavesize assumed by the code
Reviewers: rampitec, arsenm

Differential Revision: https://reviews.llvm.org/D65216

llvm-svn: 366921
2019-07-24 16:50:17 +00:00
David Green
2ff5f4ceeb [ARM] Better OR's for MVE compares
This adds a DeMorgan combine for OR's of compares to turn them into AND's,
helping prevent them from going into and out of gpr registers. It also fills in
the VCLE and VCLT nodes that MVE can select, allowing it to invert more
compares.

Differential Revision: https://reviews.llvm.org/D65059

llvm-svn: 366920
2019-07-24 16:42:09 +00:00
Francis Visoiu Mistrih
728c4d98f3 [Remarks] Simplify the creation of remark serializers
Introduce two new functions to create a serializer, and add support for
more combinations to the YAMLStrTabSerializer.

llvm-svn: 366919
2019-07-24 16:36:35 +00:00
Stanislav Mekhanoshin
6008c52cc8 [AMDGPU] Add all vgpr classes to asm parser
Differential Revision: https://reviews.llvm.org/D65158

llvm-svn: 366917
2019-07-24 16:21:18 +00:00
Matt Arsenault
6516a7b73b AMDGPU: Fix test after r366913
llvm-svn: 366916
2019-07-24 16:05:55 +00:00
Matt Arsenault
793d2dfbd7 AMDGPU/GlobalISel: Don't assume instruction can be erased when selecting exts
The G_ANYEXT handling can end up reaching selectCOPY, which mutates
the instruction in place.

llvm-svn: 366915
2019-07-24 16:05:53 +00:00
Sanjay Patel
3224176e11 [SDAG] convert (sub x, 1) to (add x, -1) in ctpop expansion; NFC
We canonicalize to the add form, so create that directly for efficiency.

llvm-svn: 366914
2019-07-24 15:43:50 +00:00
Matt Arsenault
8cfa304698 AMDGPU: Only allow FP types for format buffer intrinics
The code already somewhat assumes this is the case anyway.

llvm-svn: 366913
2019-07-24 15:37:51 +00:00
David Tenty
7758a7416f [AIX][lit] Don't depend on psutil on AIX
Summary:
On AIX psutil can run into problems with permissions to read the process
tree, which causes problems for python timeout tests which need to kill off
a test and it's children.

This patch adds a workaround by invoking shell via subprocess and using a
platform specific option to ps to list all the descendant processes so we can
kill them. We add some checks so lit can tell whether timeout tests are
supported with out exposing whether we are utilizing the psutil
implementation or the alternative.

Reviewers: hubert.reinterpretcast, andusy, davide, delcypher

Reviewed By: delcypher

Subscribers: davide, delcypher, christof, lldb-commits, libcxx-commits, llvm-commits

Tags: #lldb, #libc, #llvm

Differential Revision: https://reviews.llvm.org/D64251

llvm-svn: 366912
2019-07-24 15:04:27 +00:00