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Commit Graph

62 Commits

Author SHA1 Message Date
Benjamin Kramer
2991126d0d tblgen: remove duplicated newlines.
llvm-svn: 155038
2012-04-18 19:22:47 +00:00
Jim Grosbach
26c6c85855 Move a few more warnings to use PrintWarning().
llvm-svn: 155027
2012-04-18 18:39:31 +00:00
Andrew Trick
6d7aff8241 TableGen's regpressure: emit per-registerclass weight limits.
llvm-svn: 154518
2012-04-11 18:16:28 +00:00
Andrew Trick
2628429e92 TableGen'd regpressure: register unit set pruning.
The pruning is more complete if it is not done incrementally. The code
is also a tad less convluted.

llvm-svn: 154510
2012-04-11 17:35:26 +00:00
Andrew Trick
ccfe0f1fc6 Table-generated register pressure fixes.
Handle mixing allocatable and unallocatable register gracefully.
Simplify the pruning of register unit sets.

llvm-svn: 154474
2012-04-11 03:19:15 +00:00
Andrew Trick
0c60300f39 TableGen/reginfo potential bug: typo from previous checkin.
llvm-svn: 154452
2012-04-10 23:53:32 +00:00
Andrew Trick
360c19ad86 Fix for register pressure tables.
Recent refactoring introduced a bug. Fix: added buildRegUnitSets.

llvm-svn: 154382
2012-04-10 03:36:49 +00:00
Andrew Trick
218abb3a9c Use std::includes instead of my own implementation.
Jakob's review.

llvm-svn: 154377
2012-04-10 03:12:29 +00:00
Andrew Trick
6b7d15e240 Added register unit sets to the target description.
This is a new algorithm that finds sets of register units that can be
used to model registers pressure. This handles arbitrary, overlapping
register classes. Each register class is associated with a (small)
list of pressure sets. These are the dimensions of pressure affected
by the register class's liveness.

llvm-svn: 154374
2012-04-10 02:25:24 +00:00
Andrew Trick
f73fa6bef2 Added register unit weights to the target description.
This is a new algorithm that associates registers with weighted
register units to accuretely model their effect on register
pressure. This handles registers with multiple overlapping
subregisters. It is possible, but almost inconceivable that the
algorithm fails to find an exact solution for a target description. If
an exact solution cannot be found, an inexact, but reasonable solution
will be chosen.

llvm-svn: 154373
2012-04-10 02:25:21 +00:00
Andrew Trick
a1e25f74dd Cleanup set_union usage. The same thing but a bit cleaner now.
llvm-svn: 153922
2012-04-03 01:35:52 +00:00
Andrew Trick
a92546a4bb Use std::set_union instead of nasty custom code.
I just noticed Jakob's examples of the proper application of
std::set... routines.

llvm-svn: 153918
2012-04-03 00:47:23 +00:00
Andrew Trick
e5028d95da comment typo
llvm-svn: 153796
2012-03-31 02:39:17 +00:00
Andrew Trick
f1fa07f326 Introduce Register Units: Give each leaf register a number.
First small step toward modeling multi-register multi-pressure. In the
future, register units can also be used to model liveness and
aliasing.

llvm-svn: 153794
2012-03-31 01:35:59 +00:00
Jakob Stoklund Olesen
3da52049b4 Add more constness to CodeGenRegisters.
llvm-svn: 153667
2012-03-29 18:03:59 +00:00
Jakob Stoklund Olesen
230a0a4b40 Specify SubRegIndex components on the index itself.
It is simpler to define a composite index directly:

  def ssub_2 : SubRegIndex<[dsub_1, ssub_0]>;
  def ssub_3 : SubRegIndex<[dsub_1, ssub_1]>;

Than specifying the composite indices on each register:

  CompositeIndices = [(ssub_2 dsub_1, ssub_0),
                      (ssub_3 dsub_1, ssub_1)] in ...

This also makes it clear that SubRegIndex composition is supposed to be
unique.

llvm-svn: 149556
2012-02-01 23:16:41 +00:00
Jakob Stoklund Olesen
b1190d3876 Fix a bug in the TopoOrderRC comparison function.
The final tie breaker comparison also needs to return +/-1, or 0.
This is not a less() function.

This could cause otherwise identical super-classes to be ordered
unstably, depending on what the system qsort routine does with a bad
compare function.

llvm-svn: 149549
2012-02-01 22:19:26 +00:00
Jakob Stoklund Olesen
6ce052d3b3 Move the composite map into CodeGenSubRegIndex.
Each SubRegIndex keeps track of how it composes.

llvm-svn: 149423
2012-01-31 21:44:11 +00:00
Jakob Stoklund Olesen
6ec7412170 Add a TableGen CodeGenSubRegIndex class.
This class is used to represent SubRegIndex instances instead of the raw
Record pointers that were used before.

No functional change intended.

llvm-svn: 149418
2012-01-31 20:57:55 +00:00
Jakob Stoklund Olesen
e9c53bc69b Add a CoveredBySubRegs property to Register descriptions.
When set, this bit indicates that a register is completely defined by
the value of its sub-registers.

Use the CoveredBySubRegs property to infer which super-registers are
call-preserved given a list of callee-saved registers.  For example, the
ARM registers D8-D15 are callee-saved.  This now automatically implies
that Q4-Q7 are call-preserved.

Conversely, Win64 callees save XMM6-XMM15, but the corresponding
YMM6-YMM15 registers are not call-preserved because they are not fully
defined by their sub-registers.

llvm-svn: 148363
2012-01-18 00:16:39 +00:00
Jakob Stoklund Olesen
c5fac0a05c Add TableGen support for callee saved registers.
Targets can now add CalleeSavedRegs defs to their *CallingConv.td file.
TableGen will use this to create a *_SaveList array suitable for
returning from getCalleeSavedRegs() as well as a *_RegMask bit mask
suitable for returning from getCallPreservedMask().

llvm-svn: 148346
2012-01-17 22:46:58 +00:00
Jakob Stoklund Olesen
c477c8d35e Skip the NAME field when forming tuples.
llvm-svn: 148147
2012-01-13 22:23:50 +00:00
Jakob Stoklund Olesen
9ba097a208 Delete CodeInit and CodeRecTy from TableGen.
The code type was always identical to a string anyway. Now it is simply
a synonym. The code literal syntax [{...}] is still valid.

llvm-svn: 148092
2012-01-13 03:38:34 +00:00
Jakob Stoklund Olesen
0aa2f7755a Emit a getMatchingSuperRegClass() implementation for every target.
Use information computed while inferring new register classes to emit
accurate, table-driven implementations of getMatchingSuperRegClass().

Delete the old manual, error-prone implementations in the targets.

llvm-svn: 146873
2011-12-19 16:53:34 +00:00
Jakob Stoklund Olesen
78291d0bac Synthesize register classes for TRI::getMatchingSuperRegClass().
Teach TableGen to create the missing register classes needed for
getMatchingSuperRegClass() to return maximal results.  The function is
still not auto-generated, so it still returns inexact results.

This produces these new register classes:

ARM:
    QQPR_with_dsub_0_in_DPR_8
    QQQQPR_with_dsub_0_in_DPR_8
X86:
    GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOSP
    GR64_with_sub_16bit_in_GR16_NOREX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_TCW64_and_GR64_with_sub_32bit_in_GR32_NOAX
    GR64_TC_and_GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_NOREX
    GR64_with_sub_32bit_in_GR32_TC
    GR64_with_sub_32bit_in_GR32_ABCD_and_GR32_NOAX
    GR64_with_sub_32bit_in_GR32_NOAX_and_GR32_TC
    GR64_with_sub_32bit_in_GR32_AD
    GR64_with_sub_32bit_in_GR32_AD_and_GR32_NOAX

The other targets in the tree are not weird enough to be affected.

llvm-svn: 146872
2011-12-19 16:53:28 +00:00
Jakob Stoklund Olesen
f51f7724cb Extract a method. No functional change.
llvm-svn: 146713
2011-12-16 00:12:05 +00:00
Jakob Stoklund Olesen
bc821819f3 Use the proper comparator for set_intersection.
llvm-svn: 146674
2011-12-15 19:26:23 +00:00
Jakob Stoklund Olesen
9945c85b52 Synthesize missing register class intersections.
The function TRI::getCommonSubClass(A, B) returns the largest common
sub-class of the register classes A and B.  This patch teaches TableGen
to synthesize sub-classes such that the answer is always maximal.

In other words, every register that is in both A and B will also be
present in getCommonSubClass(A, B).

This introduces these synthetic register classes:

ARM:
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    GPRnopc_and_hGPR
    GPRnopc_and_hGPR
    hGPR_and_rGPR
    tGPR_and_tcGPR
    hGPR_and_tcGPR

X86:
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR64_NOSP_and_GR64_TC
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOSP_and_GR64_TC
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_NOSP
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR32_ABCD_and_GR32_NOAX
    GR32_NOAX_and_GR32_TC
    GR32_NOAX_and_GR32_NOSP
    GR64_NOSP_and_GR64_TC
    GR32_NOAX_and_GR32_NOREX
    GR32_NOAX_and_GR32_NOREX_NOSP
    GR64_NOREX_and_GR64_TC
    GR64_NOREX_NOSP_and_GR64_TC
    GR32_ABCD_and_GR32_NOAX
    GR64_ABCD_and_GR64_TC
    GR32_NOAX_and_GR32_TC
    GR32_AD_and_GR32_NOAX

Other targets are unaffected.

llvm-svn: 146657
2011-12-15 16:48:55 +00:00
Jakob Stoklund Olesen
bc03793434 Extract a method.
llvm-svn: 146374
2011-12-12 16:16:24 +00:00
Jakob Stoklund Olesen
82905dfc94 Add TRI::getSubClassWithSubReg(RC, Idx) function.
This function is used to constrain a register class to a sub-class that
supports the given sub-register index.

For example, getSubClassWithSubReg(GR32, sub_8bit) -> GR32_ABCD.

The function will be used to compute register classes when emitting
INSERT_SUBREG and EXTRACT_SUBREG nodes and for register class inflation
of sub-register operations.

The version provided by TableGen is usually adequate, but targets can
override.

llvm-svn: 141142
2011-10-05 00:35:49 +00:00
Jakob Stoklund Olesen
da923230c8 Properly use const_iterator.
This should unbreak the Windows build.

llvm-svn: 141105
2011-10-04 20:18:39 +00:00
Jakob Stoklund Olesen
703cd60307 Teach TableGen to infer missing register classes.
The set of register classes should be closed under sub-register
operations and intersections. That will allow the register allocator to
model combinations of constraints accurately.

This patch implements the easiest form of register class inference:  For
every register class, and for every sub-register SubIdx, the subset of
registers in RC that have a SubIdx sub-register should also be a register
class.

This does create some new register classes for the targets in the tree:

ARM gets a new QQQQPR_with_ssub_0.  This class was omitted from the .td
file on purpose because it only has two registers.  InstrEmitter and
RegisterCoalescer have safeguards against selecting too small register
classes, so it is harmless.

PowerPC gets a G8RC_with_sub_32 class because LR is not a sub_32
sub-register of LR8.  I think that might be an omission?

X86 puts RIP in the GR64 class, and since that register doesn't have
8-bit sub-registers, we get:

  GR64_with_sub_8bit
  GR64_TC_with_sub_8bit
  GR64_NOREX_with_sub_8bit
  GR64_TC_with_sub_8bit_hi

The various CodeGen classes have already been fixed so adding new
register classes should not affect compile time.

llvm-svn: 141084
2011-10-04 15:28:49 +00:00
Jakob Stoklund Olesen
af50ba10a0 TableGen: Store all allocation orders together.
There is no need to keep the primary order separate.

llvm-svn: 141082
2011-10-04 15:28:44 +00:00
Jakob Stoklund Olesen
c36b745e2e TableGen: Privatize CodeGenRegisterClass::TheDef and Name.
When TableGen starts creating its own register classes, the synthesized
classes won't have a Record reference.  All register classes must have a
name, though.

llvm-svn: 141081
2011-10-04 15:28:08 +00:00
Jakob Stoklund Olesen
1e0d8b4237 TableGen: Don't add synthetic Records to the RecordKeeper.
The RecordKeeper could be shared by multiple target instances, causing
duplicate record errors.

llvm-svn: 141080
2011-10-04 15:27:53 +00:00
Peter Collingbourne
01246536d9 Move TableGen's parser and entry point into a library
This is the first step towards splitting LLVM and Clang's tblgen executables.

llvm-svn: 140951
2011-10-01 16:41:13 +00:00
Jakob Stoklund Olesen
05823401a6 Use precomputed BitVector for CodeGenRegisterClass::hasSubClass().
All the sub-class bit vectors are computed when first creating the
register bank.

llvm-svn: 140905
2011-09-30 23:47:05 +00:00
Jakob Stoklund Olesen
402aa89d8a Compute lists of super-classes in CodeGenRegisterClass.
Use these lists instead of computing them on the fly in
RegisterInfoEmitter.

llvm-svn: 140895
2011-09-30 22:18:45 +00:00
Jakob Stoklund Olesen
82a55057c4 Precompute a bit vector of register sub-classes.
llvm-svn: 140827
2011-09-30 00:10:40 +00:00
Jakob Stoklund Olesen
35c649f61b Order register classes topologically.
All register classes are given a lower ID than their sub-classes.
Cliques are ordered alphabetically.

This will be used to simplify some sub-class operations.

llvm-svn: 140826
2011-09-30 00:10:36 +00:00
Jakob Stoklund Olesen
d7b6708541 Switch to ArrayRef<CodeGenRegisterClass*>.
This makes it possible to allocate CodeGenRegisterClass instances
dynamically and reorder them.

llvm-svn: 140816
2011-09-29 22:28:37 +00:00
David Greene
43a26c71e8 Unconstify Inits
Remove const qualifiers from Init references, per Chris' request.

llvm-svn: 136531
2011-07-29 22:43:06 +00:00
David Greene
88abfb940e [AVX] Create Inits Via Factory Method
Replace uses of new *Init with *Init::get.  This hides the allocation
implementation so that we can unique Inits in various ways.

llvm-svn: 136486
2011-07-29 19:07:07 +00:00
David Greene
b149019c5d [AVX] Constify Inits
Make references to Inits const everywhere.  This is the final step
before making them unique.

llvm-svn: 136485
2011-07-29 19:07:05 +00:00
Jakob Stoklund Olesen
c5fe14efd2 Intern all RecTy subclass instances to avoid duplicates.
Make all of the RecTy constructors private, and use get() factory
methods instead. Return singleton instances when it makes sense.

ListTy instance pointers are stored in the element RecTy instance.

BitsRecTy instance pointers, one per length, are stored in a static vector.

Also unique DefInit instances. A Record has a unique DefInit which
has a unique RecordRecTy instance.

This saves some 200k-300k RecTy allocations when parsing ARM.td. It
reduces TableGen's heap usage by almost 50%.

llvm-svn: 135399
2011-07-18 17:02:57 +00:00
Eric Christopher
3dd1f02420 Revert r134921, 134917, 134908 and 134907. They're causing failures
in multiple buildbots.

llvm-svn: 134936
2011-07-11 23:06:52 +00:00
David Greene
e224004004 Use get(0 Instead of Create()
Respond to some feedback asking for a name change.

llvm-svn: 134921
2011-07-11 20:55:22 +00:00
David Greene
096bf5c02b [AVX] Make Inits Foldable
Manage Inits in a FoldingSet.  This provides several benefits:

- Memory for Inits is properly managed

- Duplicate Inits are folded into Flyweights, saving memory

- It enforces const-correctness, protecting against certain classes
  of bugs

The above benefits allow Inits to be used in more contexts, which in
turn provides more dynamism to TableGen.  This enhanced capability
will be used by the AVX code generator to a fold common patterns
together.

llvm-svn: 134907
2011-07-11 18:25:51 +00:00
Jim Grosbach
cfcba2d22b Consolidate some TableGen diagnostic helper functions.
TableGen had diagnostic printers sprinkled about in a few places. Pull them
together into a single location in Error.cpp.

llvm-svn: 133568
2011-06-21 22:55:50 +00:00
Jakob Stoklund Olesen
22d12568aa Skip fields that don't exist in the Register class.
llvm-svn: 133470
2011-06-20 20:56:05 +00:00