1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-24 19:52:54 +01:00
Commit Graph

18496 Commits

Author SHA1 Message Date
Jyotsna Verma
e27b88fb08 reverting patch 176508.
llvm-svn: 176513
2013-03-05 20:29:23 +00:00
Jyotsna Verma
ef3cf2b345 Hexagon: Add support for lowering block address.
llvm-svn: 176508
2013-03-05 19:37:46 +00:00
Jyotsna Verma
baf7212bfe Hexagon: Expand addc, adde, subc and sube.
llvm-svn: 176505
2013-03-05 19:04:47 +00:00
Eli Bendersky
051faf7c26 Fixes a test by replacing .align by .p2align and setting triples explicitly.
Patch by David Sehr

llvm-svn: 176502
2013-03-05 18:56:14 +00:00
Jyotsna Verma
c096fbaa7d Hexagon: Add encoding bits to the TFR64 instructions.
Set imMoveImm, isAsCheapAsAMove flags for TFRI instructions.

llvm-svn: 176499
2013-03-05 18:42:28 +00:00
David Sehr
5f7e2bf434 Add a test that .align directives on capable processors use long NOPs.
llvm-svn: 176490
2013-03-05 16:46:54 +00:00
Vincent Lejeune
9ca3635aac R600: Turn BUILD_VECTOR into Reg_Sequence
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176487
2013-03-05 15:04:49 +00:00
Vincent Lejeune
d0d37f790e R600: Use MUL_IEEE for trig/fdiv intrinsic
Reviewed-by: Tom Stellard <thomas.stellard at amd.com>
llvm-svn: 176485
2013-03-05 15:04:37 +00:00
NAKAMURA Takumi
7ab1b62c2b llvm/test/CodeGen/Mips/mips64-f128.ll: Add explicit -mtriple=mips64el-unknown-unknown to appease win32.
FIXME: Is it expected for win32 to affect mips targets?
llvm-svn: 176471
2013-03-05 02:18:59 +00:00
NAKAMURA Takumi
7c27fc3cf0 llvm/test/CodeGen/Thumb/iabs.ll: Add explicit -mtriple=thumb-unknown-unknown to appease win32 hosts.
llvm-svn: 176470
2013-03-05 02:18:52 +00:00
David Sehr
e37f7ab590 The current X86 NOP padding uses one long NOP followed by the remainder in
one-byte NOPs.  If the processor actually executes those NOPs, as it sometimes
does with aligned bundling, this can have a performance impact.  From my
micro-benchmarks run on my one machine, a 15-byte NOP followed by twelve
one-byte NOPs is about 20% worse than a 15 followed by a 12.  This patch
changes NOP emission to emit as many 15-byte (the maximum) as possible followed
by at most one shorter NOP.

llvm-svn: 176464
2013-03-05 00:02:23 +00:00
Lang Hames
ba8dee024f Check isDiscardableIfUnused, rather than hasLocalLinkage, when bumping
GlobalValue linkage up to ExternalLinkage in the ExtractGV pass. This
prevents linkonce and linkonce_odr symbols from being DCE'd.

llvm-svn: 176459
2013-03-04 22:40:44 +00:00
Akira Hatanaka
8d412f5a8a [mips] Print move instructions.
"move $4, $5" is printed instead of "or $4, $5, $zero".

llvm-svn: 176455
2013-03-04 22:25:01 +00:00
Jack Carter
44abaa390d Mips specific inline assembler constraint 'R'
'R' An address that can be sued in a non-macro load or store.
This patch includes a positive test case.

llvm-svn: 176452
2013-03-04 21:33:15 +00:00
Eli Bendersky
f241522533 Reapply r176381, writing the CHECKs in a more forgiving manner to account for
running llvm-objdump on Darwin.

llvm-svn: 176443
2013-03-04 18:20:31 +00:00
Preston Gurd
66b9c4fcf9 Bypass Slow Divides
* Only apply divide bypass optimization when not optimizing for size. 
* Fixed bug caused by constant for 0 value of type Int32,
  used dividend type to generate the constant instead.
* For atom x86-64 apply the divide bypass to use 16-bit divides instead of
  64-bit divides when operand values are small enough.
* Added lit tests for 64-bit divide bypass.

Patch by Tyler Nowicki!

llvm-svn: 176442
2013-03-04 18:13:57 +00:00
Jim Grosbach
2b831fb8d3 ARM: Creating a vector from a lane of another.
The VDUP instruction source register doesn't allow a non-constant lane
index, so make sure we don't construct a ARM::VDUPLANE node asking it to
do so.

rdar://13328063
http://llvm.org/bugs/show_bug.cgi?id=13963

llvm-svn: 176413
2013-03-02 20:16:24 +00:00
Arnold Schwaighofer
c633bf302e ARM NEON: Fix v2f32 float intrinsics
Mark them as expand, they are not legal as our backend does not match them.

llvm-svn: 176410
2013-03-02 19:38:33 +00:00
Nuno Lopes
fc752c7658 recommit r172363 & r171325 (reverted in r172756)
This adds minimalistic support for PHI nodes to llvm.objectsize() evaluation

fingers crossed so that it does break clang boostrap again..

llvm-svn: 176408
2013-03-02 11:36:24 +00:00
Arnold Schwaighofer
e60e6fc70f X86 cost model: Adjust cost for custom lowered vector multiplies
This matters for example in following matrix multiply:

int **mmult(int rows, int cols, int **m1, int **m2, int **m3) {
  int i, j, k, val;
  for (i=0; i<rows; i++) {
    for (j=0; j<cols; j++) {
      val = 0;
      for (k=0; k<cols; k++) {
        val += m1[i][k] * m2[k][j];
      }
      m3[i][j] = val;
    }
  }
  return(m3);
}

Taken from the test-suite benchmark Shootout.

We estimate the cost of the multiply to be 2 while we generate 9 instructions
for it and end up being quite a bit slower than the scalar version (48% on my
machine).

Also, properly differentiate between avx1 and avx2. On avx-1 we still split the
vector into 2 128bits and handle the subvector muls like above with 9
instructions.
Only on avx-2 will we have a cost of 9 for v4i64.

I changed the test case in test/Transforms/LoopVectorize/X86/avx1.ll to use an
add instead of a mul because with a mul we now no longer vectorize. I did
verify that the mul would be indeed more expensive when vectorized with 3
kernels:

for (i ...)
   r += a[i] * 3;
for (i ...)
  m1[i] = m1[i] * 3; // This matches the test case in avx1.ll
and a matrix multiply.

In each case the vectorized version was considerably slower.

radar://13304919

llvm-svn: 176403
2013-03-02 04:02:52 +00:00
Nadav Rotem
6d803820f8 PR14448 - prevent the loop vectorizer from vectorizing the same loop twice.
The LoopVectorizer often runs multiple times on the same function due to inlining.
When this happens the loop vectorizer often vectorizes the same loops multiple times, increasing code size and adding unneeded branches.
With this patch, the vectorizer during vectorization puts metadata on scalar loops and marks them as 'already vectorized' so that it knows to ignore them when it sees them a second time.

PR14448.

llvm-svn: 176399
2013-03-02 01:33:49 +00:00
Michael Gottesman
a4c89f27cc Revert "Rewrite a test to count emitted instructions without using -stats"
This reverts commit aac7922b8fe7ae733d3fe6697e6789fd730315dc. I am reverting the
commit since it broke the phase 1 public buildbot for a few hours.

http://lab.llvm.org:8013/builders/clang-x86_64-darwin11-nobootstrap-RA/builds/2137

llvm-svn: 176394
2013-03-02 00:53:20 +00:00
Akira Hatanaka
d2f7ed089c [mips] Fix inefficient code generation.
This patch eliminates the need to emit a constant move instruction when this
pattern is matched:

(select (setgt a, Constant), T, F)

The pattern above effectively turns into this:

(conditional-move (setlt a, Constant + 1), F, T)

llvm-svn: 176384
2013-03-01 21:52:08 +00:00
Eli Bendersky
f364fecbb8 Rewrite a test to count emitted instructions without using -stats
Also removed the comments of "should produce..." because they completely
don't match the actually produced output.

llvm-svn: 176381
2013-03-01 21:34:37 +00:00
Akira Hatanaka
e2ccd1b4d6 Set properties for f128 type.
llvm-svn: 176378
2013-03-01 21:11:44 +00:00
Eli Bendersky
b43cf3bd32 Rewrite a test to check actual output rather than intermediate implementation
detail.

The was this test was written, it was relying on an implementation detail
(fixups) and hence was very brittle (relying, among other things, on the
exact ordering of statistics printed by MC).

The test was rewritten to check a more observable output difference. While it
doesn't cover 100% of the things the original test covered, it's a good
practice to write regression tests this way. If we want to check that
internal details and invariants hold, such tests should be expressed as unit
tests.

llvm-svn: 176377
2013-03-01 20:54:00 +00:00
Edwin Vane
d84583a773 No need to force-create clang-tools-extra lit.site.cfg
The make (all) target takes care of creating lit configs and auto-generating
tests. The problem with the original 'lit.site.cfg' target is it's not
recursive and doesn't fully create everything necessary for testing
clang-tools-extra.

llvm-svn: 176374
2013-03-01 19:58:58 +00:00
Michael Liao
fde72e5106 Add regression tests (WORKSFORME)
- These tests wont't crash on trunk but would be better to add them so that
  they don't break again in the future.

llvm-svn: 176369
2013-03-01 19:23:37 +00:00
Chad Rosier
25ffc43c38 Generate an error message instead of asserting or segfaulting when we can't
handle indirect register inputs.
rdar://13322011

llvm-svn: 176367
2013-03-01 19:12:05 +00:00
Benjamin Kramer
a462070739 LoopVectorize: Don't hang forever if a PHI only has skipped PHI uses.
Fixes PR15384.

llvm-svn: 176366
2013-03-01 19:07:31 +00:00
Michael Liao
1e621fbd2f Fix PR10475
- ISD::SHL/SRL/SRA must have either both scalar or both vector operands
  but TLI.getShiftAmountTy() so far only return scalar type. As a
  result, backend logic assuming that breaks.
- Rename the original TLI.getShiftAmountTy() to
  TLI.getScalarShiftAmountTy() and re-define TLI.getShiftAmountTy() to
  return target-specificed scalar type or the same vector type as the
  1st operand.
- Fix most TICG logic assuming TLI.getShiftAmountTy() a simple scalar
  type.

llvm-svn: 176364
2013-03-01 18:40:30 +00:00
Chad Rosier
313ffa4bc0 Add support for using non-pic code for arm and thumb1 when emitting the sjlj
dispatch code.  As far as I can tell the thumb2 code is behaving as expected.
I was able to compile and run the associated test case for both arm and thumb1.
rdar://13066352

llvm-svn: 176363
2013-03-01 18:30:38 +00:00
Christian Konig
1a86119413 R600/SI: fix sampler tests after fixing wait insertions
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
llvm-svn: 176359
2013-03-01 17:39:05 +00:00
Jyotsna Verma
359daa8ad9 Hexagon: Add constant extender support framework.
llvm-svn: 176358
2013-03-01 17:37:13 +00:00
Akira Hatanaka
04b651d332 [mips] Remove unused option. Fix 80-column violations.
llvm-svn: 176330
2013-03-01 02:17:02 +00:00
Akira Hatanaka
9449ff1c6e [mips] Add the capability to search delay slot filling instructions in
successor basic blocks.

Currently this is off by default.

llvm-svn: 176329
2013-03-01 02:03:51 +00:00
Akira Hatanaka
01c253f718 [mips] Add capability to search in the forward direction for instructions that
can fill the delay slot.

Currently, this is off by default.

llvm-svn: 176320
2013-03-01 00:50:52 +00:00
Akira Hatanaka
581402232c [mips] Define class MemDefsUses.
This class tracks dependence between memory instructions using underlying
objects of memory operands. 

llvm-svn: 176313
2013-03-01 00:16:31 +00:00
Quentin Colombet
5b2d4c19c9 Fix a bug in instcombine for fmul in fast math mode.
The instcombine recognized pattern looks like:
a = b * c
d = a +/- Cst
or
a = b * c
d = Cst +/- a

When creating the new operands for fadd or fsub instruction following the related fmul, the first operand was created with the second original operand (M0 was created with C1) and the second with the first (M1 with Opnd0).

The fix consists in creating the new operands with the appropriate original operand, i.e., M0 with Opnd0 and M1 with C1.

llvm-svn: 176300
2013-02-28 21:12:40 +00:00
Benjamin Kramer
df474e5dfa Cost model support for lowered math builtins.
We make the cost for calling libm functions extremely high as emitting the
calls is expensive and causes spills (on x86) so performance suffers. We still
vectorize important calls like ceilf and friends on SSE4.1. and fabs.

Differential Revision: http://llvm-reviews.chandlerc.com/D466

llvm-svn: 176287
2013-02-28 19:09:33 +00:00
Tim Northover
e7cedcf871 AArch64: remove post-encoder method from FCMP (immediate) instructions.
The work done by the post-encoder (setting architecturally unused bits to 0 as
required) can be done by the existing operand that covers the "#0.0". This
removes at least one use of the discouraged PostEncoderMethod uses.

llvm-svn: 176261
2013-02-28 14:46:14 +00:00
Tim Northover
779708f861 AArch64: be more careful resorting to inefficient addressing for weak vars.
If an otherwise weak var is actually defined in this unit, it can't be
undefined at runtime so we can use normal global variable sequences (ADRP/ADD)
to access it.

llvm-svn: 176259
2013-02-28 14:36:31 +00:00
Tim Northover
b24657b0c5 AArch64: don't drop GlobalAddress offset when handling extern_weak decls.
llvm-svn: 176258
2013-02-28 14:36:24 +00:00
Tim Northover
e2cf283c3e AArch64: Use cbnz instead of cmp/b.ne pair for atomic operations.
llvm-svn: 176253
2013-02-28 13:52:07 +00:00
Evgeniy Stepanov
caac73e5ea [msan] Implement sanitize_memory attribute.
Shadow checks are disabled and memory loads always produce fully initialized
values in functions that don't have a sanitize_memory attribute. Value and
argument shadow is propagated as usual.

This change also updates blacklist behaviour to match the above.

llvm-svn: 176247
2013-02-28 11:25:14 +00:00
Renato Golin
86c3e15702 Corrections for XFAIL armv5 tests
Most of the tests that behave differently on llvm-arm-linux buildbot
did so becase the triple wasn't set correctly to armv5, so we can
revert most of the special behaviour added previously. Some tests
still need the special treatment, though.

llvm-svn: 176243
2013-02-28 10:05:10 +00:00
Manman Ren
000b54a794 Debug Info: for static member variables, always put AT_MIPS_linkage_name to the
definition DIE (TAG_variable), and put AT_MIPS_linkage_name to TAG_member when
DarwinGDBCompat is true.

Darwin GDB needs AT_MIPS_linkage_name at both places to work.

Follow-up patch to r176143.
rdar://problem/13291234

llvm-svn: 176220
2013-02-27 23:21:02 +00:00
Jim Grosbach
4d945565f7 ARM: FMA is legal only if VFP4 is available.
rdar://13306723

llvm-svn: 176212
2013-02-27 21:31:12 +00:00
Tim Northover
281992500a ARM: permit full range of valid ADR immediates.
This fixes an issue where trying to assemlbe valid ADR instructions would cause
LLVM to hit a failed assertion.

Patch by Keith Walker.

llvm-svn: 176189
2013-02-27 16:43:09 +00:00
Benjamin Kramer
33d5dd0b08 LoopVectorize: Vectorize math builtin calls.
This properly asks TargetLibraryInfo if a call is available and if it is, it
can be translated into the corresponding LLVM builtin. We don't vectorize sqrt()
yet because I'm not sure about the semantics for negative numbers. The other
intrinsic should be exact equivalents to the libm functions.

Differential Revision: http://llvm-reviews.chandlerc.com/D465

llvm-svn: 176188
2013-02-27 15:24:19 +00:00