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Commit Graph

115 Commits

Author SHA1 Message Date
Dale Johannesen
44c0a5d545 repair x86 performance, dejagnu problems from previous change
llvm-svn: 35245
2007-03-21 21:51:52 +00:00
Dale Johannesen
3e422e3b49 do not share old induction variables when this would result in invalid
instructions (that would have to be split later)

llvm-svn: 35227
2007-03-20 21:54:54 +00:00
Evan Cheng
ce8b779c6c Added isLegalAddressExpression hook to test if the given expression can be
folded into target addressing mode for the given type.

llvm-svn: 35121
2007-03-16 08:42:32 +00:00
Evan Cheng
f132fa5bba More flexible TargetLowering LSR hooks for testing whether an immediate is
a legal target address immediate or scale.

llvm-svn: 35071
2007-03-12 23:26:27 +00:00
Anton Korobeynikov
85d6c1ebad Refactoring of formal parameter flags. Enable properly use of
zext/sext/aext stuff.

llvm-svn: 35008
2007-03-07 16:25:09 +00:00
Jim Laskey
655bea55fe Simplify lowering and selection of exception ops.
llvm-svn: 34491
2007-02-22 15:37:19 +00:00
Reid Spencer
e7ff3305d6 For PR1195:
Change use of "packed" term to "vector" in comments, strings, variable
names, etc.

llvm-svn: 34300
2007-02-15 03:39:18 +00:00
Reid Spencer
55e4e98a2a For PR1195:
Rename PackedType -> VectorType, ConstantPacked -> ConstantVector, and
PackedTyID -> VectorTyID. No functional changes.

llvm-svn: 34293
2007-02-15 02:26:10 +00:00
Evan Cheng
1b155ac243 Move SimplifySetCC to TargetLowering and allow it to be shared with legalizer.
llvm-svn: 34065
2007-02-08 22:13:59 +00:00
Anton Korobeynikov
c469cbc2e7 Fixed uninitialized stuff inside LegalizeDAG. Fortunately, the only
affected part is codegen of "memove" inside x86 backend. This fixes
PR1144

llvm-svn: 33752
2007-02-01 08:39:52 +00:00
Evan Cheng
3ec2e08a37 Allow the target to override the ISD::CondCode that's to be used to test the
result of the comparison libcall against zero.

llvm-svn: 33701
2007-01-31 09:29:11 +00:00
Nate Begeman
dc46021355 Finish off bug 680, allowing targets to custom lower frame and return
address nodes.

llvm-svn: 33636
2007-01-29 22:58:52 +00:00
Anton Korobeynikov
611d5e2eda Propagate changes from my local tree. This patch includes:
1. New parameter attribute called 'inreg'. It has meaning "place this
parameter in registers, if possible". This is some generalization of
gcc's regparm(n) attribute. It's currently used only in X86-32 backend.
2. Completely rewritten CC handling/lowering code inside X86 backend.
Merged stdcall + c CCs and fastcall + fast CC.
3. Dropped CSRET CC. We cannot add struct return variant for each
target-specific CC (e.g. stdcall + csretcc and so on).
4. Instead of CSRET CC introduced 'sret' parameter attribute. Setting in
on first attribute has meaning 'This is hidden pointer to structure
return. Handle it gently'.
5. Fixed small bug in llvm-extract + add new feature to
FunctionExtraction pass, which relinks all internal-linkaged callees
from deleted function to external linkage. This will allow further
linking everything together.

NOTEs: 1. Documentation will be updated soon.
       2. llvm-upgrade should be improved to translate csret => sret.
          Before this, there will be some unexpected test fails.
llvm-svn: 33597
2007-01-28 13:31:35 +00:00
Reid Spencer
4fe8454735 Don't #include DerivedTypes.h in this header. Make adjustments to
compensate. Move a function out of line to TargetLowering.cpp

llvm-svn: 33153
2007-01-12 23:21:42 +00:00
Evan Cheng
a8ed507f15 - Move RTLIB::Libcall enum to a separate file.
- Code clean up.

llvm-svn: 33148
2007-01-12 22:49:32 +00:00
Evan Cheng
3e3e3865b8 Silence a bogus compiler warning.
llvm-svn: 33145
2007-01-12 22:30:07 +00:00
Reid Spencer
373d2bccea For PR1064:
Implement the arbitrary bit-width integer feature. The feature allows
integers of any bitwidth (up to 64) to be defined instead of just 1, 8,
16, 32, and 64 bit integers.

This change does several things:
1. Introduces a new Derived Type, IntegerType, to represent the number of
   bits in an integer. The Type classes SubclassData field is used to
   store the number of bits. This allows 2^23 bits in an integer type.
2. Removes the five integer Type::TypeID values for the 1, 8, 16, 32 and
   64-bit integers. These are replaced with just IntegerType which is not
   a primitive any more.
3. Adjust the rest of LLVM to account for this change.

Note that while this incremental change lays the foundation for arbitrary
bit-width integers, LLVM has not yet been converted to actually deal with
them in any significant way. Most optimization passes, for example, will
still only deal with the byte-width integer types.  Future increments
will rectify this situation.

llvm-svn: 33113
2007-01-12 07:05:14 +00:00
Evan Cheng
032a597692 Store default libgcc routine names and allow them to be redefined by target.
llvm-svn: 33105
2007-01-12 02:11:51 +00:00
Reid Spencer
f3265181e2 Rename BoolTy as Int1Ty. Patch by Sheng Zhou.
llvm-svn: 33076
2007-01-11 18:21:29 +00:00
Evan Cheng
38cb858ee5 - Remove isSetCCExpensive() etc. These are no longer used.
- Add isSelectExpensive() etc. It's used to tell codegen that select is expensive for a given target, avoid using it if possible. Currently it's only
used to expand FCOPYSIGN.

llvm-svn: 32939
2007-01-05 23:31:08 +00:00
Reid Spencer
a7eaf62ace For PR950:
Change integer type names for signless integer types

llvm-svn: 32777
2006-12-31 05:23:18 +00:00
Evan Cheng
7684d815d1 Add getTypeToExpandTo() which recursively walks TransformToType to determine
the intrinsic type to expand to.

llvm-svn: 32558
2006-12-13 20:52:00 +00:00
Evan Cheng
2346bdd8c3 Update comments.
llvm-svn: 32532
2006-12-13 06:12:35 +00:00
Evan Cheng
5c6304ca6e Update comments.
llvm-svn: 32531
2006-12-13 06:09:03 +00:00
Anton Korobeynikov
e76b69846d Cleaned setjmp/longjmp lowering interfaces. Now we're producing right
code (both asm & cbe) for Mingw32 target.
Removed autoconf checks for underscored versions of setjmp/longjmp.

llvm-svn: 32415
2006-12-10 23:12:42 +00:00
Evan Cheng
c050bb298f Add a mechanism to specify whether a target supports a particular indexed load / store.
llvm-svn: 31597
2006-11-09 18:56:43 +00:00
Evan Cheng
89ee587963 Rename ISD::MemOpAddrMode to ISD::MemIndexedMode
llvm-svn: 31595
2006-11-09 17:55:04 +00:00
Evan Cheng
6b7d127df9 getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT.
llvm-svn: 31584
2006-11-09 04:29:46 +00:00
Evan Cheng
db0add3bcb Added target hook for post-indexed memory ops transformation.
llvm-svn: 31499
2006-11-07 09:04:16 +00:00
Evan Cheng
466e20fca2 Rename
llvm-svn: 31413
2006-11-03 07:21:16 +00:00
Evan Cheng
9ebbced355 Added a target specific hook to check whether / how a node can be transformed
into a pair of base / offset nodes for pre-indexed load / store ops.

llvm-svn: 31407
2006-11-03 03:04:06 +00:00
Chris Lattner
4cb79a5f9d generalize this api
llvm-svn: 31365
2006-11-02 01:39:10 +00:00
Chris Lattner
d9afd310a6 Change the prototype for TargetLowering::isOperandValidForConstraint
llvm-svn: 31318
2006-10-31 19:40:43 +00:00
Evan Cheng
fe5bb5dbe6 Merge ISD::TRUNCSTORE to ISD::STORE. Switch to using StoreSDNode.
llvm-svn: 30945
2006-10-13 21:14:26 +00:00
Evan Cheng
967d6af1d2 Merging ISD::LOAD and ISD::LOADX. Added LoadSDNode to represent load nodes.
Chain and address ptr remains as operands. SrcValue, extending mode, extending
VT (or rather loaded VT before extension) are now instance variables of
LoadSDNode.

Introduce load / store addressing modes to represent pre- and post-indexed
load and store. Also added an additional operand offset that is only used in
post-indexed mode (i.e. base ptr += offset after load/store).

Added alignment info (not yet used) and isVolatile fields.

llvm-svn: 30843
2006-10-09 20:55:20 +00:00
Chris Lattner
77545e4a28 Add support for targets to declare that they use a GOT
llvm-svn: 30777
2006-10-06 22:46:34 +00:00
Evan Cheng
494e8e6971 Combine ISD::EXTLOAD, ISD::SEXTLOAD, ISD::ZEXTLOAD into ISD::LOADX. Add an
extra operand to LOADX to specify the exact value extension type.

llvm-svn: 30714
2006-10-04 00:56:09 +00:00
Duraid Madina
51396ffd3e add setJumpBufSize() and setJumpBufAlignment() to target-lowering.
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
2006-09-04 06:21:35 +00:00
Andrew Lenharth
a2bda5b0e1 Start on my todo list
llvm-svn: 28752
2006-06-12 16:07:18 +00:00
Reid Spencer
574d4e6992 For PR786:
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.

llvm-svn: 28453
2006-05-24 19:21:13 +00:00
Evan Cheng
89f7ea0382 Another typo. Pointed out by Nate Begeman.
llvm-svn: 28353
2006-05-17 18:22:14 +00:00
Evan Cheng
09c4a5d032 Fix a mis-leading comment.
llvm-svn: 28350
2006-05-17 18:08:20 +00:00
Chris Lattner
3e13a7d49e There is now a default impl of this method
llvm-svn: 28336
2006-05-16 22:52:11 +00:00
Andrew Lenharth
14504c85ed Move this code to a common place
llvm-svn: 28329
2006-05-16 17:42:15 +00:00
Chris Lattner
06d617846d Add some new methods for computing sign bit information.
llvm-svn: 28144
2006-05-06 09:26:22 +00:00
Owen Anderson
71bc529dfa Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.

llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Evan Cheng
ec4d1668ef Added a virtual method isVectorClearMaskLegal to TLI. It is similar to
isShuffleMaskLegal, used to determine if it makes sense to turn a
"vector clear" (e.g. pand V, <0, -1, 0, -1> to a shuffle of the vector and
a zero vector.

llvm-svn: 27873
2006-04-20 08:54:13 +00:00
Chris Lattner
048bc55352 Provide a default impl of LowerArguments
llvm-svn: 27605
2006-04-12 16:21:12 +00:00
Chris Lattner
1dc3c03ee7 Move isShuffleLegal from TLI to Legalize.
llvm-svn: 27398
2006-04-04 17:21:22 +00:00
Chris Lattner
9925c6018f Allow targets to have fine grained control over which types various ops get
promoted to, if they desire.

llvm-svn: 27389
2006-04-04 00:25:10 +00:00