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46e4658c95
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166 Commits

Author SHA1 Message Date
Chris Lattner
46e4658c95 eliminate a copy of the machineoperand printing stuff. Keep the copy that 
knows how to print offsets.

llvm-svn: 45457
 2007-12-30 21:03:30 +00:00
Chris Lattner
ff61fe680e Simplify and clean up some machine operand/instr printing/dumping stuff. 
llvm-svn: 45456
 2007-12-30 21:01:27 +00:00
Chris Lattner
98c3fabf47 two register machineoperands are not identical unless their subregs match. 
llvm-svn: 45455
 2007-12-30 20:55:08 +00:00
Chris Lattner
4a4943a78f MachineOperand::getImmedValue -> MachineOperand::getImm 
llvm-svn: 45454
 2007-12-30 20:50:28 +00:00
Chris Lattner
d6051f028d make machine operands fatter: give each one an up-pointer to the 
machineinstr that owns it.

llvm-svn: 45449
 2007-12-30 06:11:04 +00:00
Chris Lattner
19dd6c4eac Start using the simplified methods for adding operands. 
llvm-svn: 45432
 2007-12-30 00:41:17 +00:00
Chris Lattner
e868c77f16 simplify some code by factoring operand construction better. 
llvm-svn: 45428
 2007-12-30 00:12:25 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Evan Cheng
fd33cb316f Clean up sub-register implementation by moving subReg information back to 
MachineOperand auxInfo. Previous clunky implementation uses an external map
to track sub-register uses. That works because register allocator uses
a new virtual register for each spilled use. With interval splitting (coming
soon), we may have multiple uses of the same register some of which are
of using different sub-registers from others. It's too fragile to constantly
update the information.

llvm-svn: 44104
 2007-11-14 07:59:08 +00:00
Evan Cheng
2262b2a792 Optionally create a MachineInstr without default implicit operands. 
llvm-svn: 42945
 2007-10-13 02:23:01 +00:00
Evan Cheng
d11cd4a095 EXTRACT_SUBREG coalescing support. The coalescer now treats EXTRACT_SUBREG like 
(almost) a register copy. However, it always coalesced to the register of the
RHS (the super-register). All uses of the result of a EXTRACT_SUBREG are sub-
register uses which adds subtle complications to load folding, spiller rewrite,
etc.

llvm-svn: 42899
 2007-10-12 08:50:34 +00:00
Dan Gohman
fb60c0dfed Remove isReg, isImm, and isMBB, and change all their users to use 
isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.

llvm-svn: 41958
 2007-09-14 20:33:02 +00:00
Dan Gohman
53119779c2 Remove spurious consts. This fixes warnings with compilers that 
are strict about such things.

llvm-svn: 41956
 2007-09-14 20:08:19 +00:00
Christopher Lamb
cb63a77a51 Remove subreg index from MachineInstr's and also keep vregs as unsigned when adding operands. 
llvm-svn: 40514
 2007-07-26 07:00:46 +00:00
Evan Cheng
88c463eb8c MachineInstr::isPredicable() is no longer needed. 
llvm-svn: 37599
 2007-06-15 19:06:07 +00:00
Evan Cheng
d8b25a2091 Add missing const qualifiers. 
llvm-svn: 37341
 2007-05-29 18:35:22 +00:00
Evan Cheng
6f761adecb Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr. 
llvm-svn: 37121
 2007-05-16 20:56:08 +00:00
Evan Cheng
eea85a767e Added getNumExplicitOperands and findFirstPredOperand. 
llvm-svn: 37064
 2007-05-15 01:26:09 +00:00
Nate Begeman
767ee95d29 llvm bug #1350, parts 1, 2, and 3. 
llvm-svn: 36618
 2007-05-01 05:57:02 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
201771637e Change findRegisterUseOperand() to return operand index instead. 
llvm-svn: 35363
 2007-03-26 22:37:45 +00:00
Evan Cheng
387f1c2bdf Use findRegisterUseOperand to find a kill of particular register. 
llvm-svn: 34512
 2007-02-23 01:04:26 +00:00
Evan Cheng
e4ab9c032b Re-apply my liveintervalanalysis changes. Now with PR1207 fixes. 
llvm-svn: 34428
 2007-02-19 21:49:54 +00:00
Reid Spencer
b27fcf3482 For PR1207: 
Revert patches that caused the problem. Evan, please investigate and reapply
when you've discovered the problem.

llvm-svn: 34399
 2007-02-19 03:20:00 +00:00
Evan Cheng
35f59a6dd2 Added findRegisterDefOperand(). 
llvm-svn: 34380
 2007-02-17 11:10:18 +00:00
Evan Cheng
5b8b96e9de Print <dead> def operands. 
llvm-svn: 34343
 2007-02-16 09:49:18 +00:00
Jeff Cohen
c396e18e8e The best unbreakage yet, addressing Bill's concerns. 
llvm-svn: 32622
 2006-12-16 02:15:42 +00:00
Jeff Cohen
03161dd132 An even better unbreakage... 
llvm-svn: 32617
 2006-12-15 22:57:14 +00:00
Bill Wendling
a3246c4272 Changed llvm_ostream et all to OStream. llvm_cerr, llvm_cout, llvm_null, are 
now cerr, cout, and NullStream resp.

llvm-svn: 32298
 2006-12-07 01:30:32 +00:00
Evan Cheng
59494f9e3d Move copyKillDeadInfo out-of-line. Add findRegisterUseOperand(). 
llvm-svn: 32273
 2006-12-06 08:27:42 +00:00
Evan Cheng
cb65ba1821 - MachineInstr now keeps a ptr to TargetInstrDescriptor instead of Opcode. 
- Remove the ugly TargetInstrDescriptors hack.

llvm-svn: 32032
 2006-11-30 07:08:44 +00:00
Bill Wendling
d8c0883f20 Use llvm streams instead of <iostream> 
llvm-svn: 31985
 2006-11-28 22:48:48 +00:00
Evan Cheng
e176869ec0 Clean up. 
llvm-svn: 31957
 2006-11-28 02:25:34 +00:00
Evan Cheng
98fa7ab4d7 Change MachineInstr ctor's to take a TargetInstrDescriptor reference instead 
of opcode and number of operands.

llvm-svn: 31947
 2006-11-27 23:37:22 +00:00
Chris Lattner
31f45746ad setOperand should not zap the operand list or add implicit operands to an 
instruction.  Doing so breaks the FP stackifier, the alpha branch selector
the sparc fpmover.

This fixes PR1012 and CodeGen/X86/fp-stack-compare.ll

llvm-svn: 31876
 2006-11-20 17:57:22 +00:00
Evan Cheng
cf45b9fa95 Minor updates. 
llvm-svn: 31761
 2006-11-15 20:54:29 +00:00
Evan Cheng
7cabf9d02c - Let MachineInstr ctors add implicit def and use operands. Other operands 
will be inserted before these operands. If the opcode changes (by
  setOpcode), the implicit operands are updated as well.
- Added IsKill, IsDead fields to MachineOperand in preparation for changes
  that move kill / dead info to MachineInstr's.

llvm-svn: 31711
 2006-11-13 23:34:06 +00:00
Evan Cheng
7dab9abfb8 Add methods to add implicit def use operands to a MI. 
llvm-svn: 31675
 2006-11-11 10:20:02 +00:00
Evan Cheng
013597778d Add implicit def / use operands to MachineInstr. 
llvm-svn: 31633
 2006-11-10 08:43:01 +00:00
Chris Lattner
5bb7f41bca be more aggressive about matching identical instructions. 
llvm-svn: 31179
 2006-10-25 18:08:14 +00:00
Chris Lattner
cf4137d0b9 implement MachineOperand::isIdenticalTo 
llvm-svn: 31088
 2006-10-20 22:39:59 +00:00
Chris Lattner
0fad1515ee Only call isUse/isDef on register operands 
llvm-svn: 30118
 2006-09-05 20:19:27 +00:00
Evan Cheng
07d8ccec50 Instructions with variable operands (variable_ops) can have a number required 
operands. e.g.
def CALL32r : I<0xFF, MRM2r, (ops GR32:$dst, variable_ops),
                "call {*}$dst", [(X86call GR32:$dst)]>;
TableGen should emit operand informations for the "required" operands.

Added a target instruction info flag M_VARIABLE_OPS to indicate the target
instruction may have more operands in addition to the minimum required
operands.

llvm-svn: 28791
 2006-06-15 07:22:16 +00:00
Evan Cheng
328b47bc28 Remove a bogus cast. 
llvm-svn: 28492
 2006-05-26 08:00:14 +00:00
Chris Lattner
db888e7880 Final pass of minor cleanups for MachineInstr 
llvm-svn: 28110
 2006-05-04 19:36:09 +00:00
Chris Lattner
32adc4592f Remove redundancy and a level of indirection when creating machine operands 
llvm-svn: 28107
 2006-05-04 19:14:44 +00:00
Chris Lattner
075404adaa Remove and simplify some more machineinstr/machineoperand stuff. 
llvm-svn: 28105
 2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling. 
llvm-svn: 28104
 2006-05-04 18:05:43 +00:00
Chris Lattner
685568510a Move some methods out of MachineInstr into MachineOperand 
llvm-svn: 28102
 2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14 There shalt be only one "immediate" operand type! 
llvm-svn: 28099
 2006-05-04 17:21:20 +00:00