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9 Commits

Author SHA1 Message Date
Nadav Rotem
c23e698b5c Transform: (EXTRACT_VECTOR_ELT( VECTOR_SHUFFLE )) -> EXTRACT_VECTOR_ELT. 
llvm-svn: 148337
 2012-01-17 21:44:01 +00:00
Nadav Rotem
c460c870b2 Fix 11769. 
In CanXFormVExtractWithShuffleIntoLoad we assumed that EXTRACT_VECTOR_ELT can be later handled by the DAGCombiner.
However, in some cases on AVX, the EXTRACT_VECTOR_ELT is legalized to EXTRACT_SUBVECTOR + EXTRACT_VECTOR_ELT, which
currently is not handled by the DAGCombiner. In this patch I added a check that we only extract from the XMM part.

llvm-svn: 148298
 2012-01-17 09:13:19 +00:00
Chad Rosier
b4f2ccc1e0 Cleanup test case by adding checks for test names. 
llvm-svn: 148166
 2012-01-14 01:46:51 +00:00
Elena Demikhovsky
beb66de0f9 Fixed a bug in LowerVECTOR_SHUFFLE caused assertion failure 
lc: X86ISelLowering.cpp:6480: llvm::SDValue llvm::X86TargetLowering::LowerVECTOR_SHUFFLE(llvm::SDValue, llvm::SelectionDAG&) const: Assertion `V1.getOpcode() != ISD::UNDEF&&  "Op 1 of shuffle should not be undef"' failed.
Added a test.

llvm-svn: 148044
 2012-01-12 20:33:10 +00:00
Chad Rosier
afcaa8f38a Enhance DAGCombine for transforming 128->256 casts into a vmovaps, rather 
then a vxorps + vinsertf128 pair if the original vector came from a load.
rdar://10594409

llvm-svn: 147481
 2012-01-03 21:05:52 +00:00
Elena Demikhovsky
9b4613ff14 Fixed a bug in LowerVECTOR_SHUFFLE and LowerBUILD_VECTOR. 
Matching MOVLP mask for AVX (265-bit vectors) was wrong.
The failure was detected by conformance tests.

llvm-svn: 147308
 2011-12-28 08:14:01 +00:00
Evan Cheng
77f0fb0296 Update test to something more sensible. 
llvm-svn: 146282
 2011-12-09 21:54:10 +00:00
Evan Cheng
ad8debd736 Add 256-bit variant vmovss and vmovsd patterns. rdar://10538417 
llvm-svn: 146196
 2011-12-08 22:30:45 +00:00
Eli Friedman
7188ba35cb Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00