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78 Commits

Author SHA1 Message Date
Duraid Madina
51396ffd3e add setJumpBufSize() and setJumpBufAlignment() to target-lowering. 
Call these from your backend to enjoy setjmp/longjmp goodness, see
lib/Target/IA64/IA64ISelLowering.cpp for an example

llvm-svn: 30095
 2006-09-04 06:21:35 +00:00
Andrew Lenharth
a2bda5b0e1 Start on my todo list 
llvm-svn: 28752
 2006-06-12 16:07:18 +00:00
Reid Spencer
574d4e6992 For PR786: 
Minor tweaks in public headers and a few .cpp files so that LLVM can build
successfully with -pedantic and projects using LLVM with -pedantic don't
get warnings from LLVM. There's still more -pedantic warnings to fix.

llvm-svn: 28453
 2006-05-24 19:21:13 +00:00
Evan Cheng
89f7ea0382 Another typo. Pointed out by Nate Begeman. 
llvm-svn: 28353
 2006-05-17 18:22:14 +00:00
Evan Cheng
09c4a5d032 Fix a mis-leading comment. 
llvm-svn: 28350
 2006-05-17 18:08:20 +00:00
Chris Lattner
3e13a7d49e There is now a default impl of this method 
llvm-svn: 28336
 2006-05-16 22:52:11 +00:00
Andrew Lenharth
14504c85ed Move this code to a common place 
llvm-svn: 28329
 2006-05-16 17:42:15 +00:00
Chris Lattner
06d617846d Add some new methods for computing sign bit information. 
llvm-svn: 28144
 2006-05-06 09:26:22 +00:00
Owen Anderson
71bc529dfa Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference. 
This fixes PR 759.

llvm-svn: 28074
 2006-05-03 01:29:57 +00:00
Evan Cheng
ec4d1668ef Added a virtual method isVectorClearMaskLegal to TLI. It is similar to 
isShuffleMaskLegal, used to determine if it makes sense to turn a
"vector clear" (e.g. pand V, <0, -1, 0, -1> to a shuffle of the vector and
a zero vector.

llvm-svn: 27873
 2006-04-20 08:54:13 +00:00
Chris Lattner
048bc55352 Provide a default impl of LowerArguments 
llvm-svn: 27605
 2006-04-12 16:21:12 +00:00
Chris Lattner
1dc3c03ee7 Move isShuffleLegal from TLI to Legalize. 
llvm-svn: 27398
 2006-04-04 17:21:22 +00:00
Chris Lattner
9925c6018f Allow targets to have fine grained control over which types various ops get 
promoted to, if they desire.

llvm-svn: 27389
 2006-04-04 00:25:10 +00:00
Chris Lattner
8e0dfe133c Modify the TargetLowering::getPackedTypeBreakdown method to also return the 
unpromoted element type.

llvm-svn: 27273
 2006-03-31 00:46:36 +00:00
Chris Lattner
557951b354 Add a method useful for decimating vectors. 
llvm-svn: 27269
 2006-03-31 00:28:23 +00:00
Evan Cheng
54215cd1ea Added a ValueType operand to isShuffleMaskLegal(). For now, x86 will not do 
64-bit vector shuffle.

llvm-svn: 26964
 2006-03-22 22:07:06 +00:00
Chris Lattner
a3663c3dbb Add some helper methods 
llvm-svn: 26882
 2006-03-20 00:55:52 +00:00
Evan Cheng
cad75d9f0c Added a way for TargetLowering to specify what values can be used as the 
scale component of the target addressing mode.

llvm-svn: 26802
 2006-03-16 21:47:42 +00:00
Evan Cheng
ed013bd937 Add LSR hooks. 
llvm-svn: 26740
 2006-03-13 23:18:16 +00:00
Chris Lattner
c656f75535 custom lowered nodes are legal too 
llvm-svn: 26561
 2006-03-05 23:49:19 +00:00
Evan Cheng
0c445855f2 Number of NodeTypes now exceeds 128. 
llvm-svn: 26503
 2006-03-03 06:58:59 +00:00
Chris Lattner
40501a50fe Add interfaces for targets to provide target-specific dag combiner optimizations. 
llvm-svn: 26442
 2006-03-01 04:52:55 +00:00
Evan Cheng
b8a44ab1dd Missing a cast previously. 
llvm-svn: 26434
 2006-03-01 00:58:54 +00:00
Chris Lattner
0957a2e87c Add C_Memory operand type 
llvm-svn: 26344
 2006-02-24 01:10:14 +00:00
Chris Lattner
ed45ad33b7 Make the LLVM headers "-ansi -pedantic -Wno-long-long" clean. 
Patch by Martin Partel!

llvm-svn: 26313
 2006-02-22 16:23:43 +00:00
Chris Lattner
6bb2c3e9cd split register class handling from explicit physreg handling. 
llvm-svn: 26308
 2006-02-22 00:56:39 +00:00
Chris Lattner
ed3b59056a Pass in a value type to getRegForInlineAsmConstraint, allowing targets to 
select different sets of registers depending on the type requested.

llvm-svn: 26304
 2006-02-21 23:10:29 +00:00
Nate Begeman
aef186befc Fix a nit sabre noticed 
llvm-svn: 26262
 2006-02-17 18:06:19 +00:00
Nate Begeman
0bc71999b9 Rework the SelectionDAG-based implementations of SimplifyDemandedBits 
and ComputeMaskedBits to match the new improved versions in instcombine.
Tested against all of multisource/benchmarks on ppc.

llvm-svn: 26238
 2006-02-16 21:11:51 +00:00
Evan Cheng
f6c74c0096 Rename maxStoresPerMemSet to maxStoresPerMemset, etc. 
llvm-svn: 26174
 2006-02-14 08:38:30 +00:00
Chris Lattner
478eb50b79 getConstraintType should be virtual. 
llvm-svn: 26041
 2006-02-07 20:13:44 +00:00
Chris Lattner
2395722dbd Add some methods for inline asm support. 
llvm-svn: 25950
 2006-02-04 02:12:09 +00:00
Nate Begeman
2d9838ec9b Add a framework for eliminating instructions that produces undemanded bits. 
llvm-svn: 25945
 2006-02-03 22:24:05 +00:00
Chris Lattner
5583b2e227 Clear the OpAction field before setting it. This allows a target to set 
an instruction operation action to Expand, then set it to Legal later.

llvm-svn: 25812
 2006-01-30 06:09:03 +00:00
Chris Lattner
a1cc69e24e Move MaskedValueIsZero from the DAGCombiner to the TargetLowering interface, 
making isMaskedValueZeroForTargetNode simpler, and useable from other parts
of the compiler.

llvm-svn: 25802
 2006-01-30 04:08:18 +00:00
Chris Lattner
7f64ff5ce0 Pass the address of the main MaskedValueIsZero function to allow recursion. 
llvm-svn: 25797
 2006-01-30 03:48:36 +00:00
Chris Lattner
a8ca8f5eb9 Clean up the interface to ValueTypeActions, allowing Legalize to use a copy 
of it more cleanly.  Double the size of OpActions, allowing it to hold actions
for any VT.

llvm-svn: 25782
 2006-01-29 08:40:37 +00:00
Chris Lattner
2240c0df71 remove this method I just added, now is not the time. 
llvm-svn: 25729
 2006-01-28 03:43:33 +00:00
Chris Lattner
063c13029b add a new callback 
llvm-svn: 25727
 2006-01-28 03:37:03 +00:00
Nate Begeman
87c2c0e66b Implement Promote for VAARG, and allow it to be custom promoted for people 
who don't want the default behavior (Alpha).

llvm-svn: 25726
 2006-01-28 03:14:31 +00:00
Nate Begeman
d2c6fbef4a Remove TLI.LowerReturnTo, and just let targets custom lower ISD::RET for 
the same functionality.  This addresses another piece of bug 680.  Next,
on to fixing Alpha VAARG, which I broke last time.

llvm-svn: 25696
 2006-01-27 21:09:22 +00:00
Chris Lattner
ab8e0e40f9 Add a method for inline asm support. 
llvm-svn: 25656
 2006-01-26 20:27:33 +00:00
Nate Begeman
c29fac7fce First part of bug 680: 
Remove TLI.LowerVA* and replace it with SDNodes that are lowered the same
way as everything else.

llvm-svn: 25606
 2006-01-25 18:21:52 +00:00
Evan Cheng
f4b53efbb2 Add a enum to specify target scheduling preference: SchedulingForLatency or 
SchedulingForRegPressure. Added corresponding methods to set / get the value.

llvm-svn: 25598
 2006-01-25 09:09:02 +00:00
Chris Lattner
8fe9dd16fb Provide an interface for Targets to specify their stack pointer register 
for llvm.stacksave/restore.

llvm-svn: 25275
 2006-01-13 17:47:52 +00:00
Jeff Cohen
8727139340 Oh oh... Unix is case sensitive. 
llvm-svn: 24928
 2005-12-22 01:46:59 +00:00
Jeff Cohen
8afabfd8f1 Make it compile with VC++. 
llvm-svn: 24927
 2005-12-22 01:44:51 +00:00
Evan Cheng
822f360f84 Added TargetLowering::isMaskedValueZeroForTargetNode() declaration. 
llvm-svn: 24923
 2005-12-21 23:15:41 +00:00
Evan Cheng
44e4e6a57f Added a hook to print out names of target specific DAG nodes. 
llvm-svn: 24877
 2005-12-20 06:22:03 +00:00
Nate Begeman
a1c2df2471 Add the majority of the vector machien value types we expect to support, 
and make a few changes to the legalization machinery to support more than
16 types.

llvm-svn: 24511
 2005-11-29 05:45:29 +00:00