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21 Commits

Author SHA1 Message Date
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Owen Anderson
7da515c665 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Evan Cheng
0b9eaaf45d Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Evan Cheng
15fc769cf2 Correct some load / store instruction itinerary mistakes: 
1. Cortex-A8 load / store multiplies can only issue on ALU0.
2. Eliminate A8_Issue, A8_LSPipe will correctly limit the load / store issues.
3. Correctly model all vld1 and vld2 variants.

llvm-svn: 116134
 2010-10-09 01:03:04 +00:00
Bob Wilson
8689a52c10 Change register allocation order for ARM VFP and NEON registers to put the 
callee-saved registers at the end of the lists.  Also prefer to avoid using
the low registers that are in register subclasses required by certain
instructions, so that those registers will more likely be available when needed.
This change makes a huge improvement in spilling in some cases.  Thanks to
Jakob for helping me realize the problem.

Most of this patch is fixing the testsuite.  There are quite a few places
where we're checking for specific registers.  I changed those to wildcards
in places where that doesn't weaken the tests.  The spill-q.ll and
thumb2-spill-q.ll tests stopped spilling with this change, so I added a bunch
of live values to force spills on those tests.

llvm-svn: 116055
 2010-10-08 06:15:13 +00:00
Bob Wilson
8951c7592c Convert VLD1 and VLD2 instructions to use pseudo-instructions until 
after regalloc.

llvm-svn: 112825
 2010-09-02 16:00:54 +00:00
Bob Wilson
c01101e76c Add alignment arguments to all the NEON load/store intrinsics. 
Update all the tests using those intrinsics and add support for
auto-upgrading bitcode files with the old versions of the intrinsics.

llvm-svn: 112271
 2010-08-27 17:13:24 +00:00
Bob Wilson
c3856a5130 Replace some NEON vmovl intrinsic that I missed earlier. 
llvm-svn: 111696
 2010-08-20 23:22:43 +00:00
Bob Wilson
7feb850d36 Use a target-specific VMOVIMM DAG node instead of BUILD_VECTOR to represent 
NEON VMOV-immediate instructions.  This simplifies some things.

llvm-svn: 108275
 2010-07-13 21:16:48 +00:00
Bob Wilson
f15e542bdc Print "dregpair" NEON operands with a space between them, for readability and 
consistency with other instructions that have lists of register operands.

llvm-svn: 107944
 2010-07-09 00:47:20 +00:00
Bob Wilson
dd02fe62a2 Reenable DAG combining for vector shuffles. It looks like it was temporarily 
disabled and then never turned back on again.  Adjust some tests, one because
this change avoids an unnecessary instruction, and the other to make it
continue testing what it was intended to test.

llvm-svn: 107941
 2010-07-09 00:38:12 +00:00
Dan Gohman
d79ac4a097 Eliminate the other half of the BRCOND optimization, and update 
as many tests as possible.

llvm-svn: 106749
 2010-06-24 15:24:03 +00:00
Rafael Espindola
d7a63bead9 Remove arm_apcscc from the test files. It is the default and doing this 
matches what llvm-gcc and clang now produce.

llvm-svn: 106221
 2010-06-17 15:18:27 +00:00
Evan Cheng
849bca1ab6 Fix some latency computation bugs: if the use is not a machine opcode do not just return zero. 
llvm-svn: 105061
 2010-05-28 23:26:21 +00:00
Evan Cheng
6397a77e16 Change ARM scheduling default to list-hybrid if the target supports floating point instructions (and is not using soft float). 
llvm-svn: 104307
 2010-05-21 00:43:17 +00:00
Jakob Stoklund Olesen
6a2bfde3c8 TwoAddressInstructionPass doesn't really know how to merge live intervals when 
lowering REG_SEQUENCE instructions.

Insert copies for REG_SEQUENCE sources not killed to avoid breaking later passes.

llvm-svn: 104146
 2010-05-19 20:08:00 +00:00
Evan Cheng
9fc34e676d Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE. 
llvm-svn: 104050
 2010-05-18 20:03:28 +00:00
Evan Cheng
8aa900cf16 Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions. 
llvm-svn: 103994
 2010-05-17 23:24:12 +00:00
Evan Cheng
378d6c5d76 Fix PR7156. If the sources of a REG_SEQUENCE are all IMPLICIT_DEF's. Replace it with an IMPLICIT_DEF rather than deleting it or else it would be left without a def. 
llvm-svn: 103984
 2010-05-17 22:09:49 +00:00
Evan Cheng
bb0a4fbe13 Careful with reg_sequence coalescing to not to overwrite sub-register indices. 
llvm-svn: 103971
 2010-05-17 20:57:12 +00:00
Evan Cheng
3bce87c79f Turn on -neon-reg-sequence by default. 
Using NEON load / store multiple instructions will no longer create gobs of vmov of D registers!

llvm-svn: 103960
 2010-05-17 19:51:20 +00:00