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182748 Commits

Author SHA1 Message Date
Jinsong Ji
4b2d844f4f [PowerPC][NFC][MachinePipeliner] Add some regression testcases
Exposed by refactoring in https://reviews.llvm.org/D64665.

llvm-svn: 367732
2019-08-02 22:27:44 +00:00
Douglas Yung
103ef490da Revert Fix and test inter-procedural register allocation for ARM
This reverts r367669 (git commit f6b00c279a5587a25876752a6ecd8da0bed959dc)

This was breaking a build bot http://lab.llvm.org:8011/builders/netbsd-amd64/builds/21233

llvm-svn: 367731
2019-08-02 22:11:49 +00:00
Stella Stamenova
c0f4100fc7 [lit] Fix 42812: lit test suite can no longer be run stand-alone
Summary:
This change updates the lit.cfg file to use llvm_config when it is available, but when it is not, it directly modifies the config object. This makes it possible to run the lit tests standalone without having built llvm (as long as the correct binaries are present in the path such as FileCheck and not).

Because the lit tests don't take a hard dependency on llvm_config, some features such as system-windows have to have definitions in lit's cfg file as well. This is a potential issue as the os features sometimes change names (for example, we went from windows to system-windows, etc.). This can cause drift between lit's tests and the rest of the llvm tests.

Reviewers: probinson, mgorny

Reviewed By: mgorny

Subscribers: delcypher, llvm-commits, asmith

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65674

llvm-svn: 367730
2019-08-02 22:03:12 +00:00
JF Bastien
507c70c558 Revert "Remove support for unsupported MSVC versions"
Mismatched preprocessor, I'll fix in a follow-up.

llvm-svn: 367728
2019-08-02 22:02:25 +00:00
JF Bastien
92e42b0a20 Remove support for unsupported MSVC versions
Reviewers: rnk, lebedev.ri

Subscribers: hiraditya, jkorous, dexonsmith, lebedev.ri, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65662

llvm-svn: 367727
2019-08-02 21:52:35 +00:00
Stefan Stipanovic
1866a358f4 [Attributor] Using liveness in other attributes.
Modifying other AbstractAttributes to use Liveness AA and skip dead instructions.

Reviewers: jdoerfert, uenoku

Subscribers: hiraditya, llvm-commits

Differential revision: https://reviews.llvm.org/D65243

llvm-svn: 367725
2019-08-02 21:31:22 +00:00
Yonghong Song
1f886e2f2a [BPF] annotate DIType metadata for builtin preseve_array_access_index()
Previously, debuginfo types are annotated to
IR builtin preserve_struct_access_index() and
preserve_union_access_index(), but not
preserve_array_access_index(). The debug info
is useful to identify the root type name which
later will be used for type comparison.

For user access without explicit type conversions,
the previous scheme works as we can ignore intermediate
compiler generated type conversions (e.g., from union types to
union members) and still generate correct access index string.

The issue comes with user explicit type conversions, e.g.,
converting an array to a structure like below:
  struct t { int a; char b[40]; };
  struct p { int c; int d; };
  struct t *var = ...;
  ... __builtin_preserve_access_index(&(((struct p *)&(var->b[0]))->d)) ...
Although BPF backend can derive the type of &(var->b[0]),
explicit type annotation make checking more consistent
and less error prone.

Another benefit is for multiple dimension array handling.
For example,
  struct p { int c; int d; } g[8][9][10];
  ... __builtin_preserve_access_index(&g[2][3][4].d) ...
It would be possible to calculate the number of "struct p"'s
before accessing its member "d" if array debug info is
available as it contains each dimension range.

This patch enables to annotate IR builtin preserve_array_access_index()
with proper debuginfo type. The unit test case and language reference
is updated as well.

Signed-off-by: Yonghong Song <yhs@fb.com>

Differential Revision: https://reviews.llvm.org/D65664

llvm-svn: 367724
2019-08-02 21:28:28 +00:00
Amara Emerson
785f4c1ed2 [AArch64][GlobalISel] Eliminate redundant G_ZEXT when the source is implicitly zext-loaded.
These cases can come up when the extending loads combiner doesn't combine a
zext(load) to a zextload op, due to some other operation being in between, which
then gets simplified at a later stage.

Differential Revision: https://reviews.llvm.org/D65360

llvm-svn: 367723
2019-08-02 21:15:36 +00:00
Simon Pilgrim
ebe4ff9c2b [TargetLowering] SimplifyMultipleUseDemandedBits - don't assume INSERT_VECTOR_ELT value type is simple.
Noticed by inspection - this was copied from the X86 target equivalent where we can assume its legal/simple.

llvm-svn: 367721
2019-08-02 21:07:07 +00:00
Daniel Sanders
fedbc49000 Use MCRegister in MCRegisterInfo's interfaces
Summary:
As part of this, define DenseMapInfo for MCRegister (and Register while I'm at it)

Depends on D65599

Reviewers: arsenm

Subscribers: MatzeB, qcolombet, jvesely, wdng, nhaehnle, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65605

llvm-svn: 367719
2019-08-02 20:23:00 +00:00
Philip Reames
050c82570a [Statepoints] Fix overalignment of loads in no-realign-stack functions
This really should have been part of 366765.  For some reason, I forgot to handle the corresponding load side, and the readable test cases (using deopt vs statepoints) turned out to be overly reduced.  Oops.

As seen in the test change, the problem was that we were using a load with alignment expectations rather than the unaligned variant when the stack alignment was less than that prefered type alignment.

llvm-svn: 367718
2019-08-02 20:17:37 +00:00
Peter Collingbourne
1d38f6deb9 hwasan: Remove unused field CurModuleUniqueId. NFCI.
llvm-svn: 367717
2019-08-02 20:14:58 +00:00
Lang Hames
cba634369c [ORC] Remove a dead method.
llvm-svn: 367716
2019-08-02 20:09:30 +00:00
Craig Topper
6d76a4bcea [ScalarizeMaskedMemIntrin] Add constant mask support to expandload and compressstore scalarization
This adds support for generating all the loads or stores for a constant mask into a single basic block with no conditionals.

Differential Revision: https://reviews.llvm.org/D65613

llvm-svn: 367715
2019-08-02 20:04:34 +00:00
Philip Reames
f4079cb7ec [Test] Demonstrate a realignment bug missed in r366765
llvm-svn: 367714
2019-08-02 20:01:43 +00:00
Jinsong Ji
233eb03485 [PowerPC][NFC] Enable ADT BitVectorTest
Test on ppc64le passed.
This fix https://bugs.llvm.org/show_bug.cgi?id=42702

llvm-svn: 367713
2019-08-02 19:58:00 +00:00
Lang Hames
c847808d77 [ORC] Turn on symbol-flags overrides for LLJIT on Windows by default.
libObject does not apply the Exported flag to symbols in COFF object files,
which can lead to assertions when the symbol flags initially derived from
IR added to the JIT clash with the flags seen by the JIT linker. Both
RTDyldObjectLinkingLayer and ObjectLinkingLayer have a workaround for this:
they can be told to override the flags seen by the linker with the flags
attached to the materialization responsibility object that was passed down
to the linker. This patch modifies LLJIT's setup code to enable this override
by default on platforms where COFF is the default object format.

llvm-svn: 367712
2019-08-02 19:43:20 +00:00
Daniel Sanders
22e7bf14f7 Add MCRegister and use it in MCRegisterClass::contains()
Summary:
Register can cast to MCRegister and we may want to consider asserting
!isValid() || isPhysical() when expensive checks are on.

Depends on D65554

Reviewers: arsenm

Subscribers: wdng, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65599

llvm-svn: 367711
2019-08-02 19:37:17 +00:00
Sanjay Patel
6449e66c97 [DAGCombiner] try to convert opposing shifts to casts
This reverses a questionable IR canonicalization when a truncate
is free:

sra (add (shl X, N1C), AddC), N1C -->
sext (add (trunc X to (width - N1C)), AddC')

https://rise4fun.com/Alive/slRC

More details in PR42644:
https://bugs.llvm.org/show_bug.cgi?id=42644

I limited this to pre-legalization for code simplicity because that
should be enough to reverse the IR patterns. I don't have any
evidence (no regression test diffs) that we need to try this later.

Differential Revision: https://reviews.llvm.org/D65607

llvm-svn: 367710
2019-08-02 19:33:46 +00:00
Eric Christopher
3ca8e94f65 Temporarily Revert "Changing representation of cv_def_range directives in Codeview debug info assembly format for better readability"
This is breaking bots and the author asked me to revert.

This reverts commit 367704.

llvm-svn: 367707
2019-08-02 19:10:37 +00:00
Nilanjana Basu
4126a8f15d Changing representation of cv_def_range directives in Codeview debug info assembly format for better readability
llvm-svn: 367704
2019-08-02 18:44:39 +00:00
Alina Sbirlea
2da2801c96 [NewPassManager] Resolve assertion in CGSCCPassManager when CallCounts change.
Summary:
If the CallCounts change after an iteration of the DevirtSCCRepeatedPass, this is not reflected in the local CallCounts structure triggering the assertion checking the before/after sizes.
Since it is valid for the size to change and this only uses the CallCounts for the devirtualizing heuristic, keep a <Function*, CallCount> map instead, and make the devirtualizing decision using the counts for the functions that exist both before and after the pass.

Resolves PR42726.

Reviewers: chandlerc

Subscribers: mehdi_amini, jlebar, sanjoy.google, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65621

llvm-svn: 367703
2019-08-02 18:37:03 +00:00
George Rimar
01f8709122 [llvm-objcopy] - Fix the strip-dwo-groups.test.
It was reported (https://reviews.llvm.org/D65273#1612246)
that this test fails if the compilation directory contain
a "debug_" substring.

This should fix it.

llvm-svn: 367702
2019-08-02 18:22:46 +00:00
Jessica Paquette
7f4d840652 [AArch64][GlobalISel] Support the neg_addsub_shifted_imm32 pattern
Add an equivalent ComplexRendererFns function for SelectNegArithImmed. This
allows us to select immediate adds of -1 by turning them into subtracts.

Update select-binop.mir to show that the pattern works.

Differential Revision: https://reviews.llvm.org/D65460

llvm-svn: 367700
2019-08-02 18:12:53 +00:00
Alina Sbirlea
2f3c53a88e [SimplifyCFG] Cleanup redundant conditions [NFC].
Summary:
Since the for loop iterates over BB's predecessors, the branch conditions found must have BB as one of the successors.
For an unconditional branch the successor must be BB, added `assert`.
For a conditional branch, one of the two successors must be BB, simplify `else if` to `else` and `assert`.
Sink common instructions outside the if/else block.

Reviewers: sanjoy.google

Subscribers: jlebar, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D65596

llvm-svn: 367699
2019-08-02 18:06:54 +00:00
Simon Pilgrim
538c639d53 [AMDGPU] Regenerated saddo.ll test file for D47927
llvm-svn: 367698
2019-08-02 17:52:55 +00:00
Daniel Sanders
cb1bdeca8d Fix ARC after r367633
llvm-svn: 367697
2019-08-02 17:52:17 +00:00
Peter Collingbourne
35a0672873 CodeGen: Don't follow aliases when extracting type info.
This fixes a crash in the case where the type info object is an alias
pointing to a non-zero offset within a global or is otherwise unanalyzable
by the stripPointerCasts() function. Looking through the alias is not the
right thing to do anyway for similar reasons as D65118.

Differential Revision: https://reviews.llvm.org/D65314

llvm-svn: 367696
2019-08-02 17:43:45 +00:00
Sanjay Patel
d2c85e3ceb [InstCombine] fold cmp+select using select operand equivalence
As discussed in PR42696:
https://bugs.llvm.org/show_bug.cgi?id=42696
...but won't help that case yet.

We have an odd situation where a select operand equivalence fold was
implemented in InstSimplify when it could have been done more generally
in InstCombine if we allow dropping of {nsw,nuw,exact} from a binop operand.

Here's an example:
https://rise4fun.com/Alive/Xplr

  %cmp = icmp eq i32 %x, 2147483647
  %add = add nsw i32 %x, 1
  %sel = select i1 %cmp, i32 -2147483648, i32 %add
  =>
  %sel = add i32 %x, 1

I've left the InstSimplify code in place for now, but my guess is that we'd
prefer to remove that as a follow-up to save on code duplication and
compile-time.

Differential Revision: https://reviews.llvm.org/D65576

llvm-svn: 367695
2019-08-02 17:39:32 +00:00
James Y Knight
3f801ddf08 Fix git-llvm to not delete non-empty directories.
Previously, if a directory contained only other sub-directories, one
of which was being removed, git llvm would delete the parent and all
its subdirs, even though only one should've been deleted.

This error occurred in r366590, where the commit attempted to remove
lldb/packages/Python/lldbsuite/test/tools/lldb-mi, but git-llvm
erroneously removed the entire contents of
lldb/packages/Python/lldbsuite/test/tools.

This happened because "git apply" automatically removes empty
directories locally, and the absence of a local directory was
previously taken as an indication to call 'svn rm' on that
directory. However, an empty local directory does not necessarily
indicate that the directory is truly empty.

Fix that by removing directories only when they're empty on the git
side.

Differential Revision: https://reviews.llvm.org/D65416

llvm-svn: 367693
2019-08-02 17:10:04 +00:00
Peter Collingbourne
53643d6c06 gn build: Merge r367667.
llvm-svn: 367692
2019-08-02 17:02:05 +00:00
Paul Robinson
65503fe2fe [doc] Give a workaround for a FileCheck regex that ends in a brace.
Addresses PR42864.

llvm-svn: 367689
2019-08-02 16:07:48 +00:00
Teresa Johnson
07f2331c21 Use llvm-nm instead of nm in new test to unbreak Windows bot
New test added in r367679 used nm and should use llvm-nm.

llvm-svn: 367688
2019-08-02 15:49:39 +00:00
Lang Hames
a6587cc70d [ORC] Change the locking scheme for ThreadSafeModule.
ThreadSafeModule/ThreadSafeContext are used to manage lifetimes and locking
for LLVMContexts in ORCv2. Prior to this patch contexts were locked as soon
as an associated Module was emitted (to be compiled and linked), and were not
unlocked until the emit call returned. This could lead to deadlocks if
interdependent modules that shared contexts were compiled on different threads:
when, during emission of the first module, the dependence was discovered the
second module (which would provide the required symbol) could not be emitted as
the thread emitting the first module still held the lock.

This patch eliminates this possibility by moving to a finer-grained locking
scheme. Each client holds the module lock only while they are actively operating
on it. To make this finer grained locking simpler/safer to implement this patch
removes the explicit lock method, 'getContextLock', from ThreadSafeModule and
replaces it with a new method, 'withModuleDo', that implicitly locks the context,
calls a user-supplied function object to operate on the Module, then implicitly
unlocks the context before returning the result.

ThreadSafeModule TSM = getModule(...);
size_t NumFunctions = TSM.withModuleDo(
    [](Module &M) { // <- context locked before entry to lambda.
      return M.size();
    });

Existing ORCv2 layers that operate on ThreadSafeModules are updated to use the
new method.

This method is used to introduce Module locking into each of the existing
layers.

llvm-svn: 367686
2019-08-02 15:21:37 +00:00
David Candler
f44af90ee1 [NFC] Test commit, corrected some spelling in comment
Test commit, corrected some spelling in comment.

Differential Revision: https://reviews.llvm.org/D65516

llvm-svn: 367685
2019-08-02 14:44:17 +00:00
Tim Northover
2dffc88cad GlobalISel: support swiftself attribute
llvm-svn: 367683
2019-08-02 14:09:49 +00:00
Teresa Johnson
d13618986a Fix new test try 2
Fix second (and last) instance of wrong Input file name in new test
added in r367679.

llvm-svn: 367682
2019-08-02 13:49:48 +00:00
Teresa Johnson
ba00c92a1a Fix new test
Thew new test added in r367679 was using the wrong copy of the Input
file.

llvm-svn: 367680
2019-08-02 13:26:18 +00:00
Teresa Johnson
0273961b82 [ThinLTO] Implement index-based WPD
This patch adds support to the WholeProgramDevirt pass to perform
index-based WPD, which is invoked from ThinLTO during the thin link.

The ThinLTO backend (WPD import phase) behaves the same regardless of
whether the WPD decisions were made with the index-based or (the
existing) IR-based analysis.

Depends on D54815.

Reviewers: pcc

Subscribers: mehdi_amini, inglorion, eraman, steven_wu, dexonsmith, arphaman, dang, llvm-commits

Differential Revision: https://reviews.llvm.org/D55153

llvm-svn: 367679
2019-08-02 13:10:52 +00:00
Sanjay Patel
3f8e72c714 [x86] add/adjust tests for shift-add-shift; NFC
Goes with D65607.

llvm-svn: 367677
2019-08-02 11:50:03 +00:00
Martin Storsjo
312512790c [llvm-dlltool] Clarify an error message. NFC.
The parameter to the -D (--dllname) option is the name of the dll
that llvm-dlltool produces an import library for. Even though this
is named "OutputFile" in the COFFModuleDefinition class, it's not
an output file name in the context of llvm-dlltool, but the name
of the DLL to create an import library for.

llvm-svn: 367676
2019-08-02 11:20:03 +00:00
Andrea Di Biagio
66df8adc20 [MCA] Add support for printing immedate values as hex. Also enable lexing of masm binary and hex literals.
This patch adds a new llvm-mca flag named -print-imm-hex.

By default, the instruction printer prints immediate operands as decimals. Flag
-print-imm-hex enables the instruction printer to print those operands in hex.

This patch also adds support for MASM binary and hex literal numbers (example
0FFh, 101b).
Added tests to verify the behavior of the new flag. Tests also verify that masm
numeric literal operands are now recognized.

Differential Revision: https://reviews.llvm.org/D65588

llvm-svn: 367671
2019-08-02 10:38:25 +00:00
Oliver Stannard
fac519c9d7 [IPRA][ARM] Disable no-CSR optimisation for ARM
This optimisation isn't generally profitable for ARM, because we can
save/restore many registers in the prologue and epilogue using the PUSH
and POP instructions, but mostly use individual LDR/STR instructions for
other spills.

Differential revision: https://reviews.llvm.org/D64910

llvm-svn: 367670
2019-08-02 10:23:17 +00:00
Oliver Stannard
c00402ed88 Fix and test inter-procedural register allocation for ARM
- Avoid a crash when IPRA calls ARMFrameLowering::determineCalleeSaves
  with a null RegScavenger. Simply not updating the register scavenger
  is fine because IPRA only cares about the SavedRegs vector, the acutal
  code of the function has already been generated at this point.
- Add a new hook to TargetRegisterInfo to get the set of registers which
  can be clobbered inside a call, even if the compiler can see both
  sides, by linker-generated code.

Differential revision: https://reviews.llvm.org/D64908

llvm-svn: 367669
2019-08-02 10:23:05 +00:00
Serguei Katkov
dd9035157b [Loop Peeling] Introduce an option for profile based peeling disabling.
This patch adds an ability to disable profile based peeling 
causing the peeling of all iterations and as a result prohibits
further unroll/peeling attempts on that loop.

The motivation to get an ability to separate peeling usage in
pipeline where in the first part we peel only separate iterations if needed
and later in pipeline we apply the full peeling which will prohibit further peeling.

Reviewers: reames, fhahn
Reviewed By: reames
Subscribers: hiraditya, zzheng, dmgreen, llvm-commits
Differential Revision: https://reviews.llvm.org/D64983

llvm-svn: 367668
2019-08-02 09:32:52 +00:00
Jay Foad
49491c746e [LV] Fix test failure in a Release build.
llvm-svn: 367666
2019-08-02 08:33:41 +00:00
Sam Parker
5993431721 [NFC][ARM[ParallelDSP] Rename/remove/change types
Remove forward declaration, fold a couple of typedefs and change one
to be more useful.

llvm-svn: 367665
2019-08-02 08:21:17 +00:00
Peter Smith
b8d8637f8d [AliasAnalysis] Initialize a member variable that may be used by unit test.
The unit tests in BasicAliasAnalysisTest use the alias analysis API
directly and do not call setAAResults to initalize AAR. This gives a
valgrind error "Conditional Jump depends on unitialized variable".

On most buildbots the variable is nullptr, but in some cases it can be
non nullptr leading to seemingly random failures.

These tests were disabled in r366986. With the initialization they can be
enabled again.

Fixes PR42719

Differential Revision: https://reviews.llvm.org/D65568

llvm-svn: 367662
2019-08-02 08:05:14 +00:00
Sam Parker
d898f1e745 [NFC][ARM][ParallelDSP] Remove ValueList
We only care about the first element in the list.

llvm-svn: 367660
2019-08-02 07:32:28 +00:00
Hideki Saito
ddedfa8803 Moves the newly added test interleaved-accesses-waw-dependency.ll to X86 subdirectory.
ps4-buildslave1 reported a failure. The test has x86 triple.

llvm-svn: 367659
2019-08-02 07:25:09 +00:00