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3774 Commits

Author SHA1 Message Date
Evan Cheng
1ed1741260 Some restructuring in preparation for most aggressive if-conversion. 
llvm-svn: 37231
 2007-05-18 18:14:37 +00:00
Dan Gohman
d6a33914fb Qualify several calls to functions in the MVT namespace, for consistency. 
llvm-svn: 37230
 2007-05-18 17:52:13 +00:00
Evan Cheng
234f07808b Watch out for blocks that end with a return. 
llvm-svn: 37227
 2007-05-18 17:06:53 +00:00
Evan Cheng
40eecb3d06 If true / false blocks fallthrough before ifcvt, add unconditional branches to ifcvt'd block. 
llvm-svn: 37200
 2007-05-18 01:55:58 +00:00
Dale Johannesen
ca37006ffb Remove some unneeded branches. (spotted by Evan, thanks) 
llvm-svn: 37198
 2007-05-18 01:28:58 +00:00
Evan Cheng
c6aa69557a Make use of target specific block size limits; bug fixes. 
llvm-svn: 37195
 2007-05-18 00:20:58 +00:00
Evan Cheng
b4cc6606d5 Move isSuccessor() offline, change it to use std::find. 
llvm-svn: 37190
 2007-05-17 23:58:53 +00:00
Chris Lattner
910abfbfd1 disable MaskedValueIsZero, ComputeMaskedBits, and SimplifyDemandedBits for 
i128 integers.  The 64-bit masks are not wide enough to represent the results.
These should be converted to APInt someday.

llvm-svn: 37169
 2007-05-17 18:19:23 +00:00
Chris Lattner
d441344214 add expand support for ADDC/SUBC/ADDE/SUBE so we can codegen 128-bit add/sub on 32-bit (or less) targets 
llvm-svn: 37168
 2007-05-17 18:15:41 +00:00
Evan Cheng
3163b77d5e Add target hook to specify block size limit for if-conversion. 
llvm-svn: 37134
 2007-05-16 23:45:53 +00:00
Dale Johannesen
cc99a6fc32 Don't fold bitconvert(load) for preinc/postdec loads. Likewise stores. 
llvm-svn: 37130
 2007-05-16 22:45:30 +00:00
Evan Cheng
ab88e91c81 isBlockPredicable() always ignore terminal instructions; add comments. 
llvm-svn: 37126
 2007-05-16 21:54:37 +00:00
Evan Cheng
6f761adecb Rename M_PREDICATED to M_PREDICABLE; Moved isPredicable() to MachineInstr. 
llvm-svn: 37121
 2007-05-16 20:56:08 +00:00
Duncan Sands
3296999dbb Output exception call-sites in address order, as required by the unwinding 
runtime.

llvm-svn: 37104
 2007-05-16 12:12:23 +00:00
Chris Lattner
a18b36cf45 Use a ptr set instead of a linear search to unique TokenFactor operands. 
This fixes PR1423

llvm-svn: 37102
 2007-05-16 06:37:59 +00:00
Evan Cheng
3fb34a4fdd Devang points out that we need an assertion here. 
llvm-svn: 37097
 2007-05-16 05:11:10 +00:00
Evan Cheng
a781c7788a Bug fix: should check ABI alignment, not pref. alignment. 
llvm-svn: 37094
 2007-05-16 02:04:50 +00:00
Evan Cheng
aafca4d4a2 Initial commit of (very basic) if converter. 
llvm-svn: 37092
 2007-05-16 02:00:57 +00:00
Dale Johannesen
78ae2e1acb Remove extra CFG edges before doing these passes; it makes them happier. 
llvm-svn: 37089
 2007-05-15 21:19:17 +00:00
Lauro Ramos Venancio
251ea5ab65 Fix an infinite recursion in GetNegatedExpression. 
llvm-svn: 37086
 2007-05-15 17:05:43 +00:00
Duncan Sands
eddbb07561 The index into the actions table is a ULEB128 not a SLEB128. 
llvm-svn: 37084
 2007-05-15 13:54:14 +00:00
Reid Spencer
b1ac506546 Un-brain-dead-ify the lowering of part set for the reverse case. 
llvm-svn: 37071
 2007-05-15 02:26:52 +00:00
Chris Lattner
ba648e0d45 Fix some subtle issues handling immediate values. This fixes 
test/CodeGen/ARM/2007-05-14-InlineAsmCstCrash.ll

llvm-svn: 37069
 2007-05-15 01:33:58 +00:00
Evan Cheng
eea85a767e Added getNumExplicitOperands and findFirstPredOperand. 
llvm-svn: 37064
 2007-05-15 01:26:09 +00:00
Chris Lattner
eba1b74df3 implement a simple fneg optimization/propagation thing. This compiles: 
CodeGen/PowerPC/fneg.ll into:

_t4:
        fmul f0, f3, f4
        fmadd f1, f1, f2, f0
        blr

instead of:

_t4:
        fneg f0, f3
        fmul f0, f0, f4
        fmsub f1, f1, f2, f0
        blr

llvm-svn: 37054
 2007-05-14 22:04:50 +00:00
Evan Cheng
9645be8cf5 Only worry about intervening kill if there are more than one live ranges in the interval. 
llvm-svn: 37052
 2007-05-14 21:23:51 +00:00
Evan Cheng
e9e48bcf28 Fix for PR1406: 
v1 =
r2 = move v1
   = op r2<kill>
...
r2 = move v1
   = op r2<kill>

Clear the first r2 kill if v1 and r2 are joined.

llvm-svn: 37050
 2007-05-14 21:10:05 +00:00
Evan Cheng
bb876d7323 When marking a register as being implicitly defined, make sure to clear its partial use info as well. 
llvm-svn: 37046
 2007-05-14 20:39:18 +00:00
Reid Spencer
afe2314bb0 Give names to the final result values of the part_set computations. This 
just aids in readability and debugability of the output. No functional change.

llvm-svn: 37037
 2007-05-14 17:21:17 +00:00
Anton Korobeynikov
ad0dd14386 Emit function debug frames in one atom. This will prevent us from generating incorrect assembler in case of both 
debug information & exception information presented.

llvm-svn: 37019
 2007-05-13 17:30:11 +00:00
Anton Korobeynikov
100919126f Emit multiple common EH frames for multiple (including blank) personality 
functions. This partly fixes PR1414: now we're restricted only to one
personality function per eh frame, not per module. Further work on
"multiple personalities" topic needs representative example.

llvm-svn: 37018
 2007-05-13 15:42:26 +00:00
Anton Korobeynikov
7daaf71b29 More DWARF-related things cleanup: 
1. Fix PR1380
2. Apply Duncan's patch from PR1410
3. Insert workaround for "one personality function per module" as noted in PR1414
4. Emit correct debug frames for x86/linux. This partly fixes DebugInfo/2006-11-06-StackTrace.cpp: stack trace is
shown correctly, but arguments for function on top of stack are displayed incorrectly.

llvm-svn: 37015
 2007-05-12 22:36:25 +00:00
Reid Spencer
e7a70b7212 Get the size of auto arrays right, regardless of its changing size. 
llvm-svn: 37006
 2007-05-12 11:07:40 +00:00
Devang Patel
c611adb5b7 Fix http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20070507/049516.html 
llvm-svn: 36998
 2007-05-11 23:14:43 +00:00
Anton Korobeynikov
5754e67b1a Perform correct actions numbers/sizes computation 
llvm-svn: 36988
 2007-05-11 08:47:35 +00:00
Anton Korobeynikov
2d2a44b71f Fix action No calculation in multiple-invoke-one-LP mode 
llvm-svn: 36987
 2007-05-11 08:23:57 +00:00
Dale Johannesen
2f28ffc5fd Do not generate branches to entry block. This fixes several test suite 
failures on PPC (can happen only when prologue code is null)

llvm-svn: 36979
 2007-05-10 23:59:23 +00:00
Anton Korobeynikov
5ba99a95e8 Ooops. Some debugging stuff :) 
llvm-svn: 36978
 2007-05-10 22:38:46 +00:00
Anton Korobeynikov
0a29b65e0c Allow multiple invokes per landing pad. This (probably) fixes PR1410. 
llvm-svn: 36977
 2007-05-10 22:34:59 +00:00
Duncan Sands
828ef09f10 Later computations assume we are aligned at this point. 
llvm-svn: 36975
 2007-05-10 18:40:24 +00:00
Anton Korobeynikov
a25bb3a0ff TypeIds are indexed by j, not i 
llvm-svn: 36974
 2007-05-10 15:10:34 +00:00
Dale Johannesen
4f9661688c Make tail merging handle many more cases (all it can, I think). 
llvm-svn: 36966
 2007-05-10 01:01:49 +00:00
Evan Cheng
649f25dad1 Can't fold the bit_convert is the store is a truncating store. 
llvm-svn: 36962
 2007-05-09 21:49:47 +00:00
Anton Korobeynikov
4423f1a3fd Do not assert, when case range split metric is zero and JTs are not allowed: just emit binary tree in this case. This 
fixes PR1403.

llvm-svn: 36959
 2007-05-09 20:07:08 +00:00
Bill Wendling
a5f8cb0805 Change names from RA to something unique to get rid of naming conflicts with 
certain linkers...

llvm-svn: 36944
 2007-05-08 19:02:46 +00:00
Evan Cheng
855b26b72e Eliminate MarkVirtRegAliveInBlock recursion. 
llvm-svn: 36943
 2007-05-08 19:00:00 +00:00
Evan Cheng
e18b87868d Forgot a check. 
llvm-svn: 36910
 2007-05-07 21:36:06 +00:00
Evan Cheng
18d994d6d6 Enable a couple of xforms: 
- (store (bitconvert v)) -> (store v) if resultant store does not require
higher alignment
- (bitconvert (load v)) -> (load (bitconvert*)v) if resultant load does not
require higher alignment

llvm-svn: 36908
 2007-05-07 21:27:48 +00:00
Dale Johannesen
c884abe112 Handle some non-exit blocks in tail merging. 
llvm-svn: 36907
 2007-05-07 20:57:21 +00:00
Duncan Sands
20a9ed0e20 Parameter attributes on invoke calls were being lost due to the wrong 
attribute index being used.  Fix proposed by Anton Korobeynikov, who
asked me to implement and commit it for him.  This is PR1398.

llvm-svn: 36906
 2007-05-07 20:49:28 +00:00
Anton Korobeynikov
3765489a61 Detabify 
llvm-svn: 36891
 2007-05-06 20:14:21 +00:00
Nick Lewycky
c2306ff5b4 Fix typo in comment. 
llvm-svn: 36873
 2007-05-06 13:37:16 +00:00
Duncan Sands
4459cd664c Use the personality function that was registered with MMI rather than 
hardwiring in the C++ one.

llvm-svn: 36789
 2007-05-05 20:27:00 +00:00
Chris Lattner
d1534330ee Propagate alignment/volatility in two places. 
Implement support for expanding a bitcast from an illegal vector type to
a legal one (e.g. 4xi32 -> 4xf32 in SSE1).  This fixes PR1371 and
CodeGen/X86/2007-05-05-VecCastExpand.ll

llvm-svn: 36787
 2007-05-05 19:39:05 +00:00
Duncan Sands
be371cc319 Spelling fix. 
llvm-svn: 36781
 2007-05-05 16:32:57 +00:00
Anton Korobeynikov
ce48606d7a Emit sections/directives in the proper order. This fixes PR1376. Also, 
some small cleanup was made.

llvm-svn: 36780
 2007-05-05 09:04:50 +00:00
Duncan Sands
f2323ca89c A bitcast of a global variable may have been constant folded to a GEP - 
handle this case too.

llvm-svn: 36745
 2007-05-04 17:12:26 +00:00
Evan Cheng
8c8b6ce116 Don't create indexed load / store with zero offset! 
llvm-svn: 36716
 2007-05-03 23:52:19 +00:00
Chris Lattner
e95894e9f9 Allow i/s to match (gv+c). This fixes CodeGen/PowerPC/2007-05-03-InlineAsm-S-Constraint.ll 
and PR1382

llvm-svn: 36672
 2007-05-03 16:54:34 +00:00
Devang Patel
cd45427a87 Drop 'const' 
llvm-svn: 36662
 2007-05-03 01:11:54 +00:00
Anton Korobeynikov
ca71b83e50 Properly set arguments bitwidth of EHSELECT node 
llvm-svn: 36654
 2007-05-02 22:15:48 +00:00
Devang Patel
8ee9065162 Use 'static const char' instead of 'static const int'. 
Due to darwin gcc bug, one version of darwin linker coalesces
static const int, which defauts PassID based pass identification.

llvm-svn: 36652
 2007-05-02 21:39:20 +00:00
Lauro Ramos Venancio
57d03e112b Fix build error. 
llvm-svn: 36648
 2007-05-02 20:37:47 +00:00
Anton Korobeynikov
6e6bfcaf4d Fix couple of bugs connected with eh info: 
1. Correct output offsets on Linux
2. Fix "style" of personality function. It shouldn't be indirect.

llvm-svn: 36633
 2007-05-01 22:23:12 +00:00
Devang Patel
38a66bc82e Do not use typeinfo to identify pass in pass manager. 
llvm-svn: 36632
 2007-05-01 21:15:47 +00:00
Evan Cheng
17f967eb52 If call frame is not part of stack frame and no dynamic alloc, eliminateFrameIndex() must adjust SP offset with size of call frames. 
llvm-svn: 36625
 2007-05-01 09:01:42 +00:00
Evan Cheng
6dc02c2b07 Forgot about chain result; also UNDEF cannot have multiple values. 
llvm-svn: 36622
 2007-05-01 08:53:39 +00:00
Nate Begeman
767ee95d29 llvm bug #1350, parts 1, 2, and 3. 
llvm-svn: 36618
 2007-05-01 05:57:02 +00:00
Evan Cheng
248de25fb5 Under normal circumstances, when a frame pointer is not required, we reserve 
argument space for call sites in the function immediately on entry to the
current function. This eliminates the need for add/sub sp brackets around call
sites. However, this is not always a good idea. If the "call frame" is large and
the target load / store instructions have small immediate field to encode sp
offset, this can cause poor codegen. In the worst case, this can make it
impossible to scavenge a register if the reserved spill slot is pushed too far
apart from sp / fp.

llvm-svn: 36607
 2007-05-01 00:52:08 +00:00
Evan Cheng
fe933cd6ca * Only turn a load to UNDEF if all of its outputs have no uses (indexed loads 
produce two results.)
* Do not touch volatile loads.

llvm-svn: 36604
 2007-05-01 00:38:21 +00:00
Chris Lattner
8da69f853c Fix PR1228 and CodeGen/Generic/2007-04-30-LandingPadBranchFolding.ll 
llvm-svn: 36602
 2007-04-30 23:35:00 +00:00
Chris Lattner
c7f45f4572 print isLandingPad() for MBBs 
llvm-svn: 36600
 2007-04-30 23:12:53 +00:00
Chris Lattner
3b2c717e6a Continue refactoring inline asm code. If there is an earlyclobber output 
register, preallocate all input registers and the early clobbered output.

This fixes PR1357 and CodeGen/PowerPC/2007-04-30-InlineAsmEarlyClobber.ll

llvm-svn: 36599
 2007-04-30 21:11:17 +00:00
Evan Cheng
5039cf6382 Updates. 
llvm-svn: 36594
 2007-04-30 18:42:09 +00:00
Chris Lattner
4ac6ba02d1 refactor GetRegistersForValue to take OpInfo as an argument instead of various 
pieces of it.  No functionality change.

llvm-svn: 36592
 2007-04-30 17:29:31 +00:00
Chris Lattner
e3f7f2afcb refactor some code, no functionality change 
llvm-svn: 36590
 2007-04-30 17:16:27 +00:00
Chris Lattner
9f10fc6b4c Clean up multi-line asam string printing. Instead of printing: 
# InlineAsm Start
        subfc r3,r5,r4
                subfze r4,r3
        # InlineAsm End

print:

        # InlineAsm Start
        subfc r3,r5,r4
        subfze r4,r3
        # InlineAsm End

llvm-svn: 36589
 2007-04-30 17:00:18 +00:00
Chris Lattner
087a1aaaab generalize aggregate handling 
llvm-svn: 36568
 2007-04-29 18:58:03 +00:00
Anton Korobeynikov
cb2004f82c Implement review feedback 
llvm-svn: 36564
 2007-04-29 18:02:48 +00:00
Chris Lattner
85e1cac6b7 memory operands that have a direct operand should have their stores created 
before the copies into physregs are done.  This avoids having flag operands
skip the store, causing cycles in the dag at sched time.  This fixes infinite
loops on these tests:

test/CodeGen/Generic/2007-04-08-MultipleFrameIndices.ll for PR1308
test/CodeGen/PowerPC/2007-01-29-lbrx-asm.ll
test/CodeGen/PowerPC/2007-01-31-InlineAsmAddrMode.ll
test/CodeGen/X86/2006-07-12-InlineAsmQConstraint.ll for PR828

llvm-svn: 36547
 2007-04-28 21:12:06 +00:00
Chris Lattner
97d396d928 eliminate more redundant constraint type analysis 
llvm-svn: 36546
 2007-04-28 21:03:16 +00:00
Chris Lattner
4153538017 merge constraint type analysis stuff together. 
llvm-svn: 36545
 2007-04-28 21:01:43 +00:00
Chris Lattner
0e0d379b5d Significant refactoring of the inline asm stuff, to support future changes. 
No functionality change.

llvm-svn: 36544
 2007-04-28 20:49:53 +00:00
Anton Korobeynikov
45162c6dad Implement review feedback. Aliasees can be either GlobalValue's or 
bitcasts of them.

llvm-svn: 36537
 2007-04-28 13:45:00 +00:00
Chris Lattner
4c7178e326 memory inputs to an inline asm are required to have an address available. 
If the operand is not already an indirect operand, spill it to a constant
pool entry or a stack slot.

This fixes PR1356 and CodeGen/X86/2007-04-27-InlineAsm-IntMemInput.ll

llvm-svn: 36536
 2007-04-28 06:42:38 +00:00
Chris Lattner
0e2a4a7890 Fix CodeGen/Generic/2007-04-27-LargeMemObject.ll and 
CodeGen/Generic/2007-04-27-InlineAsm-X-Dest.ll

llvm-svn: 36534
 2007-04-28 06:08:13 +00:00
Chris Lattner
0a0983b493 Fix this to match change to InlineAsm class. 
llvm-svn: 36524
 2007-04-28 04:05:59 +00:00
Chris Lattner
51c23d862d Fix incorrect legalization of EHSELECTOR. This fixes 
CodeGen/Generic/2007-04-14-EHSelectorCrash.ll and PR1326

llvm-svn: 36510
 2007-04-27 17:12:52 +00:00
Evan Cheng
96a4c5fb05 Expand UINT_TO_FP in turns of SINT_TO_FP when UINTTOFP_* libcalls are not available. 
llvm-svn: 36501
 2007-04-27 07:33:31 +00:00
Chris Lattner
eef11c75d4 improve EH global handling, patch by Duncan Sands. 
llvm-svn: 36499
 2007-04-27 01:20:11 +00:00
Chris Lattner
92bff16acb enable Anton's shift/and switch lowering stuff! It now passes ppc bootstrap 
successfully! woohoo...

llvm-svn: 36496
 2007-04-26 21:09:43 +00:00
Anton Korobeynikov
3e0f9076d0 Fixx off-by-one bug, which prevents llvm-gcc bootstrap on ppc32 
llvm-svn: 36490
 2007-04-26 20:44:04 +00:00
Dan Gohman
bda4470e76 Fix a typo in a comment. 
llvm-svn: 36485
 2007-04-26 19:40:56 +00:00
Evan Cheng
eff332e3e1 Rename findRegisterUseOperand to findRegisterUseOperandIdx to avoid confusion. 
llvm-svn: 36483
 2007-04-26 19:00:32 +00:00
Evan Cheng
22fb2aa782 Minor bug. 
llvm-svn: 36473
 2007-04-26 08:24:22 +00:00
Evan Cheng
cfa2a787f7 Be careful when to add implicit kill / dead operands. Don't add them during / post reg-allocation. 
llvm-svn: 36458
 2007-04-26 01:40:09 +00:00
Evan Cheng
7f44e880dc Match MachineFunction::UsedPhysRegs changes. 
llvm-svn: 36452
 2007-04-25 22:13:27 +00:00
Evan Cheng
132ea465a1 Change UsedPhysRegs from array bool to BitVector to save some space. Setting / getting its states now go through MachineFunction. 
llvm-svn: 36451
 2007-04-25 22:10:09 +00:00
Evan Cheng
c3b686ff44 Clean up. 
llvm-svn: 36449
 2007-04-25 21:34:08 +00:00
Evan Cheng
e464e596a6 Data structure change to improve compile time (especially in debug mode). 
llvm-svn: 36447
 2007-04-25 19:34:00 +00:00
Evan Cheng
c713a5ea36 This was lefted out. Fixed sumarray-dbl. 
llvm-svn: 36445
 2007-04-25 18:33:21 +00:00
Anton Korobeynikov
25dc9a61cb Implement aliases. This fixes PR1017 and it's dependent bugs. CFE part 
will follow.

llvm-svn: 36435
 2007-04-25 14:27:10 +00:00
Evan Cheng
e884f9cb2a Fix for PR1306. 
- A register def / use now implicitly affects sub-register liveness but does
not affect liveness information of super-registers.
- Def of a larger register (if followed by a use later) is treated as
read/mod/write of a smaller register.

llvm-svn: 36434
 2007-04-25 07:30:23 +00:00
Evan Cheng
4f48ec6738 Clean up. 
llvm-svn: 36431
 2007-04-25 07:18:20 +00:00
Chris Lattner
ca7480e8cb support for >4G stack frames 
llvm-svn: 36425
 2007-04-25 04:30:24 +00:00
Chris Lattner
a2b590fff8 support > 4G stack objects 
llvm-svn: 36422
 2007-04-25 04:20:54 +00:00
Chris Lattner
8860742825 allow support for 64-bit stack objects 
llvm-svn: 36420
 2007-04-25 04:08:28 +00:00
Chris Lattner
64bb6c0a08 Be more careful about folding op(x, undef) when we have vector operands. 
This fixes CodeGen/X86/2007-04-24-VectorCrash.ll

llvm-svn: 36413
 2007-04-25 00:00:45 +00:00
Bill Wendling
b3b0427654 Assertion when using a 1-element vector for an add operation. Get the 
real vector type in this case.

llvm-svn: 36402
 2007-04-24 21:13:23 +00:00
Scott Michel
5a33297ae3 Use '-1U' where '-1UL' is obvious overkill, eliminating gcc warnings about 
tests always being true in the process.

llvm-svn: 36387
 2007-04-24 01:24:20 +00:00
Dale Johannesen
c878c6c2ed modify per review commentary 
llvm-svn: 36383
 2007-04-23 23:33:31 +00:00
Dale Johannesen
0b2847d8c4 make EmitAlignment work the way Chris says it should 
llvm-svn: 36368
 2007-04-23 19:58:54 +00:00
Christopher Lamb
a157874a8a PR400 phase 2. Propagate attributed load/store information through DAGs. 
llvm-svn: 36356
 2007-04-22 23:15:30 +00:00
Lauro Ramos Venancio
3b60b9546e X86 TLS: Implement review feedback. 
llvm-svn: 36318
 2007-04-21 20:56:26 +00:00
Reid Spencer
81070d52da Revert Christopher Lamb's load/store alignment changes. 
llvm-svn: 36309
 2007-04-21 18:36:27 +00:00
Christopher Lamb
b56b6a7ad7 add support for alignment attributes on load/store instructions 
llvm-svn: 36301
 2007-04-21 08:16:25 +00:00
Lauro Ramos Venancio
a6bb7b3907 Allow the lowering of ISD::GLOBAL_OFFSET_TABLE. 
llvm-svn: 36290
 2007-04-20 23:02:39 +00:00
Lauro Ramos Venancio
bc32d90b46 Implement "general dynamic", "initial exec" and "local exec" TLS models for 
X86 32 bits.

llvm-svn: 36283
 2007-04-20 21:38:10 +00:00
Evan Cheng
fbbdb92c9d VarInfo::UsedBlocks is no longer used. Remove. 
llvm-svn: 36250
 2007-04-18 05:04:38 +00:00
Chris Lattner
ea3c945817 allow SRL to simplify its operands, as it doesn't demand all bits as input. 
llvm-svn: 36245
 2007-04-18 03:06:49 +00:00
Chris Lattner
4ce8602d58 When replacing a node in SimplifyDemandedBits, if the old node used any 
single-use nodes, they will be dead soon.  Make sure to remove them before
processing other nodes.  This implements CodeGen/X86/shl_elim.ll

llvm-svn: 36244
 2007-04-18 03:05:22 +00:00
Chris Lattner
639f807048 fix a pasto 
llvm-svn: 36242
 2007-04-18 03:01:40 +00:00
Evan Cheng
1325999a14 Don't populate TryAgainList when coalescing only physical registers with virtual registers. 
llvm-svn: 36240
 2007-04-18 02:30:19 +00:00
Evan Cheng
eecfac47a8 Increment use count of new virtuals created during PHI elimination. 
llvm-svn: 36233
 2007-04-18 00:36:11 +00:00
Chris Lattner
1677782ef0 Fix a bug in my previous patch, grabbing the shift amount width from the 
wrong operand.

llvm-svn: 36223
 2007-04-17 22:53:02 +00:00
Chris Lattner
b55496c660 Fold (x << c1)>> c2 into a single shift if the bits shifted out aren't used. 
This compiles:
int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        srwi r2, r3, 1
        extsh r3, r2
        blr

on PPC, instead of:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

GCC produces:
_baz:
        srwi r10,r4,24
        insrwi r10,r3,24,0
        srawi r9,r3,24
        srawi r3,r10,9
        extsh r3,r3
        blr

This implements CodeGen/PowerPC/shl_elim.ll

llvm-svn: 36221
 2007-04-17 21:14:16 +00:00
Evan Cheng
48352d7a71 Copy coalescing change to prevent a physical register from being pin to a 
long live interval that has low usage density.
1. Change order of coalescing to join physical registers with virtual
   registers first before virtual register intervals become too long.
2. Check size and usage density to determine if it's worthwhile to join.
3. If joining is aborted, assign virtual register live interval allocation
   preference field to the physical register.
4. Register allocator should try to allocate to the preferred register
   first (if available) to create identify moves that can be eliminated.

llvm-svn: 36218
 2007-04-17 20:32:26 +00:00
Evan Cheng
c5d2df366a Add a register allocation preference field; add a method to compute size of a live interval. 
llvm-svn: 36216
 2007-04-17 20:25:11 +00:00
Evan Cheng
94e0223e55 Keep track of number of uses within the function per virtual register. 
llvm-svn: 36214
 2007-04-17 20:22:11 +00:00
Chris Lattner
9ad682ad80 SIGN_EXTEND_INREG does not demand its top bits. Give SimplifyDemandedBits 
a chance to hack on it.  This compiles:

int baz(long long a) { return (short)(((int)(a >>24)) >> 9); }

into:
_baz:
        slwi r2, r3, 8
        srwi r2, r2, 9
        extsh r3, r2
        blr

instead of:

_baz:
        srwi r2, r4, 24
        rlwimi r2, r3, 8, 0, 23
        srwi r2, r2, 9
        extsh r3, r2
        blr

This implements CodeGen/PowerPC/sign_ext_inreg1.ll

llvm-svn: 36212
 2007-04-17 19:03:21 +00:00
Reid Spencer
b640dc70f9 Fix problems in the PartSet lowering having to do with incorrect bit width. 
llvm-svn: 36180
 2007-04-16 22:21:14 +00:00
Anton Korobeynikov
f3e62a428a Removed tabs everywhere except autogenerated & external files. Add make 
target for tabs checking.

llvm-svn: 36146
 2007-04-16 18:10:23 +00:00
Chris Lattner
357a11fcbb disable switch lowering using shift/and. It still breaks ppc bootstrap for 
some reason.  :(  Will investigate.

llvm-svn: 36011
 2007-04-14 19:39:41 +00:00
Anton Korobeynikov
bdb4f560da Fix PR1325: Case range optimization was performed in the case it 
shouldn't. Also fix some "latent" bug on 64-bit platforms

llvm-svn: 35990
 2007-04-14 13:25:55 +00:00
Chris Lattner
6e71d21892 disable shift/and lowering to work around PR1325 for now. 
llvm-svn: 35985
 2007-04-14 02:26:56 +00:00
Anton Korobeynikov
5bb6590218 Fix PR1323 : we haven't updated phi nodes in good manner :) 
llvm-svn: 35963
 2007-04-13 06:53:51 +00:00
Reid Spencer
f1154e6d96 Make sure intrinsics that are lowered to functions make the function weak 
linkage so we only end up with one of them in a program. These are, after
all overloaded and templatish in nature.

llvm-svn: 35956
 2007-04-12 21:53:38 +00:00
Reid Spencer
1e53c865c2 Fix bugs in generated code for part_select and part_set so that llc doesn't 
barf when CBE is run with a program that contains these intrinsics.

llvm-svn: 35946
 2007-04-12 13:30:14 +00:00
Reid Spencer
76e9a17f61 Fix a bug in PartSet. The replacement value needs to be zext or trunc to 
the size of the value, not just zext. Also, give better names to two BBs.

llvm-svn: 35945
 2007-04-12 12:46:33 +00:00
Chris Lattner
0da8de5848 the result of an inline asm copy can be an arbitrary VT that the register 
class supports.  In the case of vectors, this means we often get the wrong
type (e.g. we get v4f32 instead of v8i16).  Make sure to convert the vector
result to the right type.  This fixes CodeGen/X86/2007-04-11-InlineAsmVectorResult.ll

llvm-svn: 35944
 2007-04-12 06:00:20 +00:00
Chris Lattner
7acaf64d70 fold noop vbitconvert instructions 
llvm-svn: 35943
 2007-04-12 05:58:43 +00:00
Chris Lattner
2f221a83ec Fix weirdness handling single element vectors. 
llvm-svn: 35941
 2007-04-12 04:44:28 +00:00
Reid Spencer
82da0eb67c For PR1284: 
Implement the "part_set" intrinsic.

llvm-svn: 35938
 2007-04-12 02:48:46 +00:00
Chris Lattner
f29ad16397 fix an infinite loop compiling ldecod, notice by JeffC. 
llvm-svn: 35910
 2007-04-11 16:51:53 +00:00
Chris Lattner
1d20292190 Fix this harder. 
llvm-svn: 35888
 2007-04-11 06:50:51 +00:00
Chris Lattner
01ebc25b36 don't create shifts by zero, fix some problems with my previous patch 
llvm-svn: 35887
 2007-04-11 06:43:25 +00:00
Chris Lattner
0289490285 Teach the codegen to turn [aez]ext (setcc) -> selectcc of 1/0, which often 
allows other simplifications.  For example, this compiles:
int isnegative(unsigned int X) {
   return !(X < 2147483648U);
}

Into this code:

x86:
        movl 4(%esp), %eax
        shrl $31, %eax
        ret
arm:
        mov r0, r0, lsr #31
        bx lr
thumb:
        lsr r0, r0, #31
        bx lr

instead of:

x86:
        cmpl $0, 4(%esp)
        sets %al
        movzbl %al, %eax
        ret

arm:
        mov r3, #0
        cmp r0, #0
        movlt r3, #1
        mov r0, r3
        bx lr

thumb:
        mov r2, #1
        mov r1, #0
        cmp r0, #0
        blt LBB1_2      @entry
LBB1_1: @entry
        cpy r2, r1
LBB1_2: @entry
        cpy r0, r2
        bx lr

Testcase here: test/CodeGen/Generic/ispositive.ll

llvm-svn: 35883
 2007-04-11 05:32:27 +00:00
Chris Lattner
3f0e49403c Codegen integer abs more efficiently using the trick from the PPC CWG. This 
improves codegen on many architectures.  Tests committed as CodeGen/*/iabs.ll

X86 Old:			X86 New:
_test:				_test:
   movl 4(%esp), %ecx		   movl 4(%esp), %eax
   movl %ecx, %eax		   movl %eax, %ecx
   negl %eax			   sarl $31, %ecx
   testl %ecx, %ecx		   addl %ecx, %eax
   cmovns %ecx, %eax		   xorl %ecx, %eax
   ret				   ret

PPC Old:			PPC New:
_test:				_test:
   cmpwi cr0, r3, -1		   srawi r2, r3, 31
   neg r2, r3			   add r3, r3, r2
   bgt cr0, LBB1_2 ;		   xor r3, r3, r2
LBB1_1: ;			   blr
   mr r3, r2
LBB1_2: ;
   blr

ARM Old:			ARM New:
_test:				_test:
   rsb r3, r0, #0		   add r3, r0, r0, asr #31
   cmp r0, #0			   eor r0, r3, r0, asr #31
   movge r3, r0			   bx lr
   mov r0, r3
   bx lr

Thumb Old:			Thumb New:
_test:				_test:
   neg r2, r0			   asr r2, r0, #31
   cmp r0, #0			   add r0, r0, r2
   bge LBB1_2			   eor r0, r2
LBB1_1: @			   bx lr
   cpy r0, r2
LBB1_2: @
   bx lr


Sparc Old:			Sparc New:
test:				test:
   save -96, %o6, %o6		   save -96, %o6, %o6
   sethi 0, %l0			   sra %i0, 31, %l0
   sub %l0, %i0, %l0		   add %i0, %l0, %l1
   subcc %i0, -1, %l1		   xor %l1, %l0, %i0
   bg .BB1_2			   restore %g0, %g0, %g0
   nop				   retl
.BB1_1:				   nop
   or %g0, %l0, %i0
.BB1_2:
   restore %g0, %g0, %g0
   retl
   nop

It also helps alpha/ia64 :)

llvm-svn: 35881
 2007-04-11 05:11:38 +00:00
Reid Spencer
2792e203c5 For PR1146: 
Put the parameter attributes in their own ParamAttr name space. Adjust the
rest of llvm as a result.

llvm-svn: 35877
 2007-04-11 02:44:20 +00:00
Chris Lattner
e2444f7ec8 apparently some people commit without building the tree, or they forget to 
commit a LOT of files.

llvm-svn: 35858
 2007-04-10 03:20:39 +00:00