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211573 Commits

Author SHA1 Message Date
Andy Wingo
4c62f39d2f [WebAssembly] call_indirect issues table number relocs
If the reference-types feature is enabled, call_indirect will explicitly
reference its corresponding function table via `TABLE_NUMBER`
relocations against a table symbol.

Also, as before, address-taken functions can also cause the function
table to be created, only with reference-types they additionally cause a
symbol table entry to be emitted.

We abuse the used-in-reloc flag on symbols to indicate which tables
should end up in the symbol table.  We do this because unfortunately
older wasm-ld will carp if it see a table symbol.

Differential Revision: https://reviews.llvm.org/D90948
2021-02-22 10:13:36 +01:00
Djordje Todorovic
e2f803118c [NFC][llvm-dwarfdump] Don't calculate unnecessary stats
Small optimization of the code -- No need to calculate any stats
for NULL nodes, and also no need to call the collectStatsForDie()
if it is the CU itself.

Differential Revision: https://reviews.llvm.org/D96871
2021-02-22 00:31:29 -08:00
Amara Emerson
584c3e72c8 [AArch64][GlobalISel] Fix <16 x s8> G_DUP regbankselect to assign source to gpr.
We can only select this type if the source is on GPR, not FPR.
2021-02-21 21:17:29 -08:00
Kazu Hirata
38cc9ea5cc [CodeGen] Use range-based for loops (NFC) 2021-02-21 19:58:07 -08:00
Kazu Hirata
64140f094e [llvm] Fix header guards (NFC)
Identified with llvm-header-guard.
2021-02-21 19:58:05 -08:00
Kazu Hirata
83ddc1026f [Analysis] Use ListSeparator (NFC) 2021-02-21 19:58:04 -08:00
Petr Hosek
0968fe7374 [InstrProfiling] Use ELF section groups for counters, data and values
__start_/__stop_ references retain C identifier name sections such as
__llvm_prf_*. Putting these into a section group disables this logic.

The ELF section group semantics ensures that group members are retained
or discarded as a unit. When a function symbol is discarded, this allows
allows linker to discard counters, data and values associated with that
function symbol as well.

Note that `noduplicates` COMDAT is lowered to zero-flag section group in
ELF. We only set this for functions that aren't already in a COMDAT and
for those that don't have available_externally linkage since we already
use regular COMDAT groups for those.

Differential Revision: https://reviews.llvm.org/D96757
2021-02-21 16:13:06 -08:00
Craig Topper
eeb855b166 [KnownBits][RISCV] Improve known bits for srem.
The result must be less than or equal to the LHS side, so any
leading zeros in the left hand side must also exist in the result.
This is stronger than the previous behavior where we only considered
the sign bit being 0.

The affected test case used the sign bit being known 0 to change
a sign extend to a zero extend pre type legalization. After type
legalization the types were promoted to i64, but we no longer
knew bit 31 was zero. This shifts are are the equivalent of an
AND with 0xffffffff or zext_inreg X, i32. This patch allows us to
see that bit 31 is zero and remove the shifts.

Reviewed By: RKSimon

Differential Revision: https://reviews.llvm.org/D97124
2021-02-21 14:48:29 -08:00
Simon Pilgrim
0606b4495b [X86] Add vector support to sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. 2021-02-21 21:51:27 +00:00
Simon Pilgrim
b7c3719b71 [X86] Replace explicit constant handling in sub(C1, xor(X, C2)) -> add(xor(X, ~C2), C1+1) fold. NFCI.
NFC cleanup before adding vector support - rely on the SelectionDAG to handle everything for us.
2021-02-21 21:40:32 +00:00
Simon Pilgrim
69e2e277dc [X86] Regenerate sub.ll test 2021-02-21 21:25:26 +00:00
Simon Pilgrim
72833ddc08 [X86] Add 'sub C1, (xor X, C1) -> add (xor X, ~C2), C1+1' tests
This is also in sub.ll but that's for a specific i686 pattern - this adds x86_64 and vector tests
2021-02-21 21:19:39 +00:00
Simon Pilgrim
14c2353c18 [X86] Add common CHECK check-prefix to sub combine tests 2021-02-21 21:10:52 +00:00
Craig Topper
43d920b6bd [SelectionDAG][RISCV] Teach ComputeNumSignBits to handle SREM.
This also removes a pattern from RISCV that is no longer needed
since the sexti32 on the LHS of the srem in the pattern implies
the result is sign extended so the sign_extend_inreg should be
removed in DAG combine now.

Reviewed By: luismarques, RKSimon

Differential Revision: https://reviews.llvm.org/D97133
2021-02-21 11:13:36 -08:00
Simon Pilgrim
19966fb2bc [X86][AVX] canonicalizeLaneShuffleWithRepeatedOps - remove unnecessary BITCASTs.
In conjunction with the 'vperm2x128(bitcast(x),bitcast(y),c) -> bitcast(vperm2x128(x,y,c))' fold in combineTargetShuffle, this should remove any unnecessary bitcasts around vperm2x128 lane shuffles.
2021-02-21 18:40:32 +00:00
madhur13490
c582e6ee1c [NFC] Remove redundant word in comment
Differential Revision: https://reviews.llvm.org/D97157
2021-02-21 18:04:20 +00:00
Nikita Popov
ce78a3156f [Loads] Add optimized FindAvailableLoadedValue() overload (NFCI)
FindAvailableLoadedValue() accepts an iterator by reference. If no
available value is found, then the iterator will either be left
at a clobbering instruction or the beginning of the basic block.
This allows using FindAvailableLoadedValue() across multiple blocks.

If this functionality is not needed, as is the case in InstCombine,
then we can use a much more efficient implementation: First try
to find an available value, and only perform clobber checks if
we actually found one. As this function only looks at a very small
number of instructions (6 by default) and usually doesn't find an
available value, this saves many expensive alias analysis queries.
2021-02-21 18:42:56 +01:00
Sanjay Patel
3d791c7666 [IR] restrict vector reduction intrinsic types
The arguments in all cases should be vectors of exactly one of integer or FP.

All of the tests currently pass the verifier because we check for any vector
type regardless of the type of reduction.
This obviously can't work if we mix up integer and FP, and based on current
LangRef text it was not intended to work for pointers either.

The pointer case from https://llvm.org/PR49215 is what led me here. That
example was avoided with 5b250a27ec.

Differential Revision: https://reviews.llvm.org/D96904
2021-02-21 12:37:00 -05:00
Nikita Popov
80c50652f7 [Loads] Extract helper frunction for available load/store (NFC)
This contains the logic for extracting an available load/store
from a given instruction, to be reused in a following patch.
2021-02-21 18:24:58 +01:00
Kristina Bessonova
84eff7b913 [ThinLTO] Fix import of multiply defined global variables
Currently, if there is a module that contains a strong definition of
a global variable and a module that has both a weak definition for
the same global and a reference to it, it may result in an undefined symbol error
while linking with ThinLTO.

It happens because:
* the strong definition become internal because it is read-only and can be imported;
* the weak definition gets replaced by a declaration because it's non-prevailing;
* the strong definition failed to be imported because the destination module
  already contains another definition of the global yet this def is non-prevailing.

The patch adds a check to computeImportForReferencedGlobals() that allows
considering a global variable for being imported even if the module contains
a definition of it in the case this def has an interposable linkage type.

Note that currently the check is based only on the linkage type
(and this seems to be enough at the moment), but it might be worth to account
the information whether the def is prevailing or not.

Reviewed By: tejohnson

Differential Revision: https://reviews.llvm.org/D95943
2021-02-21 18:34:12 +02:00
Simon Pilgrim
b2f83027f4 [DAG] Match USUBSAT patterns through zext/trunc
This patch handles usubsat patterns hidden through zext/trunc and uses the getTruncatedUSUBSAT helper to determine if the USUBSAT can be correctly performed in the truncated form:

zext(x) >= y ? x - trunc(y) : 0 --> usubsat(x,trunc(umin(y,SatLimit)))
zext(x) >  y ? x - trunc(y) : 0 --> usubsat(x,trunc(umin(y,SatLimit)))

Based on original examples:

void foo(unsigned short *p, int max, int n) {
    int i;
    unsigned m;
    for (i = 0; i < n; i++) {
        m = *--p;
        *p = (unsigned short)(m >= max ? m-max : 0);
    }
}

Differential Revision: https://reviews.llvm.org/D25987
2021-02-21 15:26:54 +00:00
Simon Pilgrim
dd799f16a2 [X86][AVX] Fold concat(extract_subvector(v0,c0), extract_subvector(v1,c1)) -> vperm2x128
Fixes regression exposed by removing bitcasts across logic-ops in D96206.

Differential Revision: https://reviews.llvm.org/D96206
2021-02-21 14:50:43 +00:00
Simon Pilgrim
1640de7ef3 [X86] Fold bitcast(logic(bitcast(X), Y)) --> logic'(X, bitcast(Y)) for int-int bitcasts
Extend the existing combine that handles bitcasting for fp-logic ops to also help remove logic ops across bitcasts to/from the same integer types.

This helps improve AVX512 predicate handling for D/Q logic ops and also allows DAGCombine's scalarizeExtractedBinop to remove some annoying gpr->simd->gpr transfers.

The concat_vectors regression in pr40891.ll will be addressed in a followup commit on this patch.

Differential Revision: https://reviews.llvm.org/D96206
2021-02-21 14:40:54 +00:00
Craig Topper
f5a3ff6669 [RISCV] Add test cases for add/sub/mul overflow intrinsics. NFC
Largely copied from AArch64/arm64-xaluo.ll
2021-02-21 00:21:20 -08:00
Kazu Hirata
5d6ed75196 [CodeGen] Use range-based for loops (NFC) 2021-02-20 21:46:02 -08:00
Kazu Hirata
ad69418507 [TableGen] Use ListSeparator (NFC) 2021-02-20 21:46:01 -08:00
Jianzhou Zhao
3bbcdc72f8 [dfsan] Comment out unused methods by D97087 temporarily 2021-02-21 03:31:19 +00:00
Petr Hosek
e5a6554cdf [InstrProfiling] Use nobits as __llvm_prf_cnts section type in ELF
This can reduce the binary size because counters will no longer occupy
space in the binary, instead they will be allocated by dynamic linker.

Differential Revision: https://reviews.llvm.org/D97110
2021-02-20 14:20:33 -08:00
Craig Topper
6a6bc85d60 [RISCV] Add another test case showing failure to use remw when the RHS has been zero extended from less than i32. NFC 2021-02-20 14:03:30 -08:00
Nikita Popov
81952c68f5 [ConstantRange] Handle wrapping ranges in min/max (PR48643)
When one of the inputs is a wrapping range, intersect with the
union of the two inputs. The union of the two inputs corresponds
to the result we would get if we treated the min/max as a simple
select.

This fixes PR48643.
2021-02-20 22:52:09 +01:00
Sanjay Patel
d173dde91f [InstCombine] fold fdiv with exp/exp2 divisor (PR49147)
Follow-up to:
D96648 / b40fde062
...for the special-case base calls.

From the earlier commit:
This is unusual in the general (non-reciprocal) case because we need
an extra instruction, but that should be better for general FP
reassociation and codegen. We conservatively check for "arcp" FMF
here as we do with existing fdiv folds, but it is not strictly
necessary to have that.
2021-02-20 16:02:58 -05:00
Sanjay Patel
bf3bc2b22b [InstCombine] add tests for fdiv of exp/exp2; NFC 2021-02-20 16:02:58 -05:00
Nikita Popov
ca3345ac4e [ConstantRange] Handle wrapping range in binaryNot()
We don't need any special handling for wrapping ranges (or empty
ranges for that matter). The sub() call will already compute a
correct and precise range.

We only need to adjust the test expectation: We're now computing
an optimal result, rather than an unsigned envelope.
2021-02-20 21:45:59 +01:00
Craig Topper
8328dce0c0 [RISCV] Add an additional remw test to rv64m-exhaustive-w-insts.ll. NFC
This adds the IR for this C code

int32_t foo(uint16_t x, int16_t y) {
  x %= y;
  return x;
}

Note the dividend is unsigned and the divisor is signed. C type
promotion rules will extend them and use a 32-bit srem and the
function returns a 32-bit result.

We fail to use remw for this case. The zero extended input has
enough sign bits, but we won't consider (i64 AssertZext X, i16) in
the sexti32 isel pattern.

We also end up with a extra shifts to zero upper bits on the result.
computeKnownBits knew the result was positive before type legalization
and allowed the SIGN_EXTEND to become ZERO_EXTEND. But after promoting
to i64 we no longer know that bit 31 (and all bits above it) should
be 0.
2021-02-20 12:20:19 -08:00
Nikita Popov
ff8774490f [ConstantRangeTest] Print detailed information on failure (NFC)
When the optimality check fails, print the inputs, the computed
range and the better range that was found. This makes it much
simpler to identify the cause of the failure.

Make sure that full ranges (which, unlikely all the other cases,
have multiple ways to construct them that all result in the same
range) only print one message by handling them separately.
2021-02-20 20:05:11 +01:00
Teresa Johnson
6eca038caa [LTO] Fix cloning of llvm*.used when splitting module
Refines the fix in 3c4c205060c9398da705eb71b63ddd8a04999de9 to only
put globals whose defs were cloned into the split regular LTO module
on the cloned llvm*.used globals. This avoids an issue where one of the
attached values was a local that was promoted in the original module
after the module was cloned. We only need to have the values defined in
the new module on those globals.

Fixes PR49251.

Differential Revision: https://reviews.llvm.org/D97013
2021-02-20 09:46:43 -08:00
Fraser Cormack
c4642ac1ba [RISCV] Support extraction of misaligned subvectors
This patch extends the support for RVV EXTRACT_SUBVECTOR to cover those
which don't align to a vector register boundary. It accomplishes this by
extracting the nearest register-sized subvector (a subregister
operation), then sliding the vector down with VSLIDEDOWN and extracting
the subvector from the first position (a COPY operation).

Since this procedure involves the use of VSCALE and multiplication, the
handling of such operations is done during lowering to simplify the
implementation and make use of DAG combining. This necessitated moving
some helper functions from RISCVISelDAGToDAG to RISCVTargetLowering.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D96959
2021-02-20 15:43:54 +00:00
Fraser Cormack
676a71a31e [RISCV] Improve register allocation around vector masks
With vector mask registers only allocatable to V0 (VMV0Regs) it is
relatively simple to generate code which uses multiple masks and naively
requires spilling.

This patch aims to improve codegen in such cases by telling LLVM it can
use VRRegs to hold masks. This will prevent spilling in many cases by
having LLVM copy to an available VR register.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D97055
2021-02-20 14:47:51 +00:00
David Zarzycki
c56e7eeef4 [lit testing] "END." not "END:" 2021-02-20 09:43:36 -05:00
Simon Pilgrim
df708ad856 [InstCombine] matchBSwapOrBitReverse - remove pattern matching early-out. NFCI.
recognizeBSwapOrBitReverseIdiom + collectBitParts have pattern matching to bail out early if a bswap/bitreverse pattern isn't possible - we should be able to rely on this instead without any notable change in compile time.

This is part of a cleanup towards letting matchBSwapOrBitReverse /recognizeBSwapOrBitReverseIdiom use 'root' instructions that aren't ORs (FSHL/FSHRs in particular which can be prematurely created).

Differential Revision: https://reviews.llvm.org/D97056
2021-02-20 13:15:34 +00:00
Fraser Cormack
aafb3719b1 [RISCV] Pre-commit test case for D97055. NFC.
This adds a test which unnecessarily spills mask registers.
2021-02-20 12:36:55 +00:00
Simon Pilgrim
7b7deefff4 [X86][SSE] Use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI.
These are auto-upgraded to the equivalent llvm variants now.
2021-02-20 12:17:46 +00:00
Simon Pilgrim
74c5a2787c [X86][SSE] vector-compare-combines.ll - use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI.
These are auto-upgraded to the equivalent llvm variants now.
2021-02-20 12:16:54 +00:00
Simon Pilgrim
c505dedb59 [X86][AVX] Remove AVX2 min/max intrinsics tests
These are now autoupgraded to the llvm equivalents and the tests already moved avx2-intrinsics-x86-upgrade.ll
2021-02-20 12:13:06 +00:00
Simon Pilgrim
ba312be916 [X86][SSE] Remove SSE41 min/max intrinsics tests
These are now autoupgraded to the llvm equivalents and the tests already moved sse41-intrinsics-x86-upgrade.ll
2021-02-20 12:11:50 +00:00
Simon Pilgrim
af2a0364eb [X86][SSE2] Remove SSE2 min/max intrinsics tests
These are now autoupgraded to the llvm equivalents and the tests already moved sse2-intrinsics-x86-upgrade.ll
2021-02-20 12:10:58 +00:00
Simon Pilgrim
7f62d50c0b [X86] KnownBits - use llvm min/max intrinsics instead of (deprecated) sse intrinsics. NFCI.
These are auto-upgraded to the equivalent llvm variants now.
2021-02-20 12:07:02 +00:00
Simon Pilgrim
7a307c4062 [DAG] foldSubToUSubSat - fold sub(a,trunc(umin(zext(a),b))) -> usubsat(a,trunc(umin(b,SatLimit)))
This moves the last custom x86 USUBSAT fold to generic DAGCombine.

Completes PR40111

Differential Revision: https://reviews.llvm.org/D96703
2021-02-20 12:02:07 +00:00
Nikita Popov
9bdd9a8130 [ConstantRangeTest] Make exhaustive testing more principled (NFC)
The current infrastructure for exhaustive ConstantRange testing is
somewhat confusing in what exactly it tests and currently cannot even
be used for operations that produce smallest-size results, rather than
signed/unsigned envelopes.

This patch makes the testing more principled by collecting the exact
set of results of an operation into a bit set and then comparing it
against the range approximation by:

 * Checking conservative correctness: All elements in the set must be
   in the range.
 * Checking optimality under a given preference function: None of the
   (slack-free) ranges that can be constructed from the set are
   preferred over the computed range.

Implemented preference functions are:

 * PreferSmallest: Smallest range regardless of signed/unsigned wrapping
   behavior. Probably what we would call "optimal" without further
   qualification.
 * PreferSmallestUnsigned/Signed: Smallest range that has no
   unsigned/signed wrapping. We use this if our calculation is precise
   only up to signed/unsigned envelope.
 * PreferSmallestNonFullUnsigned/Signed: Smallest range that has no
   unsigned/signed wrapping -- but preferring a smaller wrapping range
   over a (non-wrapping) full range. We use this if we have a fully
   precise calculation but apply a sign preference to the result
   (union/intersection). Even with a sign preference, returning a
   wrapping range is still "strictly better" than returning a full one.

This also addresses PR49273 by replacing the fragile manual range
construction logic in testBinarySetOperationExhaustive() with generic
code that isn't specialized to the particular form of ranges that set
operations can produces.

Differential Revision: https://reviews.llvm.org/D88356
2021-02-20 12:37:31 +01:00
David Zarzycki
81606a10c8 [lit] Add --xfail and --filter-out (inverse of --filter)
In semi-automated environments,  XFAILing or filtering out known regressions without actually committing changes or temporarily modifying the test suite can be quite useful.

Reviewed By: yln

Differential Revision: https://reviews.llvm.org/D96662
2021-02-20 05:43:29 -05:00