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Commit Graph

344 Commits

Author SHA1 Message Date
Bob Wilson
4cb29f6864 Convert to FileCheck.
llvm-svn: 82710
2009-09-24 20:23:02 +00:00
Evan Cheng
e9267f10c7 Fix PR5024 with a big hammer: disable the double-def assertion in the scavenger.
LiveVariables add implicit kills to correctly track partial register kills. This works well enough and is fairly accurate. But coalescer can make it impossible to maintain these markers. e.g.

        BL <ga:sss1>, %R0<kill,undef>, %S0<kill>, %R0<imp-def>, %R1<imp-def,dead>, %R2<imp-def,dead>, %R3<imp-def,dead>, %R12<imp-def,dead>, %LR<imp-def,dead>, %D0<imp-def>, ...
...
	%reg1031<def> = FLDS <cp#1>, 0, 14, %reg0, Mem:LD4[ConstantPool]
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When reg1031 and S0 are coalesced, the copy (FCPYS) will be eliminated the the implicit-kill of D0 is lost. In this case it's possible to move the marker to the FLDS. But in many cases, this is not possible. Suppose

	%reg1031<def> = FOO <cp#1>, %D0<imp-def>
...
   	%S0<def> = FCPYS %reg1031<kill>, 14, %reg0, %D0<imp-use,kill>

When FCPYS goes away, the definition of S0 is the "FOO" instruction. However, transferring the D0 implicit-kill to FOO doesn't work since it is the def of D0 itself. We need to fix this in another time by introducing a "kill" pseudo instruction to track liveness.

Disabling the assertion is not ideal, but machine verifier is doing that job now. It's important to know double-def is not a miscomputation since it means a register should be free but it's not tracked as free. It's a performance issue instead.

llvm-svn: 82677
2009-09-24 02:27:09 +00:00
Evan Cheng
863ed2677b Fix PR5024. LiveVariables physical register defs should *commit* only after all
of the defs are processed.
Also fix a implicit_def propagation bug: a implicit_def of a physical register
should be applied to uses of the sub-registers.

llvm-svn: 82616
2009-09-23 06:28:31 +00:00
Evan Cheng
97c8597450 Fix PR5024. LiveVariables::FindLastPartialDef should return a set of sub-registers that were defined by the last partial def, not just a single sub-register.
llvm-svn: 82535
2009-09-22 08:34:46 +00:00
Evan Cheng
07d521ed99 Fix a pasto. Also simplify for Bill's benefit.
llvm-svn: 82505
2009-09-22 01:48:19 +00:00
Evan Cheng
a6d602a5c1 Clean up spill weight computation. Also some changes to give loop induction
variable increment / decrement slighter high priority. 

This has major impact on some micro-benchmarks. On MultiSource/Applications
and spec tests, it's a minor win. It also reduce 256.bzip instruction count
by 8%, 55 on 164.gzip on i386 / Darwin.

llvm-svn: 82485
2009-09-21 21:12:25 +00:00
Evan Cheng
3edb8b18a5 Fix PR4986. "r1024 = insert_subreg r1024, undef, 2" cannot be turned in an implicit_def. Instead, it's an identity copy so it should be eliminated. Also make sure to update livevariable kill information.
llvm-svn: 82436
2009-09-21 04:32:32 +00:00
Bob Wilson
9bcea11785 Convert more tests to FileCheck.
llvm-svn: 81915
2009-09-15 20:58:02 +00:00
Sandeep Patel
7727a68464 Fix superreg use in ARMAsmPrinter. Approved by Anton Korobeynikov.
llvm-svn: 81878
2009-09-15 17:53:11 +00:00
Anton Korobeynikov
fa4c7562d5 Define proper subreg sets for arm - this should fix bunch of subtle problems
with subreg - superreg mapping and also fix PR4965.

llvm-svn: 81657
2009-09-13 00:59:43 +00:00
Dan Gohman
8e55f0f55b Remove an unnecessary -f.
llvm-svn: 81546
2009-09-11 18:41:06 +00:00
Dan Gohman
f2c290dfa6 Convert more tests to avoid llvm-as.
llvm-svn: 81545
2009-09-11 18:36:27 +00:00
Bob Wilson
7b39f31422 Don't swap the operands of a subtraction when trying to create a
post-decrement load/store.

llvm-svn: 81464
2009-09-10 22:09:31 +00:00
Bob Wilson
877a857b4b Fix pr4939: Change FPCCToARMCC to translate SETOLE to ARMCC::LS.
See the bug report for details.

llvm-svn: 81397
2009-09-09 23:14:54 +00:00
Dan Gohman
142428ce64 Eliminate more uses of llvm-as and llvm-dis.
llvm-svn: 81293
2009-09-09 00:09:15 +00:00
Anton Korobeynikov
2b6ef7724e Unbreak getOnesVector() / getZeroVector() to use valid ARM extended imm's.
llvm-svn: 81262
2009-09-08 22:51:43 +00:00
Anton Korobeynikov
0b3a620d60 Add NEON 'laned' operations. This fixes another bunch of gcc testsuite fails and
makes the code faster.

llvm-svn: 81220
2009-09-08 15:22:32 +00:00
Daniel Dunbar
2a64e85835 Remove stale greps.
llvm-svn: 80986
2009-09-04 05:07:52 +00:00
Bob Wilson
25410ac604 Convert tests to FileCheck.
llvm-svn: 80983
2009-09-04 04:07:19 +00:00
Bob Wilson
9e02907942 Convert a test to FileCheck.
llvm-svn: 80975
2009-09-04 00:32:31 +00:00
Evan Cheng
41e87f2f13 Reference to hidden symbols do not have to go through non-lazy pointer in non-pic mode. rdar://7187172.
llvm-svn: 80904
2009-09-03 07:04:02 +00:00
Anton Korobeynikov
7125d63acf More missed vdup patterns
llvm-svn: 80838
2009-09-02 21:21:28 +00:00
Bob Wilson
6972a16bbc Add support for generating code for vst{234}lane intrinsics.
llvm-svn: 80707
2009-09-01 18:51:56 +00:00
Bob Wilson
75b2b04e1e Fix incorrect declarations of intrinsics in this test.
llvm-svn: 80705
2009-09-01 18:50:43 +00:00
Bob Wilson
d638cc8869 Add test for vld{234}_lane instructions.
llvm-svn: 80658
2009-09-01 04:27:10 +00:00
Bob Wilson
03f5a5bfff Fix pr4843: When an instruction has multiple destination registers that are
tied to different source registers, the TwoAddressInstructionPass needs to
be smarter.  Change it to check before replacing a source register whether
that source register is tied to a different destination register, and if so,
defer handling it until a subsequent iteration.

llvm-svn: 80654
2009-09-01 04:18:40 +00:00
Jim Grosbach
4e0e9a4870 SJLJ is arm/darwin only for now. force the triple for the test
llvm-svn: 80651
2009-09-01 02:34:49 +00:00
Jim Grosbach
9a220088ac Clean up LSDA name generation and use for SJLJ exception handling. This
makes an eggregious hack somewhat more palatable. Bringing the LSDA forward
and making it a GV available for reference would be even better, but is
beyond the scope of what I'm looking to solve at this point.

Objective C++ code could generate function names that broke the previous
scheme. This fixes that.

llvm-svn: 80649
2009-09-01 01:57:56 +00:00
David Goodwin
0fc3764297 Don't mark a register live at an undef use.
llvm-svn: 80621
2009-08-31 20:47:02 +00:00
Anton Korobeynikov
17529667db Add missed pattern
llvm-svn: 80502
2009-08-30 19:06:39 +00:00
Anton Korobeynikov
a261afbf14 EXTRACT_VECTOR_ELEMENT can have result type different from element type.
Remove the assertion and generalize the code for ARM NEON stuff.

llvm-svn: 80498
2009-08-30 17:14:54 +00:00
Anton Korobeynikov
b2e6f5eed4 Do not assert on too wide splats we don't support.
llvm-svn: 80409
2009-08-29 00:08:18 +00:00
Anton Korobeynikov
9fd6082c10 Add missed extract_element pattern
llvm-svn: 80408
2009-08-28 23:41:26 +00:00
Evan Cheng
d7a07ab112 Let Darwin linker auto-synthesize stubs and lazy-pointers. This deletes a bunch of nasty code in ARM asm printer.
llvm-svn: 80404
2009-08-28 23:18:09 +00:00
Evan Cheng
2d5d3700e9 v4, v5 does not support sxtb / sxth.
llvm-svn: 80322
2009-08-28 00:31:43 +00:00
Anton Korobeynikov
cb0fdc4505 scalar_to_vector is fully legal now (implemented as subreg accesses)
llvm-svn: 80249
2009-08-27 16:04:47 +00:00
Anton Korobeynikov
e17a92c545 Ok, sometimes it's profitable to turn scalar_to_vector stuff into subreg access.
Add a testcase.

llvm-svn: 80246
2009-08-27 14:51:42 +00:00
Evan Cheng
984f8efcaa Fix PR4789. Teach eliminateFrameIndex how to handle VLDRQ and VSTRQ which cannot fold any immediate offset.
llvm-svn: 80191
2009-08-27 01:23:50 +00:00
Bob Wilson
c7d92cfb15 Convert some more Neon tests to FileCheck.
llvm-svn: 80120
2009-08-26 18:11:50 +00:00
Anton Korobeynikov
1c904039ce Expand scalar_to_vector - we don't have any isel logic for it now
llvm-svn: 80107
2009-08-26 16:26:09 +00:00
David Goodwin
047f69da86 Fixup register kills after scheduling.
llvm-svn: 80002
2009-08-25 17:03:05 +00:00
Dan Gohman
bf08e82d8e Remove obsolete -f flags.
llvm-svn: 79992
2009-08-25 15:38:29 +00:00
Dale Johannesen
add8a314dd Split test into 3.
llvm-svn: 79926
2009-08-24 17:51:19 +00:00
Eli Friedman
79615641f1 Make x86 test actually test x86 code generation. Fix the
construct on ARM, which was breaking by coincidence, and add a similar 
testcase for ARM.

llvm-svn: 79719
2009-08-22 03:13:10 +00:00
Bob Wilson
79c0af15d0 Use CHECK-NEXT to make sure we're only getting one copy of each shuffle
instruction.

llvm-svn: 79702
2009-08-22 00:13:23 +00:00
Bob Wilson
6d4400e852 Match VTRN, VZIP, and VUZP shuffles. Restore the tests for these operations,
now using shuffles instead of intrinsics.

llvm-svn: 79673
2009-08-21 20:54:19 +00:00
Bob Wilson
0da4ec0046 Add some tests for vext.16 and vext.32.
llvm-svn: 79638
2009-08-21 16:35:24 +00:00
Bob Wilson
c046b62f1a Remove Neon intrinsics for VZIP, VUZP, and VTRN. We will represent these as
vector shuffles.  Temporarily remove the tests for these operations until the
new implementation is working.

llvm-svn: 79579
2009-08-21 00:01:42 +00:00
Bob Wilson
fae9057bf0 Add support for Neon VEXT (vector extract) shuffles.
This is derived from a patch by Anton Korzh.  I modified it to recognize
the VEXT shuffles during legalization and lower them to a target-specific
DAG node.

llvm-svn: 79428
2009-08-19 17:03:43 +00:00
Bill Wendling
962adec4ee Reapply r79127. It was fixed by d0k.
llvm-svn: 79136
2009-08-15 21:21:19 +00:00