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Commit Graph

76 Commits

Author SHA1 Message Date
Nate Begeman
f2d22dbd9b Fix JIT encoding of ppc mfocrf instruction; the operands were reversed
llvm-svn: 22707
2005-08-08 20:04:52 +00:00
Nate Begeman
7259cc60c4 Support building non-PIC
Remove the LoadHiAddr pseudo-instruction.
Optimization of stores to and loads from statics.
Force JIT to use new non-PIC codepaths.

llvm-svn: 22494
2005-07-21 20:44:43 +00:00
Nate Begeman
ae843fcefe Generate mfocrf when targeting g5. Generate fsqrt/fsqrts when targetin g5.
8-byte align doubles.

llvm-svn: 22486
2005-07-20 22:42:00 +00:00
Chris Lattner
0366a913ad PPC "branch and link" instructions are branches in the PPC sense, but not
in the LLVM code generator sense (they are calls).  Don't mark them as such,
which fixes the regressions on the ppc tester last night

llvm-svn: 22065
2005-05-15 20:11:44 +00:00
Chris Lattner
e6f861f92c switch over the rest of the formats that use RC to use isDOT
llvm-svn: 21352
2005-04-19 05:21:30 +00:00
Chris Lattner
082ca8fcab Convert the XForm instrs and XSForm instruction over to use isDOT
llvm-svn: 21351
2005-04-19 05:15:18 +00:00
Chris Lattner
e6f7713f03 convert over bform and iform instructions
llvm-svn: 21349
2005-04-19 05:00:59 +00:00
Chris Lattner
3ae0832381 Convert over DForm and DSForm instructions
llvm-svn: 21348
2005-04-19 04:59:28 +00:00
Chris Lattner
4ecf523af4 Convert XLForm and XForm instructions over to use PPC64 when appropriate.
llvm-svn: 21347
2005-04-19 04:51:30 +00:00
Chris Lattner
6a2abe8591 Convert XO XS and XFX forms to use isPPC64
llvm-svn: 21346
2005-04-19 04:40:07 +00:00
Chris Lattner
3cfa7a24cb Turn PPC64 and VMX into classes that can be added to instructions instead of
bits that must be passed up the inheritance hierarchy.  Convert MForm and AForm
instructions over

llvm-svn: 21345
2005-04-19 04:32:54 +00:00
Nate Begeman
85cd65b389 Change codegen for setcc to read the bit directly out of the condition
register.  Added support in the .td file for the g5-specific variant
  of cr -> gpr moves that executes faster, but we currently don't
  generate it.

llvm-svn: 21314
2005-04-18 02:43:24 +00:00
Nate Begeman
604895b03c Implement multi-way branches through logical ops on condition registers.
This can generate considerably shorter code, reducing the size of crafty
by almost 1%.  Also fix the printing of mcrf.  The code is currently
disabled until it gets a bit more testing, but should work as-is.

llvm-svn: 21298
2005-04-14 09:45:08 +00:00
Nate Begeman
b707ec16b4 Add the necessary support to codegen condition register logical ops with
register allocated condition registers.  Make sure that the printed
  output is gas compatible.

llvm-svn: 21295
2005-04-14 03:20:38 +00:00
Nate Begeman
f96b42f1b6 Initial support for allocation condition registers
llvm-svn: 21246
2005-04-12 07:04:16 +00:00
Nate Begeman
a154deaaff Implement bitfield clears
Implement divide by negative power of two

llvm-svn: 21240
2005-04-12 00:10:02 +00:00
Chris Lattner
ee715b2abc ORo sets CR0
llvm-svn: 21227
2005-04-11 15:03:48 +00:00
Chris Lattner
7d11f40ee2 Revert the previous patch, which I didn't mean to check in.
llvm-svn: 21226
2005-04-11 15:03:41 +00:00
Chris Lattner
d925c74452 Fix a minor bug (ORo didn't mark that it set CR0).
Refactor how . instructions are handled.  In particular, instead of passing
the RC flag all the way up the inheritance hierarchy, just make a new tblgen
class 'DOT' which can be added to an instruction definition.

For example, instead of this:

-def AND  : XForm_6<31,  28, 0, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-let Defs = [CR0] in
-def ANDo : XForm_6<31,  28, 1, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
-                   "and. $rA, $rS, $rB">;

We now have this:

+def AND  : XForm_6<31,  28, 0, 0, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
                    "and $rA, $rS, $rB">;

llvm-svn: 21225
2005-04-11 15:01:39 +00:00
Nate Begeman
783fe2108e Add recording variants of ISD::AND and ISD::OR. This kills almost 1000
(1.5%) instructions in 186.crafty

llvm-svn: 21222
2005-04-11 06:34:10 +00:00
Nate Begeman
dda6155d19 Add rlwnm instruction for variable rotate
Generate rotate left/right immediate
Generate code for brcondtwoway
Use new livein/liveout functionality

llvm-svn: 21187
2005-04-09 20:09:12 +00:00
Nate Begeman
b44597771c Add support for MULHS and MULHU nodes
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

llvm-svn: 21104
2005-04-06 00:25:27 +00:00
Nate Begeman
682fd51f9c Add support for multiply-add, multiply-sub, and their negated versions
llvm-svn: 21089
2005-04-04 23:01:51 +00:00
Nate Begeman
402c04ff16 Set shift amount to Extend
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
2005-04-02 05:59:34 +00:00
Nate Begeman
d5d90ec76b Implement SetCC, fix ZERO_EXTEND_INREG
llvm-svn: 20933
2005-03-29 21:54:38 +00:00
Nate Begeman
32d1caae6d Remove fake instruction 'subc' (mnemonic for subfc).
More pattern isel updates

llvm-svn: 20902
2005-03-28 22:28:37 +00:00
Chris Lattner
5174b9cb60 Fix a problem where the PPC backend lost track of the fact that it had
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool.  This should hopefully
fix oscar from sending the PPC tester spinning out of control.

llvm-svn: 20197
2005-02-15 20:26:49 +00:00
Chris Lattner
a0561d43b2 Factor out common .td file chunks.
llvm-svn: 18982
2004-12-16 16:31:57 +00:00
Chris Lattner
1f6882a401 Fix encoding of fneg instruction
llvm-svn: 18226
2004-11-25 03:53:44 +00:00
Nate Begeman
f8b9f49dc8 Fix encoding of bctrl, and remove some unused instructions
llvm-svn: 18192
2004-11-24 00:16:37 +00:00
Chris Lattner
f50b42adc1 Fix encoding of blr and bctr
llvm-svn: 18178
2004-11-23 22:06:24 +00:00
Chris Lattner
512b1d6c2a Fix encodings
llvm-svn: 18164
2004-11-23 19:23:18 +00:00
Chris Lattner
1b163867c6 LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter
llvm-svn: 18138
2004-11-23 05:54:25 +00:00
Chris Lattner
5b68bdb2ce Comment out a couple of unused instructions.
llvm-svn: 18135
2004-11-22 23:07:01 +00:00
Misha Brukman
757502af07 Add BCTR and LWZU instruction opcodes
llvm-svn: 17851
2004-11-15 21:20:09 +00:00
Misha Brukman
58d9e43fa1 Add BA, BL, and BLA opcodes
llvm-svn: 17193
2004-10-23 20:29:24 +00:00
Misha Brukman
e4ae05e099 Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions.
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.

llvm-svn: 17182
2004-10-23 06:05:49 +00:00
Misha Brukman
5cea06807d The value of the XO field for MFLR and MFCTR is 339, not 399
llvm-svn: 17181
2004-10-23 05:38:55 +00:00
Nate Begeman
d4c970aa3d Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.

This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.

llvm-svn: 17068
2004-10-16 20:43:38 +00:00
Nate Begeman
370b1b7a9a Several fixes and enhancements to the PPC32 backend.
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr

llvm-svn: 16826
2004-10-07 22:30:03 +00:00
Nate Begeman
61d1797c03 add optimized code sequences for setcc x, 0
llvm-svn: 16478
2004-09-22 04:40:25 +00:00
Nate Begeman
ce6d62eac7 Add 64 bit divide instructions, and use them
llvm-svn: 16198
2004-09-06 18:46:59 +00:00
Nate Begeman
e816600b3e All PPC instructions are now auto-printed
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out

llvm-svn: 16163
2004-09-04 05:00:00 +00:00
Nate Begeman
3bad485eec Convert remaining X-Form and Pseudo instructions over to asm writer
llvm-svn: 16142
2004-09-02 08:13:00 +00:00
Nate Begeman
220175aa4d convert M and MD form instructions to generated asm writer
llvm-svn: 16121
2004-08-31 02:28:08 +00:00
Nate Begeman
e58512a61c Move yet more instructions over to being printed by the generated asm writer
llvm-svn: 16112
2004-08-30 02:28:06 +00:00
Nate Begeman
7792aa1f8b Convert A-Form instructions to auto-generated asm writer
llvm-svn: 16107
2004-08-29 22:45:13 +00:00
Nate Begeman
68e2dd66af Improvements to int->float cast code for PPC-64
llvm-svn: 16105
2004-08-29 22:02:43 +00:00
Nate Begeman
923af3763d Implement the following missing functionality in the PPC backend:
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts

llvm-svn: 16081
2004-08-29 08:19:32 +00:00
Nate Begeman
dd700ce5e4 Move XForm instructions over to the auto-generated asm writer
llvm-svn: 15962
2004-08-21 05:56:39 +00:00