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Commit Graph

98517 Commits

Author SHA1 Message Date
Adrian Prantl
4d7b214e27 add source in comment
llvm-svn: 197642
2013-12-19 01:41:16 +00:00
Rafael Espindola
859cb122ba Synchronize the NaCl DataLayout strings with the ones in clang.
Patch by Derek Schuff.

llvm-svn: 197640
2013-12-19 00:44:37 +00:00
Reed Kotler
660bf702a1 Make cosmetic changes as part of Mips internal post commit review of
patch r196331.

llvm-svn: 197638
2013-12-19 00:43:08 +00:00
NAKAMURA Takumi
5bd83087aa ArchiveFileDescriptorTests: Fix CMake build. Each unit test is expected to have suffix "*Tests" for lit gtest runner to seek one.
llvm-svn: 197636
2013-12-19 00:41:08 +00:00
NAKAMURA Takumi
b74598e93b ArchiveFileDescriptorTests: Resurrect part of r197600, but make it invalidated, to appease buildbots.
Please revert this several hours later ;)

llvm-svn: 197635
2013-12-19 00:41:03 +00:00
Yuchen Wu
a7b83f0a43 llvm-cov: Added -f option for function summaries.
Similar to the file summaries, the function summaries output line,
branching and call statistics. The file summaries have been moved
outside the initial loop so that all of the function summaries can be
outputted before file summaries.

Also updated test cases.

llvm-svn: 197633
2013-12-19 00:29:25 +00:00
Reed Kotler
012c0a0f79 Fix a problem with mips16 stubs when calls are transformed during
tail call optimization. Some more work may be needed for indirect
calls but this patch fixes the current regression in Prolangc++/trees.
S2 optimization as part of the general cleanup and optimization
of prolog and epilog was not saving S2 in this case and needed to.

llvm-svn: 197630
2013-12-18 23:57:48 +00:00
Andrew Trick
e73fd60399 Revert "Add -mcpu=z10 to SystemZ tests."
This reverts commit r197466.

The MachineCSE fix that required the -mcpu flag has been disabled
until more work can be done to fix downstream issues. Adding -mcpu
wasn't the right workaround anyway.

llvm-svn: 197624
2013-12-18 23:04:37 +00:00
Weiming Zhao
628bf03d65 [aarch32] fix bug 18268: Incorrect condition of vsel
Given vsel_cc, op1, op2, since vsel has no LE/LT, to generate vsel for
such selection, it needs to inverse cc and swap op1 and op2. To inverse
cc, both L/G and E bits should be flipped.

llvm-svn: 197615
2013-12-18 22:25:17 +00:00
Adrian Prantl
a16d0492a0 Debug info: Implement (rvalue) reference qualifiers for C++11 non-static
member functions. Paired commit with CFE.

rdar://problem/15356637

llvm-svn: 197613
2013-12-18 21:48:19 +00:00
Adrian Prantl
e2d61b87e3 Pull in a couple of new constants from the upcoming DWARF 5 standard.
llvm-svn: 197611
2013-12-18 21:48:14 +00:00
Adrian Prantl
789db8ecdd formatting
llvm-svn: 197610
2013-12-18 21:48:11 +00:00
Rafael Espindola
6dc5fe883a Correctly handle the degenerated triple "thumb".
Fixes a crash in llc where some parts think the target is thumb and others think
it is ARM.

llvm-svn: 197607
2013-12-18 21:29:44 +00:00
Yuchen Wu
2639825176 llvm-cov: Print coverage summary to STDOUT.
File summaries will now be optionally outputted which will give line,
branching and call coverage info. Unfortunately, clang's current
instrumentation does not give enough information to deduce function
calls, something that gcc is able to do. Thus, no calls are always
outputted to be consistent with gcov output.

Also updated tests.

llvm-svn: 197606
2013-12-18 21:12:51 +00:00
Owen Anderson
db064198c8 Revert r197600 while I sort out why it's failing on Windows.
llvm-svn: 197602
2013-12-18 19:25:51 +00:00
Owen Anderson
0fdac3c752 Add a unit test for loading an object file via a file descriptor. Patch by Pete Cooper.
llvm-svn: 197600
2013-12-18 19:20:29 +00:00
Yuchen Wu
6e8ee043cc llvm-cov: s/(.*)Executed/\1Exec/
llvm-svn: 197595
2013-12-18 18:46:25 +00:00
Yuchen Wu
fabdd3701d llvm-cov: Added -c option for branch counts.
This will cause llvm-cov to output branch counts instead of branch
probabilities. -b must be enabled.

Also updated tests.

llvm-svn: 197594
2013-12-18 18:40:15 +00:00
Jordan Rose
1d4923ba76 [CMake] Don't put every project's tblgen executable in the LLVM bin directory.
This changes Clang standalone builds so that clang-tblgen lives in
clang/build/bin instead of llvm/build/bin, and so that with the Xcode
generator it's in clang/build/bin/Debug instead of llvm/build/bin/Debug/Debug/.
Yes, really.

llvm-svn: 197590
2013-12-18 17:50:33 +00:00
Matheus Almeida
351a06901f [mips][msa] Update format of RUN lines for every MSA MC test.
1. The arch directive now appears before the cpu directive
2. Long run lines were split across multiple lines
    
No functional changes.

llvm-svn: 197588
2013-12-18 17:31:21 +00:00
Logan Chien
89e5c10f8c [arm] Rename Tag_VFP_arch to Tag_FP_arch.
According to "Addenda to ABI for ARM architecture", Tag_FP_arch is the
new name for the equivalent Tag_VFP_arch.  This commit renames
Tag_VFP_arch to Tag_FP_arch.

llvm-svn: 197587
2013-12-18 17:23:15 +00:00
NAKAMURA Takumi
811b8a4265 Revert r197380, "llvm-config: Print SYSTEM_LIBS with --libs, instead of --ldflags."
I will introduce another flag, like --system-libs, later.

llvm-svn: 197583
2013-12-18 16:21:16 +00:00
NAKAMURA Takumi
56d91c88c2 [CMake] Prune LLVM_TOOLS_BINARY_DIR in LLVMConfig.cmake, since it always points build directory.
llvm-svn: 197581
2013-12-18 15:57:58 +00:00
Rafael Espindola
9b3064d2fb Fix f64 and f128 for ppc-darwin.
This patch adds -f64:32:64 to 32 bit ppc darwin since a f64 inside a
structure are only 32 bit aligned.

The patch also drop -f128:64:128 from all ppc darwin, since f128 is
128 bit aligned.

llvm-svn: 197574
2013-12-18 15:06:25 +00:00
Rafael Espindola
e1792e72e1 One ppc32-darwin, a i64 inside a structure can have 32 bit alignment.
Thanks for Iain Sandoe for testing this with the original gcc.

Clang was already getting this right.

llvm-svn: 197572
2013-12-18 14:35:37 +00:00
Tim Northover
c9f20609f9 ARM: update comment to match reality
llvm-svn: 197570
2013-12-18 14:18:36 +00:00
Matheus Almeida
25c76494df [mips][msa] Remove unneeded triple directive in MSA MC tests.
No functional changes.

llvm-svn: 197559
2013-12-18 11:06:13 +00:00
Tobias Grosser
773292756d DiagnosticInfo: Add missing namespace
llvm-svn: 197556
2013-12-18 10:12:06 +00:00
Tim Northover
d61d401a25 ARM: force soft-float ABI for tests depending on it.
This should fix the ARM bots.

llvm-svn: 197555
2013-12-18 09:58:06 +00:00
Tim Northover
fe4e45a5b0 ARM: set default float ABI based on triple.
Clang sets the float-abi target option manually, but no longer
annotates each function with its ABI. This can lead to confusing
mistmatch between "clang -emit-llvm | llc" and normal clang
invocations.

Besides which, gnueabihf actually *is* hard-float. Defaulting to soft
was just perverse.

llvm-svn: 197554
2013-12-18 09:27:33 +00:00
Kevin Qin
99ae282f19 [AArch64 NEON]Implment loading vector constant form constant pool.
llvm-svn: 197551
2013-12-18 06:26:04 +00:00
Saleem Abdulrasool
58e7056c0b AsmParser: add support for .end directive
The .end directive indicates the end of the file.  No further instructions are
processed after a .end directive is encountered.

One potential (glaringly obvious) optimisation that could be pursued here is to
extend MCAsmParser with a DiscardRemainder method to avoid processing lexemes to
the end of the file.  It was unclear at this point if that would be worth
adding, and could easily be added in a follow on change.

Signed-off-by: Saleem Abdulrasool <compnerd@compnerd.org>
llvm-svn: 197547
2013-12-18 02:53:03 +00:00
David Blaikie
a2d4a79272 DebugInfo: Introduce new DIValue, DIETypeSignature to encode references to type units via their signatures
This simplifies type unit and type unit reference creation as well as
setting the stage for inter-type hashing across type unit boundaries.

llvm-svn: 197539
2013-12-17 23:32:35 +00:00
Rafael Espindola
6b9c798c67 Fix N32 registers and stack alignment.
This patch fixes the "n" and "S" components of the data layout for mips. Clang
already gets this right.

This will be tested in clang.

llvm-svn: 197536
2013-12-17 23:15:58 +00:00
Hal Finkel
0cc169d05b Eliminate PPC instruction decoding ambiguities
The instruction definitions in the PPC backend have a number of variants
defined for the same instruction to represent differences between 64-bit and
32-bit semantics. In order to generate a disassembler for the PPC backend, we
need to mark all but one of these as CodeGen only.

No functionality change intended; this is prep work for PPC disassembly
support.

llvm-svn: 197535
2013-12-17 23:05:18 +00:00
Hal Finkel
773f2038fd Support little-endian encodings in the FixedLenDecoderEmitter
The convention used to specify the PowerPC ISA is that bits are numbered in
reverse order (0 is the index of the high bit). To support this "little endian"
encoding convention, CodeEmitterGen will reverse the bit numberings prior to
generating the encoding tables. In order to generate a disassembler,
FixedLenDecoderEmitter needs to do the same.

This moves the bit reversal logic out of CodeEmitterGen and into CodeGenTarget
(where it can be used by both CodeEmitterGen and FixedLenDecoderEmitter). This
is prep work for disassembly support in the PPC backend (which is the only
in-tree user of this little-endian encoding support).

llvm-svn: 197532
2013-12-17 22:37:50 +00:00
Quentin Colombet
de17e8bc87 [DiagnosticPrinter] Use the appropriate method to print a Twine object in a
raw_ostream.

llvm-svn: 197531
2013-12-17 22:35:07 +00:00
Reid Kleckner
7f077ea70a MC COFF: Emit the 'b' section flag for .bss sections in GNU assembly
Without this, assembling clang's disassembly would produce an object
file with the IMAGE_SCN_CNT_INITIALIZED_DATA section characteristic
rather than the uninitialized one.  link.exe would warn when merging
comdats with different flags.

llvm-svn: 197529
2013-12-17 22:12:40 +00:00
Rafael Espindola
2b8c8dce53 On APCS, only try to align aggregates to 32 bits instead of 64.
This matches clang's behavior and since it is only a preference, it is not
an ABI issue.

llvm-svn: 197526
2013-12-17 21:36:54 +00:00
Rafael Espindola
0e6563fe28 Handle i64 first for clarity. No functionality change.
llvm-svn: 197524
2013-12-17 21:28:36 +00:00
Duncan P. N. Exon Smith
e1df9cf614 Assert that the last operand is actually EFLAGS
This is another follow-up to r197503, after a post-commit review by
Andy.

<rdar://problem/15627766>

llvm-svn: 197520
2013-12-17 20:28:21 +00:00
Andrew Trick
68ff5cf488 Disabled subregister copy coalescing during MachineCSE.
This effectively backs out r197465 but leaves some of the general
fixes in place. Not all targets are ready to handle this feature. To
enable it, some infrastructure work is needed to better handle
register class constraints.

llvm-svn: 197514
2013-12-17 19:29:36 +00:00
Quentin Colombet
67a68c0b99 Add warning capabilities in LLVM.
This reapplies r197438 and fixes the link-time circular dependency between
IR and Support. The fix consists in moving the diagnostic support into IR.

The patch adds a new LLVMContext::diagnose that can be used to communicate to
the front-end, if any, that something of interest happened.
The diagnostics are supported by a new abstraction, the DiagnosticInfo class.
The base class contains the following information:
- The kind of the report: What this is about.
- The severity of the report: How bad this is.

This patch also adds 2 classes:
- DiagnosticInfoInlineAsm: For inline asm reporting. Basically, this diagnostic
will be used to switch to the new diagnostic API for LLVMContext::emitError.
- DiagnosticStackSize: For stack size reporting. Comes as a replacement of the
hard coded warning in PEI.

This patch also features dynamic diagnostic identifiers. In other words plugins
can use this infrastructure for their own diagnostics (for more details, see
getNextAvailablePluginDiagnosticKind).

This patch introduces a new DiagnosticHandlerTy and a new DiagnosticContext in
the LLVMContext that should be set by the front-end to be able to map these
diagnostics in its own system.

http://llvm-reviews.chandlerc.com/D2376
<rdar://problem/15515174>

llvm-svn: 197508
2013-12-17 17:47:22 +00:00
Matheus Almeida
b7efcc666c [mips] Fix off by one issue when applying a fixup.
The branch offset for a R_MIPS_PC16 relocation is indeed a 16-bit signed
immediate.

llvm-svn: 197506
2013-12-17 17:10:00 +00:00
Duncan P. N. Exon Smith
8e76a18c61 Setting the CPU in the new vaargs test
Trying to fix buildbots after r197503 (test passes locally).

<rdar://problem/15627766>

llvm-svn: 197505
2013-12-17 16:20:37 +00:00
Duncan P. N. Exon Smith
85e7983ab3 Revert "Revert "Mark vastart_save_xmm_regs as changing EFLAGS""
This reverts commit r197481, recommiting r197469 with an extra fix.

The vastart_save_xmm_regs pseudo-instruction expands to a test and a
branch, so it modifies EFLAGS.  Mark it so, or else the scheduler might
place it in the middle of another test+branch.

This fixes a bug exposed by r192750, which changed the initial scheduler
to source-order as part of enabling the MI Scheduler for X86.

This re-commit changes the VASTART_SAVE_XMM_REGS custom inserter not to
try to save %flags, and adds a test that catches the bad behavior of
r197469.

<rdar://problem/15627766>

llvm-svn: 197503
2013-12-17 15:54:45 +00:00
Rafael Espindola
4a6f55789a Fix the pointer size for the PS3 datalayout.
This will be tested from clang.

llvm-svn: 197501
2013-12-17 15:29:48 +00:00
Timur Iskhodzhanov
ccda095617 Add some simple COFF files with Z7 debug info
These will later be used as tests for the dumper part of http://llvm-reviews.chandlerc.com/D2232

llvm-svn: 197499
2013-12-17 14:33:31 +00:00
Eli Bendersky
b9c2cb9c36 Fix code sample in NVPTX examples: now it compiles to PTX and runs as expected.
llvm-svn: 197498
2013-12-17 14:14:15 +00:00
Stepan Dyatkovskiy
ea2c7b6742 Fix for PR18045:
http://llvm.org/bugs/show_bug.cgi?id=18045

Short issue description:
For X86 machines with sse < sse4.1 we got failures for some
particular load/store vector sequences:

$ clang-trunk -m32 -O2 test-case.c
fatal error: error in backend: Cannot select: 0x4200920: v4i32,ch = load 0x41d6ab0, 0x4205850,
      0x41dcb10<LD16[getelementptr inbounds ([4 x i32]* @e, i32 0, i32 0)](align=4)> [ORD=82]
      [ID=58]
  0x4205850: i32 = X86ISD::Wrapper 0x41d5490 [ORD=26] [ID=43]
    0x41d5490: i32 = TargetGlobalAddress<[4 x i32]* @e> 0 [ORD=26] [ID=23]
  0x41dcb10: i32 = undef [ID=2]

The reason is that EltsFromConsecutiveLoads could emit such load instruction
both before and after legalize stage. Though this instruction is not legal for
machines with SSSE3 and lower.

The fix: In EltsFromConsecutiveLoads, if we have passed legalize stage, we
check whether nodes it emits are legal. 

P.S.: If you get failure in time from 12:00 and till 22:00 (UTC-8),
perhaps I'll slow with response, so you better reject this commit. Thanks!

llvm-svn: 197492
2013-12-17 12:07:33 +00:00