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10508 Commits

Author SHA1 Message Date
Daniel Dunbar
4f45de1b1e MC/X86/AsmParser: Give an explicit error message when we reject an instruction 
because it could have an ambiguous suffix.

llvm-svn: 110890
 2010-08-12 00:55:42 +00:00
Devang Patel
66fc7d88ae This is x86 only test. 
llvm-svn: 110887
 2010-08-12 00:17:38 +00:00
Johnny Chen
9a37d16281 Changed the format of DMBsy, DSBsy, and friends from Pseudo to MiscFrm. 
Added two test cases to arm-tests.txt.

llvm-svn: 110880
 2010-08-11 23:35:12 +00:00
Bob Wilson
3582107cf8 Move the ARM SSAT and USAT optional shift amount operand out of the 
instruction opcode.  This also fixes part of PR7792.

llvm-svn: 110875
 2010-08-11 23:10:46 +00:00
Bruno Cardoso Lopes
2051068483 Add testcases for all AVX 256-bit intrinsics added in the last couple days 
llvm-svn: 110854
 2010-08-11 21:12:09 +00:00
Bruno Cardoso Lopes
fa19084e79 Reapply r109881 using a more strict command line for llc. 
llvm-svn: 110833
 2010-08-11 17:39:23 +00:00
Jim Grosbach
401709255b fix silly typo 
llvm-svn: 110831
 2010-08-11 17:32:46 +00:00
Jim Grosbach
be1b6086b3 Add a target triple, as the runtime library invocation varies a bit by 
platform. It's apparently "bl __muldf3" on linux, for example. Since that's
not what we're checking here, it's more robust to just force a triple. We
just wwant to check that the inline FP instructions are only generated
on cpus that have them."

llvm-svn: 110830
 2010-08-11 17:31:12 +00:00
Evan Cheng
c25cd5a82e Fix test and re-enable it. 
llvm-svn: 110829
 2010-08-11 17:25:51 +00:00
Dan Gohman
afbb9c2f2e Temporarily disable some failing tests, until they can be 
properly investigated.

llvm-svn: 110825
 2010-08-11 16:36:07 +00:00
Jim Grosbach
1128a47289 cortex m4 has floating point support, but only single precision. 
llvm-svn: 110810
 2010-08-11 15:44:15 +00:00
Dan Gohman
7b88985ebd Temporarily disable some failing tests, until they can be 
properly investigated.

llvm-svn: 110808
 2010-08-11 15:09:00 +00:00
Bill Wendling
f10d5c00fc Consider this code snippet: 
float t1(int argc) {
  return (argc == 1123) ? 1.234f : 2.38213f;
}

We would generate truly awful code on ARM (those with a weak stomach should look
away):

_t1:
  movw   r1, #1123
  movs   r2, #1
  movs   r3, #0
  cmp    r0, r1
  mov.w  r0, #0
  it     eq
  moveq  r0, r2
  movs   r1, #4
  cmp    r0, #0
  it     ne
  movne  r3, r1
  adr    r0, #LCPI1_0
  ldr    r0, [r0, r3]
  bx     lr

The problem was that legalization was creating a cascade of SELECT_CC nodes, for
for the comparison of "argc == 1123" which was fed into a SELECT node for the ?:
statement which was itself converted to a SELECT_CC node. This is because the
ARM back-end doesn't have custom lowering for SELECT nodes, so it used the
default "Expand".

I added a fairly simple "LowerSELECT" to the ARM back-end. It takes care of this
testcase, but can obviously be expanded to include more cases.

Now we generate this, which looks optimal to me:

_t1:
  movw   r1, #1123
  movs   r2, #0
  cmp    r0, r1
  adr    r0, #LCPI0_0
  it     eq
  moveq  r2, #4
  ldr    r0, [r0, r2]
  bx     lr
  .align  2
LCPI0_0:
  .long   1075344593  @ float 2.382130e+00
  .long   1067316150  @ float 1.234000e+00

llvm-svn: 110799
 2010-08-11 08:43:16 +00:00
Evan Cheng
f8604b772e Report error if codegen tries to instantiate a ARM target when the cpu does support it. e.g. cortex-m* processors. 
llvm-svn: 110798
 2010-08-11 07:17:46 +00:00
Evan Cheng
273160895e Add ARM Archv6M and let it implies FeatureDB (having dmb, etc.) 
llvm-svn: 110795
 2010-08-11 06:51:54 +00:00
Daniel Dunbar
bc7c0a60da MC/ARM: Add basic support for handling predication by parsing it out of the mnemonic into a separate operand form. 
llvm-svn: 110794
 2010-08-11 06:37:20 +00:00
Evan Cheng
e5bab36c75 Add Cortex-M0 support. It's a ARMv6m device (no ARM mode) with some 32-bit 
instructions: dmb, dsb, isb, msr, and mrs.

llvm-svn: 110786
 2010-08-11 06:30:38 +00:00
Evan Cheng
5fca4ca5f9 - Add subtarget feature -mattr=+db which determine whether an ARM cpu has the 
memory and synchronization barrier dmb and dsb instructions.
- Change instruction names to something more sensible (matching name of actual
  instructions).
- Added tests for memory barrier codegen.

llvm-svn: 110785
 2010-08-11 06:22:01 +00:00
Bill Wendling
8c5ac0d30c Update test to match output of optimize compares for ARM. 
llvm-svn: 110765
 2010-08-11 01:05:02 +00:00
Dan Gohman
603e66618f When analyzing loop exit conditions combined with and and or, don't 
make any assumptions about when the two conditions will agree on when
to permit the loop to exit. This fixes PR7845.

llvm-svn: 110758
 2010-08-11 00:12:36 +00:00
Bill Wendling
37ac7cfa7d The optimize comparisons pass removes the "cmp" instruction this is checking for. 
llvm-svn: 110739
 2010-08-10 22:16:05 +00:00
Nate Begeman
36e284c2be Add test for recent instcombine vector shuffle enhancement 
llvm-svn: 110737
 2010-08-10 21:58:00 +00:00
Daniel Dunbar
eb15b8b44d tests: Don't error out if HOME isn't present in t the environment. 
llvm-svn: 110711
 2010-08-10 19:36:25 +00:00
Evan Cheng
d9a1b0d046 Re-apply r110655 with fixes. Epilogue must restore sp from fp if the function stack frame has a var-sized object. 
Also added a test case to check for the added benefit of this patch: it's optimizing away the unnecessary restore of sp from fp for some non-leaf functions.

llvm-svn: 110707
 2010-08-10 19:30:19 +00:00
Daniel Dunbar
872e84afb5 Revert r110655, "Fix ARM hasFP() semantics. It should return true whenever FP 
register is", it breaks a couple test-suite tests.

llvm-svn: 110701
 2010-08-10 18:32:02 +00:00
Daniel Dunbar
f7233103ff MC/AsmParser: Fix a bug in macro argument parsing, which was dropping 
parentheses from argument lists.

llvm-svn: 110692
 2010-08-10 17:38:52 +00:00
Jakob Stoklund Olesen
99402e857d Fix test for more architectures. Patch by Tobias Grosser. 
llvm-svn: 110685
 2010-08-10 16:48:24 +00:00
Tobias Grosser
7b96737b7f RegionInfo: Do not assert if a BB is not part of the dominance tree. 
llvm-svn: 110665
 2010-08-10 09:54:35 +00:00
Tobias Grosser
766f219db9 Fix failing testcase. 
Those look like typos to me.

llvm-svn: 110664
 2010-08-10 09:54:29 +00:00
Devang Patel
84f48b5483 Handle TAG_constant for integers. 
llvm-svn: 110656
 2010-08-10 07:11:13 +00:00
Evan Cheng
3d47dbe761 Fix ARM hasFP() semantics. It should return true whenever FP register is 
reserved, not available for general allocation. This eliminates all the
extra checks for Darwin.

This change also fixes the use of FP to access frame indices in leaf
functions and cleaned up some confusing code in epilogue emission.

llvm-svn: 110655
 2010-08-10 06:26:49 +00:00
Eli Friedman
7197d66ff1 PR7853: fix a silly mistake introduced in r101899, and add a test to make sure 
it doesn't regress again.

llvm-svn: 110597
 2010-08-09 20:49:43 +00:00
Kalle Raiskila
e2c0e66ff1 Have SPU handle halfvec stores aligned by 8 bytes. 
llvm-svn: 110576
 2010-08-09 16:33:00 +00:00
Rafael Espindola
55c3b7aeb7 XFAIL for mingw that has no plugins. 
llvm-svn: 110574
 2010-08-09 15:14:06 +00:00
Nick Lewycky
0651189df1 Reject unrepresentable pointer types in intrinsics. Fixes PR7316. 
llvm-svn: 110541
 2010-08-08 06:12:09 +00:00
Rafael Espindola
4a4e535d24 Use %shlibext instead of .so 
llvm-svn: 110529
 2010-08-08 00:55:59 +00:00
Rafael Espindola
5579525578 Move the bugpoint test passes to a plugin in preparation for having bugpoint 
use opt.

llvm-svn: 110520
 2010-08-07 21:48:09 +00:00
Dale Johannesen
23f9086dd3 Use sdmem and sse_load_f64 (etc.) for the vector 
form of CMPSD (etc.)  Matching a 128-bit memory
operand is wrong, the instruction uses only 64 bits
(same as ADDSD etc.)  8193553.

llvm-svn: 110491
 2010-08-07 00:33:42 +00:00
Stuart Hastings
b0a46bfebd Test case for r110459. Radar 8264751. Test case by Fariborz Jahanian! 
llvm-svn: 110467
 2010-08-06 19:02:24 +00:00
Dan Gohman
da3f592fb3 Implement a proper getModRefInfo for va_arg. 
llvm-svn: 110458
 2010-08-06 18:24:38 +00:00
Rafael Espindola
6d53fded19 Fix eabi calling convention when a 64 bit value shadows r3. 
Without this what was happening was:

* R3 is not marked as "used"
* ARM backend thinks it has to save it to the stack because of vaarg
* Offset computation correctly ignores it
* Offsets are wrong

llvm-svn: 110446
 2010-08-06 15:35:32 +00:00
Eric Christopher
cf17d8dfa7 Add an option to always emit realignment code for a particular module. 
llvm-svn: 110404
 2010-08-05 23:57:43 +00:00
Dan Gohman
9135b410fe Implement AccessesArguments checking in the two-callsite form 
of BasicAA::getModRefInfo. This allows BasicAA to say that two
memset calls to non-aliasing memory locations don't interfere.

llvm-svn: 110393
 2010-08-05 23:34:50 +00:00
Dan Gohman
7260387710 Fix memdep's code for reasoning about dependences between two calls. A Ref 
response from getModRefInfo is not useful here. Instead, check for identical
calls only in the NoModRef case.

Reapply r110270, and strengthen it to compensate for the memdep changes.
When both calls are readonly, there is no dependence between them.

llvm-svn: 110382
 2010-08-05 22:09:15 +00:00
Devang Patel
9801232716 Move x86 specific tests into test/CodeGen/X86. 
llvm-svn: 110372
 2010-08-05 20:25:37 +00:00
Bob Wilson
4ba3c0a5e1 Add an ARM RSCrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110361
 2010-08-05 18:59:36 +00:00
Bob Wilson
9fbaea3765 Add an ARM RSBrr instruction for disassembly only. 
Partial fix for PR7792.

llvm-svn: 110358
 2010-08-05 18:23:43 +00:00
Dan Gohman
d108d2b2f8 Move x86-specific tests out of test/Transforms/LoopStrengthReduce and 
into test/CodeGen/X86, so that they aren't run when the x86 target is
not enabled.

Fix uglygep.ll to not be x86-specific.

llvm-svn: 110343
 2010-08-05 17:04:15 +00:00
Daniel Dunbar
c93cd33f41 tests: CodeGen/X86/GC tests require X86. 
llvm-svn: 110338
 2010-08-05 15:45:33 +00:00
Daniel Dunbar
b95f7b12b6 tests: Mark MC/AsmParser tests as requiring x86 for now -- almost all of them 
rely on using a specific x86 triple to test what they want to test.

llvm-svn: 110337
 2010-08-05 15:44:15 +00:00