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Commit Graph

17097 Commits

Author SHA1 Message Date
David Greene
50efbf730f [AVX] Revert 124910 until clients are ready.
llvm-svn: 124912
2011-02-05 00:24:41 +00:00
David Greene
0b0ec3aed7 [AVX] Add some utilities to insert and extract 128-bit subvectors.
This allows us to easily support 256-bit operations that don't have
native 256-bit support.  This applies to integer operations, certain
types of shuffles and various othher things.

llvm-svn: 124910
2011-02-04 23:29:33 +00:00
Jason W Kim
10c1a81736 Teach ARM/MC/ELF to handle R_ARM_JUMP24 relocation type for conditional jumps.
(yes, this is different from R_ARM_CALL)

- Adds a new method getARMBranchTargetOpValue() which handles the
  necessary distinction between the conditional and unconditional br/bl
  needed for ARM/ELF

At least for ARM mode, the needed fixup for conditional versus unconditional
br/bl is identical, but the ARM docs and existing ARM tools expect this
reloc type...

Added a few FIXME's for future naming fixups in ARMInstrInfo.td

llvm-svn: 124895
2011-02-04 19:47:15 +00:00
Daniel Dunbar
622bb34af8 MC/AsmParser: Add support for allowing the conversion process to fail (via
custom conversion functions).

llvm-svn: 124872
2011-02-04 17:12:23 +00:00
David Greene
7de7347ee8 [AVX] Support VSINSERTF128 with more patterns and appropriate
infrastructure.  This makes lowering 256-bit vectors to 128-bit
vectors simple when 256-bit vector support is not available.

llvm-svn: 124868
2011-02-04 16:08:29 +00:00
Bob Wilson
a1584cee86 Fix 80-column violations and whitespace.
llvm-svn: 124819
2011-02-03 21:46:10 +00:00
David Greene
2753be260c [AVX] VEXTRACTF128 support. This commit includes patterns for
matching EXTRACT_SUBVECTOR to VEXTRACTF128 along with support routines
to examine and translate index values.  VINSERTF128 comes next.  With
these two in place we can begin supporting more AVX operations as
INSERT/EXTRACT can be used as a fallback when 256-bit support is not
available.

llvm-svn: 124797
2011-02-03 15:50:00 +00:00
Richard Osborne
5c655f451e Add XCore intrinsics for resource instructions.
llvm-svn: 124794
2011-02-03 13:14:25 +00:00
Rafael Espindola
5bfba89832 Fix PR9127 by reversing the operands even if they have more then one use.
Reversing the operands allows us to fold, but doesn't force us to. Also, at
this point the DAG is still being optimized, so the check for hasOneUse is not
very precise.

llvm-svn: 124773
2011-02-03 03:58:05 +00:00
Bob Wilson
6fabaaad65 Update comment to match my recent change.
llvm-svn: 124725
2011-02-02 17:29:40 +00:00
Benjamin Kramer
b739613711 SimplifyCFG: Turn switches into sub+icmp+branch if possible.
This makes the job of the later optzn passes easier, allowing the vast amount of
icmp transforms to chew on it.

We transform 840 switches in gcc.c, leading to a 16k byte shrink of the resulting
binary on i386-linux.

The testcase from README.txt now compiles into
  decl  %edi
  cmpl  $3, %edi
  sbbl  %eax, %eax
  andl  $1, %eax
  ret

llvm-svn: 124724
2011-02-02 15:56:22 +00:00
Richard Osborne
5ee859cb22 Add support for trampolines on the XCore.
llvm-svn: 124722
2011-02-02 14:57:41 +00:00
Sean Callanan
27a8820ffa Fixed a bug in the disassembler where the mandatory 0x66
prefix would be misinterpreted in some cases on 32-bit
x86 platforms.  Thanks to Olivier Meurant for identifying
the bug.

llvm-svn: 124709
2011-02-02 01:09:02 +00:00
Evan Cheng
c7ce7e2ac3 Given a pair of floating point load and store, if there are no other uses of
the load, then it may be legal to transform the load and store to integer
load and store of the same width.

This is done if the target specified the transformation as profitable. e.g.
On arm, this can transform:
vldr.32 s0, []
vstr.32 s0, []

to

ldr r12, []
str r12, []

rdar://8944252

llvm-svn: 124708
2011-02-02 01:06:55 +00:00
Bob Wilson
a233675b43 PR9081: Split up LDM instruction with deprecated use of both LR and PC.
This is completely untested but pretty straightforward, so hopefully I
got it right.

llvm-svn: 124694
2011-02-01 22:30:51 +00:00
Anton Korobeynikov
323825cee4 Fix imm printing for logical instructions.
Patch by Brian G. Lucas!

llvm-svn: 124679
2011-02-01 20:22:53 +00:00
Carl Norum
667d5dbdcb Test commit - fix a double 'should' in a comment.
llvm-svn: 124652
2011-02-01 07:38:42 +00:00
Evan Cheng
0e8c521bbd Patches to build EFI with Clang/LLVM. By Carl Norum.
llvm-svn: 124639
2011-02-01 01:14:13 +00:00
Devang Patel
97c467ee47 Keep track of incoming argument's location while emitting LiveIns.
llvm-svn: 124611
2011-01-31 21:38:14 +00:00
David Greene
0db8e64017 Fix vector sign extend to put the source and destination types in the
correct places.

llvm-svn: 124601
2011-01-31 20:39:01 +00:00
Chris Lattner
1d534245fc add a note, progress unblocked by PR8575 being fixed.
llvm-svn: 124599
2011-01-31 20:23:28 +00:00
Anton Korobeynikov
b31576ae4d Save a mapping between original and cloned constpool entries.
llvm-svn: 124570
2011-01-30 22:07:39 +00:00
Benjamin Kramer
6b3c3de09a Teach DAGCombine to fold fold (sra (trunc (sr x, c1)), c2) -> (trunc (sra x, c1+c2) when c1 equals the amount of bits that are truncated off.
This happens all the time when a smul is promoted to a larger type.

On x86-64 we now compile "int test(int x) { return x/10; }" into
  movslq  %edi, %rax
  imulq $1717986919, %rax, %rax
  movq  %rax, %rcx
  shrq  $63, %rcx
  sarq  $34, %rax <- used to be "shrq $32, %rax; sarl $2, %eax"
  addl  %ecx, %eax

This fires 96 times in gcc.c on x86-64.

llvm-svn: 124559
2011-01-30 16:38:43 +00:00
Bob Wilson
e7ac2389b2 PR9030: Fix disassembly of ARM "mov pc, lr" instruction.
Patch by Jyun-Yan You.

llvm-svn: 124492
2011-01-28 17:50:30 +00:00
Evan Cheng
2042be8132 Fix PLD encoding.
llvm-svn: 124458
2011-01-27 23:48:34 +00:00
Kevin Enderby
ce1439297b Changed llvm-mc arm target to give an error if .syntax divided is used. Since
only .syntax unified is supported.

llvm-svn: 124454
2011-01-27 23:22:36 +00:00
David Greene
1f8b96494e [AVX] Clean up the code to configure target lowering for AVX. Specify
how to lower more/new operations.  This is a prerequisite for adding
additional AVX lowering.

llvm-svn: 124447
2011-01-27 22:38:56 +00:00
Roman Divacky
991a87e2e3 Introduce virtual ParseRegister method in TargetAsmParser.
Create override of this method in X86/ARM/MBlaze.

llvm-svn: 124378
2011-01-27 17:14:22 +00:00
Eric Christopher
9c446b2711 Use the incoming VT not the VT of where we're trying to store to determine
if we can store a value. Also, the exclusion is or, not and.

Fixes rdar://8920247.

llvm-svn: 124357
2011-01-27 05:44:56 +00:00
NAKAMURA Takumi
d418ff3b1a lib/Target/X86/X86ISelDAGToDAG.cpp: __main should be WINCALL64 on Win64.
CALL64 marks %xmm* as dead.

llvm-svn: 124354
2011-01-27 03:20:19 +00:00
Bill Wendling
5913724ac2 Add support for printing out floating point values from the ARM assembly
parser. The parser will always give us a binary representation of the floating
point number.

llvm-svn: 124318
2011-01-26 20:57:43 +00:00
David Greene
5c173a307b [AVX] Add INSERT_SUBVECTOR and support it on x86. This provides a
default implementation for x86, going through the stack in a similr
fashion to how the codegen implements BUILD_VECTOR.  Eventually this
will get matched to VINSERTF128 if AVX is available.

llvm-svn: 124307
2011-01-26 19:13:22 +00:00
David Greene
93b74739e7 [AVX] Support EXTRACT_SUBVECTOR on x86. This provides a default
implementation of EXTRACT_SUBVECTOR for x86, going through the stack
in a similr fashion to how the codegen implements BUILD_VECTOR.
Eventually this will get matched to VEXTRACTF128 if AVX is available.

llvm-svn: 124292
2011-01-26 15:38:49 +00:00
Bruno Cardoso Lopes
2d6bd03b18 fix the encoding and add testcases for ARM nop, yield, wfe and wfi instructions
llvm-svn: 124288
2011-01-26 13:28:14 +00:00
Bill Wendling
a4abd1fc4b Add needed braces.
llvm-svn: 124273
2011-01-26 02:06:22 +00:00
NAKAMURA Takumi
8ace7260cc Target/X86: Tweak win64's tailcall.
llvm-svn: 124272
2011-01-26 02:04:09 +00:00
NAKAMURA Takumi
066378440a Fix whitespace.
llvm-svn: 124270
2011-01-26 02:03:37 +00:00
NAKAMURA Takumi
a3d094f248 lib/Target/X86/X86RegisterInfo.cpp: Fix whitespace.
llvm-svn: 124268
2011-01-26 01:28:06 +00:00
NAKAMURA Takumi
1557668f7b lib/Target/X86/X86RegisterInfo.cpp: Fix a typo in comment.
llvm-svn: 124267
2011-01-26 01:27:58 +00:00
Bill Wendling
69916a2e10 Revert 124230. It was causing test failures.
llvm-svn: 124233
2011-01-25 21:48:36 +00:00
Bill Wendling
80dd6f7494 The floating point value is encoded in its binary form as an Imm. Convert it
appropriately so that it prints out the decimal representation.

llvm-svn: 124230
2011-01-25 21:27:46 +00:00
Evan Cheng
8e47a6e196 Don't merge restore with tail call instruction.
llvm-svn: 124167
2011-01-25 01:28:33 +00:00
Anton Korobeynikov
964b274578 Provide correct registers for EH stuff on ARM
llvm-svn: 124151
2011-01-24 22:38:45 +00:00
Chris Lattner
9ba0a83f2b fix a missing shuffle pattern, PR9009. Patch by Artiom Myaskouvskey!
llvm-svn: 124102
2011-01-24 03:42:46 +00:00
Chris Lattner
c025bec9e1 this isn't a memset, we do convert dest[i] to one though :)
llvm-svn: 124097
2011-01-24 02:32:00 +00:00
Chris Lattner
1f9ed3b437 with recent work, we now optimize this into:
define i32 @foo(i32 %x) nounwind readnone ssp {
entry:
  %tobool = icmp eq i32 %x, 0
  %tmp5 = select i1 %tobool, i32 2, i32 1
  ret i32 %tmp5
}

llvm-svn: 124091
2011-01-24 01:12:18 +00:00
Anders Carlsson
ba7114ef4c Add a memset loop that LoopIdiomRecognize doesn't recognize.
llvm-svn: 124082
2011-01-23 20:31:00 +00:00
Rafael Espindola
47bc703c55 Initialize MCNoExecStack.
llvm-svn: 124079
2011-01-23 18:50:12 +00:00
Rafael Espindola
547873da60 Add support for the --noexecstack option.
llvm-svn: 124077
2011-01-23 17:55:27 +00:00
Ted Kremenek
880c19c032 Null initialize a few variables flagged by
clang's -Wuninitialized-experimental warning.
While these don't look like real bugs, clang's
-Wuninitialized-experimental analysis is stricter
than GCC's, and these fixes have the benefit
of being general nice cleanups.

llvm-svn: 124073
2011-01-23 17:05:06 +00:00