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Author SHA1 Message Date
Benjamin Kramer
33e41f4986 EarlyCSE does this now (and GVN always did it). 
llvm-svn: 122960
 2011-01-06 13:19:46 +00:00
Benjamin Kramer
5834b2bab8 InstCombine: If we call llvm.objectsize on a malloc call we can replace it with the size passed to malloc. 
llvm-svn: 122959
 2011-01-06 13:11:05 +00:00
Benjamin Kramer
dcff486813 Remove dead code and silence warnings. 
llvm-svn: 122957
 2011-01-06 13:01:02 +00:00
Evan Cheng
1a1771584e Use movups to lower memcpy and memset even if it's not fast (like corei7). 
The theory is it's still faster than a pair of movq / a quad of movl. This
will probably hurt older chips like P4 but should run faster on current
and future Intel processors. rdar://8817010

llvm-svn: 122955
 2011-01-06 07:58:36 +00:00
Chris Lattner
40973baa5f add a note about object size from drystone, add a poorly optimized loop from 179.art. 
llvm-svn: 122954
 2011-01-06 07:41:22 +00:00
Chris Lattner
69ff12968c add a trivial instcombine missed in Dhrystone 
llvm-svn: 122953
 2011-01-06 07:09:23 +00:00
Evan Cheng
cb39cc2164 Re-implement r122936 with proper target hooks. Now getMaxStoresPerMemcpy 
etc. takes an option OptSize. If OptSize is true, it would return
the inline limit for functions with attribute OptSize.

llvm-svn: 122952
 2011-01-06 06:52:41 +00:00
Bill Wendling
a59afdaec5 PR8919 - LLVM incorrectly generates "_alloca" as the stack probing call. That 
works only on MinGW32. On 64-bit, the function to call is "__chkstk".
Patch by KS Sreeram!

llvm-svn: 122934
 2011-01-06 00:50:34 +00:00
Bill Wendling
fae0dd1afa PR8918 - When used with MinGW64, LLVM generates a "calll __main" at the 
beginning of the "main" function. The assembler complains about the invalid
suffix for the 'call' instruction. The right instruction is "callq __main".
Patch by KS Sreeram!

llvm-svn: 122933
 2011-01-06 00:47:10 +00:00
Chris Lattner
3ef9db5cd4 fix PR8900, a shuffle miscompilation. Patch by Nadav Rotem! 
llvm-svn: 122921
 2011-01-05 22:28:46 +00:00
Chris Lattner
0caa2500c0 silence more self assignment warnings. 
llvm-svn: 122920
 2011-01-05 22:26:52 +00:00
Chris Lattner
d419fe1dfe fix some -Wself-assign warnings. 
llvm-svn: 122893
 2011-01-05 18:41:05 +00:00
Wesley Peck
b6eccbe55a Commit 122778 broke DWARF debug output when using the MBlaze backend. Fixed by overriding TargetFrameInfo::getFrameIndexOffset to take into account the new frame index information. 
llvm-svn: 122889
 2011-01-05 17:34:20 +00:00
Jakob Stoklund Olesen
76e782c385 Use the EdgeBundles analysis in X86FloatingPoint instead of recomputing CFG 
bundles in the pass.

llvm-svn: 122833
 2011-01-04 21:10:11 +00:00
Jakob Stoklund Olesen
abf8941a60 Turn the EdgeBundles class into a stand-alone machine CFG analysis pass. 
The analysis will be needed by both the greedy register allocator and the
X86FloatingPoint pass. It only needs to be computed once when the CFG doesn't
change.

This pass is very fast, usually showing up as 0.0% wall time.

llvm-svn: 122832
 2011-01-04 21:10:05 +00:00
Dale Johannesen
c7168aa6fe Eliminate a warning compiling with llvm-gcc. (IMO the 
warning is overzealous but gcc is what it is.)

llvm-svn: 122829
 2011-01-04 19:31:24 +00:00
Andrew Trick
3637733170 Fix the ARM IIC_iCMPsi itinerary and add an important assert. 
llvm-svn: 122794
 2011-01-04 00:32:57 +00:00
Bill Wendling
b402d3881e Formatting changes. No functionality change. 
llvm-svn: 122789
 2011-01-03 23:59:05 +00:00
Evan Cheng
25f7df1bce Use pushq / popq instead of subq $8, %rsp / addq $8, %rsp to adjust stack in 
prologue and epilogue if the adjustment is 8. Similarly, use pushl / popl if
the adjustment is 4 in 32-bit mode.

In the epilogue, takes care to pop to a caller-saved register that's not live
at the exit (either return or tailcall instruction).
rdar://8771137

llvm-svn: 122783
 2011-01-03 22:53:22 +00:00
Wesley Peck
d22aae0d68 Fix more stack layout issues in the MBlaze backend. 
llvm-svn: 122778
 2011-01-03 21:40:26 +00:00
Benjamin Kramer
a58b69aa9d Try to reuse the value when lowering memset. 
This allows us to compile:
  void test(char *s, int a) {
    __builtin_memset(s, a, 15);
  }
into 1 mul + 3 stores instead of 3 muls + 3 stores.

llvm-svn: 122710
 2011-01-02 19:57:05 +00:00
Oscar Fuentes
6514b0ac68 A workaround for a bug in cmake 2.8.3 diagnosed on PR 8885. 
llvm-svn: 122706
 2011-01-02 19:32:31 +00:00
Chris Lattner
222b24e2de update a bunch of entries. 
llvm-svn: 122700
 2011-01-02 18:31:38 +00:00
Chris Lattner
f669d6a901 Allow loop-idiom to run on multiple BB loops, but still only scan the loop 
header for now for memset/memcpy opportunities.  It turns out that loop-rotate
is successfully rotating loops, but *DOESN'T MERGE THE BLOCKS*, turning "for 
loops" into 2 basic block loops that loop-idiom was ignoring.

With this fix, we form many *many* more memcpy and memsets than before, including
on the "history" loops in the viterbi benchmark, which look like this:

        for (j=0; j<MAX_history; ++j) {
          history_new[i][j+1] = history[2*i][j];
        }

Transforming these loops into memcpy's speeds up the viterbi benchmark from
11.98s to 3.55s on my machine.  Woo.

llvm-svn: 122685
 2011-01-02 07:58:36 +00:00
Chris Lattner
9dadac901f a missed __builtin_object_size case. 
llvm-svn: 122676
 2011-01-01 22:57:31 +00:00
Chris Lattner
e3e3cb83a5 various updates. 
llvm-svn: 122675
 2011-01-01 22:52:11 +00:00
Rafael Espindola
55f7a5057d Add support for the 'H' modifier. 
llvm-svn: 122667
 2011-01-01 20:58:46 +00:00
Anton Korobeynikov
d37cb4cd1c Model operand restrictions of mul-like instructions on ARMv5 via 
earlyclobber stuff. This should fix PRs 2313 and 8157.

Unfortunately, no testcase, since it'd be dependent on register
assignments.

llvm-svn: 122663
 2011-01-01 20:38:38 +00:00
Duncan Sands
aaddf57af9 Revert commit 122654 at the request of Chris, who reckons that instsimplify 
is the wrong hammer for this nail, and is probably right.

llvm-svn: 122661
 2011-01-01 20:08:02 +00:00
Duncan Sands
ec8b2b4cc5 Fix a README item by having InstructionSimplify do a mild form of value 
numbering, in which it considers (for example) "%a = add i32 %x, %y" and
"%b = add i32 %x, %y" to be equal because the operands are equal and the
result of the instructions only depends on the values of the operands.
This has almost no effect (it removes 4 instructions from gcc-as-one-file),
and perhaps slows down compilation: I measured a 0.4% slowdown on the large
gcc-as-one-file testcase, but it wasn't statistically significant.

llvm-svn: 122654
 2011-01-01 16:12:09 +00:00
Che-Liang Chiou
a188cfb574 ptx: remove reg-reg addressing mode and st.const 
llvm-svn: 122653
 2011-01-01 11:58:58 +00:00
Che-Liang Chiou
995a853724 ptx: add store instruction 
llvm-svn: 122652
 2011-01-01 10:50:37 +00:00
Oscar Fuentes
a63d0dbfbf Add to the list of cmake files the object file, not the asm file. This 
is necessary for executing the custom command that runs the
assember. Fixes PR8877.

llvm-svn: 122649
 2010-12-31 20:15:37 +00:00
Nick Lewycky
5cb84ee2cf Add another non-commutable instruction that gas accepts commuted forms for. 
Fixes PR8861.

llvm-svn: 122641
 2010-12-30 22:10:49 +00:00
Che-Liang Chiou
f4aaa1b2e1 ptx: add state spaces 
llvm-svn: 122638
 2010-12-30 10:41:27 +00:00
Wesley Peck
5a551350c3 Fix stack layout error in MBlaze backend. 
llvm-svn: 122631
 2010-12-29 19:46:28 +00:00
Venkatraman Govindaraju
1f9ecea940 SPARC backend fix: correctly passing arguments through stack 
llvm-svn: 122626
 2010-12-29 05:37:15 +00:00
NAKAMURA Takumi
2160b3953b CMake: Add disabling optimization on MSVC8 and MSVC10 as workaround for some files in Target/ARM and Target/X86. 
llvm-svn: 122623
 2010-12-29 03:59:27 +00:00
Venkatraman Govindaraju
3c6418f9fc Multiple SPARC backend fixes: added Y register; updated select_cc, subx, subxcc defs/uses; 
and fixed CustomInserter.

llvm-svn: 122607
 2010-12-28 20:39:17 +00:00
Chris Lattner
8e3ff12790 add a note from llvmdev 
llvm-svn: 122603
 2010-12-28 18:45:02 +00:00
Rafael Espindola
e7e67fce10 Add support for the same encodings of the personality function that gnu as 
supports.

llvm-svn: 122577
 2010-12-27 00:36:05 +00:00
Chris Lattner
a6f2b8316f fix some sort of weird pasto 
llvm-svn: 122560
 2010-12-26 12:05:11 +00:00
Chris Lattner
eec079a470 add a note 
llvm-svn: 122559
 2010-12-26 03:53:31 +00:00
Andrew Trick
134b2a5907 Various bits of framework needed for precise machine-level selection 
DAG scheduling during isel. Most new functionality is currently
guarded by -enable-sched-cycles and -enable-sched-hazard.

Added InstrItineraryData::IssueWidth field, currently derived from
ARM itineraries, but could be initialized differently on other targets.

Added ScheduleHazardRecognizer::MaxLookAhead to indicate whether it is
active, and if so how many cycles of state it holds.

Added SchedulingPriorityQueue::HasReadyFilter to allowing gating entry
into the scheduler's available queue.

ScoreboardHazardRecognizer now accesses the ScheduleDAG in order to
get information about it's SUnits, provides RecedeCycle for bottom-up
scheduling, correctly computes scoreboard depth, tracks IssueCount, and
considers potential stall cycles when checking for hazards.

ScheduleDAGRRList now models machine cycles and hazards (under
flags). It tracks MinAvailableCycle, drives the hazard recognizer and
priority queue's ready filter, manages a new PendingQueue, properly
accounts for stall cycles, etc.

llvm-svn: 122541
 2010-12-24 05:03:26 +00:00
Andrew Trick
53f4556c64 whitespace 
llvm-svn: 122539
 2010-12-24 04:28:06 +00:00
Jim Grosbach
7fc4f99084 Use a StringSwitch<> instead of a manually constructed string matcher. 
llvm-svn: 122530
 2010-12-24 00:03:39 +00:00
Evan Cheng
ea28d16e36 Code clean up. No functionality change. 
llvm-svn: 122528
 2010-12-23 23:54:17 +00:00
Jim Grosbach
03a39130cb Remove dead patterns. 
llvm-svn: 122524
 2010-12-23 23:20:13 +00:00
Jim Grosbach
14f46d80df Recognize a few more documented register name aliases for ARM in the asm lexer. 
llvm-svn: 122523
 2010-12-23 23:19:54 +00:00
Bob Wilson
85dbc89f44 Radar 8803471: Fix expansion of ARM BCCi64 pseudo instructions. 
If the basic block containing the BCCi64 (or BCCZi64) instruction ends with
an unconditional branch, that branch needs to be deleted before appending
the expansion of the BCCi64 to the end of the block.

llvm-svn: 122521
 2010-12-23 22:45:49 +00:00
Chris Lattner
01e8c46349 Flag -> Glue, the ongoing saga 
llvm-svn: 122513
 2010-12-23 18:28:41 +00:00
Chris Lattner
b607e7deda flags -> glue for selectiondag 
llvm-svn: 122509
 2010-12-23 17:24:32 +00:00
Benjamin Kramer
0a0e2c55c4 Remove/fix invalid README entries. The well thought out strcpy function doesn't return a pointer to the end of the string. 
llvm-svn: 122496
 2010-12-23 15:32:07 +00:00
Benjamin Kramer
b21118c91b Remove some obsolete README items, add a new one off the top of my head. 
llvm-svn: 122495
 2010-12-23 15:07:02 +00:00
Jeffrey Yasskin
a199652a3e Change all self assignments X=X to (void)X, so that we can turn on a 
new gcc warning that complains on self-assignments and
self-initializations.

llvm-svn: 122458
 2010-12-23 00:58:24 +00:00
Jim Grosbach
b0e9926c33 Trailing whitespace. 
llvm-svn: 122456
 2010-12-22 23:26:02 +00:00
Benjamin Kramer
d8387aa9bd X86: Lower a select directly to a setcc_carry if possible. 
int test(unsigned long a, unsigned long b) { return -(a < b); }
compiles to
  _test:                              ## @test
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    sbbl  %eax, %eax                  ## encoding: [0x19,0xc0]
    ret                               ## encoding: [0xc3]
instead of
  _test:                              ## @test
    xorl  %ecx, %ecx                  ## encoding: [0x31,0xc9]
    cmpq  %rsi, %rdi                  ## encoding: [0x48,0x39,0xf7]
    movl  $-1, %eax                   ## encoding: [0xb8,0xff,0xff,0xff,0xff]
    cmovael %ecx, %eax                ## encoding: [0x0f,0x43,0xc1]
    ret                               ## encoding: [0xc3]

llvm-svn: 122451
 2010-12-22 23:09:28 +00:00
Che-Liang Chiou
e73ad4387e ptx: add ld instruction and test 
llvm-svn: 122398
 2010-12-22 10:38:51 +00:00
Wesley Peck
2759b7bc98 Don't generate carry bit when loading immediate values on the Microblaze. 
llvm-svn: 122385
 2010-12-22 01:29:32 +00:00
Wesley Peck
0d64db9772 Add support for some of the LLVM atomic operations to the MBlaze backend. 
llvm-svn: 122384
 2010-12-22 01:15:01 +00:00
Wesley Peck
32c95e5ef4 Modeling the carry bit in the MSR register of the MicroBlaze. 
llvm-svn: 122381
 2010-12-22 00:53:07 +00:00
Wesley Peck
fc577ca406 Fix a regression introduced into the MBlaze delay slot filler. 
llvm-svn: 122379
 2010-12-22 00:22:59 +00:00
Benjamin Kramer
369872edfc Add some x86 specific dagcombines for conditional increments. 
(add Y, (sete  X, 0)) -> cmp X, 1; adc  0, Y
(add Y, (setne X, 0)) -> cmp X, 1; sbb -1, Y
(sub (sete  X, 0), Y) -> cmp X, 1; sbb  0, Y
(sub (setne X, 0), Y) -> cmp X, 1; adc -1, Y

for
  unsigned foo(unsigned a, unsigned b) {
    if (a == 0) b++;
    return b;
  }
we now get:
  foo:
    cmpl  $1, %edi
    movl  %esi, %eax
    adcl  $0, %eax
    ret
instead of:
  foo:
    testl %edi, %edi
    sete  %al
    movzbl  %al, %eax
    addl  %esi, %eax
    ret

llvm-svn: 122364
 2010-12-21 21:41:44 +00:00
Bob Wilson
01593c55a2 Add ARM-specific DAG combining to cast i64 vector element load/stores to f64. 
Type legalization splits up i64 values into pairs of i32 values, which leads
to poor quality code when inserting or extracting i64 vector elements.
If the vector element is loaded or stored, it can be treated as an f64 value
and loaded or stored directly from a VPR register.  Use the pre-legalization
DAG combiner to cast those vector elements to f64 types so that the type
legalizer won't mess them up.  Radar 8755338.

llvm-svn: 122319
 2010-12-21 06:43:19 +00:00
Eric Christopher
72ceef0a74 Arm and thumb call instructions are also in different orders. 
Fixes rdar://8782223

llvm-svn: 122313
 2010-12-21 03:50:43 +00:00
Chris Lattner
65c5243bd6 rename MVT::Flag to MVT::Glue. "Flag" is a terrible name for 
something that just glues two nodes together, even if it is
sometimes used for flags.

llvm-svn: 122310
 2010-12-21 02:38:05 +00:00
Eric Christopher
81ae56b33c If we're not using reg+reg offset we're using reg+imm, set the opcode 
to be the one we want to use. bugpoint reduced testcase is a little large,
I'll see if I can simplify it down more.

Fixes part of rdar://8782207

llvm-svn: 122307
 2010-12-21 02:12:07 +00:00
Bill Wendling
856080c8a1 Fix a copy-pasto. When the tBR_JTr instruction was converted to using the 
tPseudoInst class, its size was changed from "special" to "2 bytes". This is
incorrect because the jump table will no longer be taken into account when
calculating branch offsets.
<rdar://problem/8782216>

llvm-svn: 122303
 2010-12-21 01:57:15 +00:00
Bill Wendling
8c7f90099b Comment cleanups. 
llvm-svn: 122302
 2010-12-21 01:54:40 +00:00
Nate Begeman
c7dfecb10e Implement feedback from Bruno on making pblendvb an x86-specific ISD node in addition to being an intrinsic, and convert 
lowering to use it.  Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing.

llvm-svn: 122277
 2010-12-20 22:04:24 +00:00
Wesley Peck
e8ec7a4d1f Teach the MBlaze disassembler to disassemble special purpose registers. 
llvm-svn: 122269
 2010-12-20 21:18:04 +00:00
Wesley Peck
af2890a051 Teach the MBlaze asm parser how to parse special purpose register names. 
llvm-svn: 122261
 2010-12-20 20:43:24 +00:00
Daniel Dunbar
5580eff1f8 Add header... 
llvm-svn: 122247
 2010-12-20 15:45:51 +00:00
Daniel Dunbar
f1deaf06a9 X86/MC/Mach-O: Split out createX86MachObjectWriter(). 
llvm-svn: 122246
 2010-12-20 15:07:39 +00:00
Chris Lattner
bee7320c3c now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results, 
the same as setcc.  Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS).  This is
a step towards finishing off PR5443.  In the testcase in that bug we now  get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbq	%rcx, %rcx
	testb	$1, %cl
	setne	%dl
	ret

instead of:

	movq	%rdi, %rax
	addq	%rsi, %rax
	movl	$0, %ecx
	adcq	$0, %rcx
	testq	%rcx, %rcx
	setne	%dl
	ret

llvm-svn: 122219
 2010-12-20 01:37:09 +00:00
Chris Lattner
2d4e17d195 We lower setb to sbb with the hope that the and will go away, when it 
doesn't, match it back to setb.

On a 64-bit version of the testcase before we'd get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	sbbb	%dl, %dl
	andb	$1, %dl
	ret

now we get:

	movq	%rdi, %rax
	addq	%rsi, %rax
	setb	%dl
	ret

llvm-svn: 122217
 2010-12-20 01:16:03 +00:00
Chris Lattner
16ea7f257f use for loop over types. 
llvm-svn: 122214
 2010-12-20 01:03:27 +00:00
Chris Lattner
8b1f76cad6 Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (which 
their carry depenedencies with MVT::Flag operands) and use clean and beautiful
EFLAGS dependences instead.

We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs
(which is what requires the previous scheduler change) and change X86 ISelLowering
to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes.

With the previous series of changes, this causes no changes in the testsuite, woo.

llvm-svn: 122213
 2010-12-20 00:59:46 +00:00
Mon P Wang
d3adab7a64 Prevents PerformShuffleCombine from creating a node with an illegal type after legalize types 
has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type.

llvm-svn: 122206
 2010-12-19 23:55:53 +00:00
Chris Lattner
297259f6f1 improve the setcc -> setcc_carry optimization to happen more 
consistently by moving it out of lowering into dag combine.

Add some missing patterns for matching away extended versions of setcc_c.

llvm-svn: 122201
 2010-12-19 22:08:31 +00:00
Chris Lattner
1f31c7fa15 simplify some code to just reuse a setcc if we can instead of 
going through the CSE maps to get it.

llvm-svn: 122196
 2010-12-19 21:23:48 +00:00
Nick Lewycky
c85935836b Add missing standard headers. Patch by Joerg Sonnenberger! 
llvm-svn: 122193
 2010-12-19 20:43:38 +00:00
Nick Lewycky
e718af6c63 Add missing std:: prefixes to some calls. C++ doesn't require that <cfoo> 
headers provide symbols outside namespace std and the LLVM coding standards
state that we should prefix all of them.

llvm-svn: 122192
 2010-12-19 20:42:43 +00:00
Chris Lattner
2d59eef5fd now that generic vector types aren't selected onto MMX operations, 
we don't need -disable-mmx anymore.

llvm-svn: 122189
 2010-12-19 20:19:20 +00:00
Chris Lattner
30438e63c8 reduce copy/paste programming with the power of for loops. 
llvm-svn: 122187
 2010-12-19 20:07:10 +00:00
Chris Lattner
29475c23d0 X86 supports i8/i16 overflow ops (except i8 multiplies), we should 
generate them.  

Now we compile:

define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp {
entry:
  %0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b)
  %cmp = extractvalue %0 %0, 1
  br i1 %cmp, label %if.then, label %if.end

into:

_X:                                     ## @X
## BB#0:                                ## %entry
	subl	$12, %esp
	movb	16(%esp), %al
	addb	20(%esp), %al
	jo	LBB0_2

Before we were generating:

_X:                                     ## @X
## BB#0:                                ## %entry
	pushl	%ebp
	movl	%esp, %ebp
	subl	$8, %esp
	movb	12(%ebp), %al
	testb	%al, %al
	setge	%cl
	movb	8(%ebp), %dl
	testb	%dl, %dl
	setge	%ah
	cmpb	%cl, %ah
	sete	%cl
	addb	%al, %dl
	testb	%dl, %dl
	setge	%al
	cmpb	%al, %ah
	setne	%al
	andb	%cl, %al
	testb	%al, %al
	jne	LBB0_2

llvm-svn: 122186
 2010-12-19 20:03:11 +00:00
Chris Lattner
3bc741a0d2 recognize an unsigned add with overflow idiom into uadd. 
This resolves a README entry and technically resolves PR4916,
but we still get poor code for the testcase in that PR because
GVN isn't CSE'ing uadd with add, filed as PR8817.

Previously we got:

_test7:                                 ## @test7
	addq	%rsi, %rdi
	cmpq	%rdi, %rsi
	movl	$42, %eax
	cmovaq	%rsi, %rax
	ret

Now we get:

_test7:                                 ## @test7
	addq	%rsi, %rdi
	movl	$42, %eax
	cmovbq	%rsi, %rax
	ret

llvm-svn: 122182
 2010-12-19 19:37:52 +00:00
Anton Korobeynikov
f49c9c02d6 Restore the behavior of frame lowering before my refactoring. 
It turns out that ppc backend has really weird interdependencies
over different hooks and all stuff is fragile wrt small changes.
This should fix PR8749

llvm-svn: 122155
 2010-12-18 19:53:14 +00:00
Rafael Espindola
7f9be9e112 Remove the MCObjectFormat class. 
llvm-svn: 122147
 2010-12-18 05:37:28 +00:00
Rafael Espindola
9a4bfd7755 Move some data to the TargetWriter. 
llvm-svn: 122134
 2010-12-18 03:27:34 +00:00
Bill Wendling
9b2ef1c9be r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr to 
ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting
misaligned references to the jump table from an ADR instruction.

There is a test case, but unfortunately it's sensitive to random code changes.

<rdar://problem/8782223>

llvm-svn: 122131
 2010-12-18 02:13:59 +00:00
Bill Wendling
2dde4e38c9 RemoveUnusedCPEntries can change things. Track it. 
llvm-svn: 122129
 2010-12-18 01:53:06 +00:00
Rafael Espindola
ba05bec626 Relax push instructions. 
llvm-svn: 122121
 2010-12-18 01:01:34 +00:00
Bob Wilson
5f9e78fe20 Rearrange some Neon multiclasses. No functional changes. 
llvm-svn: 122119
 2010-12-18 00:42:58 +00:00
Bob Wilson
776d3f73eb Fix result type of Neon floating-point comparisons against zero. 
The result vector elements are always integers.  Radar 8782191.

llvm-svn: 122112
 2010-12-18 00:04:33 +00:00
Bob Wilson
c000db3584 Add some missing entries in ARMTargetLowering::getTargetNodeName. 
llvm-svn: 122111
 2010-12-18 00:04:26 +00:00
Bill Wendling
c16f9b1ccc During local stack slot allocation, the materializeFrameBaseRegister function 
may be called. If the entry block is empty, the insertion point iterator will be
the "end()" value. Calling ->getParent() on it (among others) causes problems.

Modify materializeFrameBaseRegister to take the machine basic block and insert
the frame base register at the beginning of that block. (It's very similar to
what the code does all ready. The only difference is that it will always insert
at the beginning of the entry block instead of after a previous materialization
of the frame base register. I doubt that that matters here.)

<rdar://problem/8782198>

llvm-svn: 122104
 2010-12-17 23:09:14 +00:00
Bob Wilson
12f2b81599 Avoid report_fatal_error in ARM's PrintAsmOperand method. 
The standard error handling in AsmPrinter::EmitInlineAsm handles this much
better, so just use it.

llvm-svn: 122100
 2010-12-17 23:06:42 +00:00
Nate Begeman
ef5f3c0fa7 Add support for matching psign & plendvb to the x86 target 
Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts

llvm-svn: 122098
 2010-12-17 22:55:37 +00:00
Jim Grosbach
7ca8ed3d5d If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in with 
a partial value. rdar://8782954

llvm-svn: 122078
 2010-12-17 19:03:02 +00:00
Jim Grosbach
9017f2d179 Add bits 31-28 to the Thumb2 encoding of TBB/TBH. 
llvm-svn: 122076
 2010-12-17 18:42:56 +00:00
Jim Grosbach
e0f65aaf8d Handle 2 and 4 byte data blob fixup values for ARM. 
llvm-svn: 122075
 2010-12-17 18:39:10 +00:00
Benjamin Kramer
89db30db3a Pass StringRefs by value, for consistency. 
llvm-svn: 122074
 2010-12-17 18:19:06 +00:00
Rafael Espindola
b9ca29bc1c Stub out explicit MCELFObjectTargetWriter interface. 
llvm-svn: 122067
 2010-12-17 17:45:22 +00:00
Rafael Espindola
38e6fdfd1d Move createELFObjectWriter to its own header. 
llvm-svn: 122064
 2010-12-17 16:59:53 +00:00
Kalle Raiskila
68f221707a Don't feed 19 bit immediates to ILA. 
Patch (slightly modified) by Visa Putkinen.

llvm-svn: 122052
 2010-12-17 09:36:09 +00:00
Daniel Dunbar
eea7fd1c3e MC/ARM: Use aggressive symbol folding (important for jump tables, for example). 
llvm-svn: 122044
 2010-12-17 06:00:24 +00:00
Daniel Dunbar
6979fc1057 MC/Mach-O: On second thought, use a custom hook for enabling aggressive 
IsSymbolRefDifferenceFullyResolved, it turns out this does change behavior on
enough cases for x86-32 that I would rather wait a bit on it.
 - In practice, we will want to change this eventually because it only means we
   generate less relocations (it also eliminates the need for the horrible
   '.set' hack that Darwin requires in some places).

llvm-svn: 122042
 2010-12-17 05:50:29 +00:00
Daniel Dunbar
6d4a3e98f3 MC/Target: Remove HasScatteredSymbols target hook variable, which has been 
superceded and was effectively dead.

llvm-svn: 122024
 2010-12-17 02:06:08 +00:00
Bob Wilson
125f1a26e0 Use PairDRegs to implement ConcatVectors. No functionality change. 
llvm-svn: 122017
 2010-12-17 01:21:08 +00:00
Rafael Espindola
3ee4530406 Make pushq produce signed relocations. 
llvm-svn: 122005
 2010-12-16 22:50:01 +00:00
Wesley Peck
069e991659 Fix MBlaze backend call instructions so that arguments passed through registers 
are correctly marked as used. This removes a hack where the call instructions
marked all possible argument registers as used in the tablegen description.

llvm-svn: 121994
 2010-12-16 19:41:31 +00:00
Jim Grosbach
ce773319e4 Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974 
llvm-svn: 121990
 2010-12-16 19:11:16 +00:00
Daniel Dunbar
2277f06687 MC/Mach-O: Lift some MachObjectWriter arguments into the target specific 
interface.

llvm-svn: 121981
 2010-12-16 17:21:02 +00:00
Daniel Dunbar
5fee4f6862 MC/Mach-O: Stub out explicit MCMachObjectTargetWriter interface. 
llvm-svn: 121973
 2010-12-16 16:09:19 +00:00
Daniel Dunbar
93dc10ffcb Fix indentation (per style guide). 
llvm-svn: 121972
 2010-12-16 16:08:43 +00:00
Daniel Dunbar
636e690f58 MC/Mach-O: Move createMachObjectWriter into MCMachObjectWriter.h. 
llvm-svn: 121971
 2010-12-16 16:08:33 +00:00
Daniel Dunbar
fc14f1e5f6 MC: Move target specific fixup info descriptors to TargetAsmBackend instead of 
the MCCodeEmitter, which seems like a better organization.
 - Also, cleaned up some magic constants while in the area.

llvm-svn: 121953
 2010-12-16 03:20:06 +00:00
Daniel Dunbar
8ab9be2005 MC: Make TargetAsmBackend available to the AsmStreamer. 
- Treaty talks on the non-proliferation of MC objects broke down.

llvm-svn: 121949
 2010-12-16 03:05:59 +00:00
Matt Beaumont-Gay
9b5939da47 Delete an extra "Imm5 = ", caught by GCC's -Wsequence-point but not by Clang 
(see PR4579).

llvm-svn: 121939
 2010-12-16 01:34:26 +00:00
Bill Wendling
c22ad4d7ae Remove fixup_arm_thumb_ldst. The code was never calling the "fixup" stuff for 
it. I.e., it was always an immediate value.

llvm-svn: 121932
 2010-12-16 00:50:33 +00:00
Bill Wendling
6ce0807502 Add tSpill and tRestore to the opcodes to replace with tSTRi and tLDRi 
respectively.

It may be a bug that these opcodes are getting this far into machine code
generation.

llvm-svn: 121931
 2010-12-16 00:49:54 +00:00
Bill Wendling
448cd7f1bb Add encodings for Thumb1 Spill and Restore pseudos. 
llvm-svn: 121929
 2010-12-16 00:38:41 +00:00
Jim Grosbach
84c2b29b58 Thumb1 had two patterns for the same load-from-constant-pool instruction. 
Canonicalize on tLDRpci and remove tLDRcp.

llvm-svn: 121920
 2010-12-15 23:52:36 +00:00
Eric Christopher
339499f8f3 Don't handle -arm-long-calls in fast isel for now. 
llvm-svn: 121919
 2010-12-15 23:47:29 +00:00
Bill Wendling
63ebdf4786 If we're changing the frame register to a physical register other than SP, we 
need to use tLDRi and tSTRi instead of tLDRspi and tSTRspi respectively.

llvm-svn: 121915
 2010-12-15 23:32:27 +00:00
Bill Wendling
ed6c88ead9 Whitespace cleanups. 
llvm-svn: 121914
 2010-12-15 23:31:24 +00:00
Evan Cheng
72dca1ee17 Only rr forms of ADD*_DB are commutable. 
llvm-svn: 121908
 2010-12-15 22:57:36 +00:00
Bob Wilson
438a9a1367 Add Neon VCVT instructions for f32 <-> f16 conversions. 
Clang is now providing intrinsics for these and so we need to support them
in the backend.  Radar 8068427.

llvm-svn: 121902
 2010-12-15 22:14:12 +00:00
Wesley Peck
2a376c535e Lower the MBlaze target specific calling conventions for "interrupt_handler" 
and "save_volatiles" correctly. This completes the custom calling convention
functionality changes for the MBlaze backend that were started in 121888.

llvm-svn: 121891
 2010-12-15 20:27:28 +00:00
Wesley Peck
be7405993f Add some special purpose register definitions to the MBlaze backend and cleanup some old, unused floating point register definitions. 
llvm-svn: 121882
 2010-12-15 19:35:36 +00:00
Jim Grosbach
30e7f0d09e Tweak a few pseudo-inst pattern base classes. 
llvm-svn: 121878
 2010-12-15 19:03:16 +00:00
Jim Grosbach
8278d5692a The new t2LEApcrel* pseudo instructions need the size specified. 
rdar://8768390

llvm-svn: 121876
 2010-12-15 18:48:45 +00:00
Owen Anderson
202d654195 Implement cleanups suggested by Daniel. 
llvm-svn: 121875
 2010-12-15 18:48:27 +00:00
Bill Wendling
ab9df10ee5 Add fixups for Thumb LDR/STR instructions. 
llvm-svn: 121858
 2010-12-15 08:51:02 +00:00
Chris Lattner
63d08e3444 add another overflow idiom 
llvm-svn: 121854
 2010-12-15 07:28:58 +00:00
Chris Lattner
ec899c30d9 add a note about overflow idiom recognition. 
llvm-svn: 121853
 2010-12-15 07:25:55 +00:00
Chris Lattner
82b8cda077 add a shift/imul missed optimization 
llvm-svn: 121850
 2010-12-15 07:10:43 +00:00
Chris Lattner
d2022fee87 add a note about a SPEC hack that gcc mainline does. 
llvm-svn: 121849
 2010-12-15 06:38:24 +00:00
Bill Wendling
258739db7e Reapply r121808 now that the missing patterns have been supplied. 
llvm-svn: 121820
 2010-12-15 01:03:19 +00:00
Bill Wendling
2764f25c78 Add some missing patterns now that tLDRB and tLDRH are split into reg and 
immediate versions.

llvm-svn: 121819
 2010-12-15 00:58:57 +00:00
Bill Wendling
ad13b53237 Revert r121808 until I can fix the build. 
llvm-svn: 121815
 2010-12-15 00:04:00 +00:00
Jim Grosbach
386d8fc22c thumb adr fixup needs alignment just like the t2 version. 
llvm-svn: 121812
 2010-12-14 23:47:35 +00:00
Bill Wendling
ab3d22ba7f Comments and cleaning. 
llvm-svn: 121809
 2010-12-14 23:42:48 +00:00
Bill Wendling
2883bbb8c0 Make the ISel selections for LDR/STR the same as before the LDRr/LDRi split. In 
particular, we want

   ldr r2, [r3]

to be equivalent to

   ldr r2, [r3, #0]

and not

   ldr r2, [r3, r0]

llvm-svn: 121808
 2010-12-14 23:40:49 +00:00
Jim Grosbach
1e943cc60d Add support for MC-ized encoding of tLEApcrel and tLEApcrelJT. rdar://8755755 
llvm-svn: 121798
 2010-12-14 22:28:03 +00:00
Bill Wendling
213a3d080d Fix comment. 
llvm-svn: 121797
 2010-12-14 22:26:49 +00:00
Bill Wendling
7e589d4753 Multiclassify the LDR/STR encoding patterns. The only functionality difference 
is the addition of the FoldableAsLoad & Rematerializable flags to some of the
load instructions. ARM has these flags set for them.

llvm-svn: 121794
 2010-12-14 22:10:49 +00:00
Jim Grosbach
70721628b4 trailing whitespace 
llvm-svn: 121792
 2010-12-14 21:28:29 +00:00
Jim Grosbach
e84e95e6d2 Refactor a bit for legibility. 
llvm-svn: 121790
 2010-12-14 21:10:47 +00:00
Jim Grosbach
ef58d5968e trailing whitespace. 
llvm-svn: 121789
 2010-12-14 20:46:39 +00:00
Jim Grosbach
13d82ea2b1 Make sure to propagate the predicate operands for LEApcrel to ADR. 
llvm-svn: 121788
 2010-12-14 20:45:47 +00:00
Owen Anderson
4ce4ce2f60 Fix a small bug (typo?) in the fixup for Thumb1 CBZ/CBNZ instructions. 
llvm-svn: 121784
 2010-12-14 19:42:53 +00:00
Jakob Stoklund Olesen
d0b2397aaa Add TargetRegisterInfo::printReg() to pretty-print registers. 
llvm-svn: 121780
 2010-12-14 18:53:39 +00:00
Daniel Dunbar
3f9b9dc852 MC/ARM: Fix-up fixup offset for fixup_arm_branch target specific fixup. 
llvm-svn: 121772
 2010-12-14 17:37:16 +00:00
Jim Grosbach
88727a93a8 Trailing whitespace 
llvm-svn: 121769
 2010-12-14 16:25:15 +00:00
Bill Wendling
4fe39bae17 Use the integer scheduling intrinsic for integer loads and stores. 
llvm-svn: 121765
 2010-12-14 12:33:05 +00:00
Bill Wendling
61720b79f9 The tLDR et al instructions were emitting either a reg/reg or reg/imm 
instruction based on the t_addrmode_s# mode and what it returned. There is some
obvious badness to this. In particular, it's hard to do MC-encoding when the
instruction may change out from underneath you after the t_addrmode_s# variable
is finally resolved.

The solution is to revert a long-ago change that merged the reg/reg and reg/imm
versions. There is the addition of several new addressing modes. They no longer
have extraneous operands associated with them. I.e., if it's reg/reg we don't
have to have a dummy zero immediate tacked on to the SDNode.

There are some obvious cleanups here, which will happen shortly.

llvm-svn: 121747
 2010-12-14 03:36:38 +00:00
Evan Cheng
6a2bed92f5 bfi A, (and B, C1), C2) -> bfi A, B, C2 iff C1 & C2 == C1. rdar://8458663 
llvm-svn: 121746
 2010-12-14 03:22:07 +00:00
Owen Anderson
c84f8c23b3 Second attempt at make Thumb2 LEAs pseudos. This time, perform the lowering much later, which makes the entire 
process cleaner.

llvm-svn: 121735
 2010-12-14 00:36:49 +00:00
Bob Wilson
33e5e902b0 Remove the rest of the *_sfp Neon instruction patterns. 
Use the same COPY_TO_REGCLASS approach as for the 2-register *_sfp instructions.
This change made a big difference in the code generated for the
CodeGen/Thumb2/cross-rc-coalescing-2.ll test: The coalescer is still doing
a fine job, but some instructions that were previously moved outside the loop
are not moved now.  It's using fewer VFP registers now, which is generally
a good thing, so I think the estimates for register pressure changed and that
affected the LICM behavior.  Since that isn't obviously wrong, I've just
changed the test file.  This completes the work for Radar 8711675.

llvm-svn: 121730
 2010-12-13 23:02:37 +00:00
Bob Wilson
b189b77d9b Simplify N2VSPat, removing some unnecessary type arguments. 
llvm-svn: 121729
 2010-12-13 23:02:31 +00:00
Owen Anderson
af1dde2673 Revert r121721, which broke buildbots. 
llvm-svn: 121726
 2010-12-13 22:51:08 +00:00
Owen Anderson
c298c8ed4d Make Thumb2 LEA-like instruction into pseudos, which map down to ADR. Provide correct fixups for Thumb2 ADR, 
which is _of course_ different from ARM ADR fixups, or any other Thumb2 fixup.

llvm-svn: 121721
 2010-12-13 22:29:52 +00:00
Bob Wilson
203303291f Delete a line that I forgot to revert previously. 
llvm-svn: 121719
 2010-12-13 22:05:55 +00:00
Bob Wilson
074095ddf2 Use COPY_TO_REGCLASS instead of pseudo instructions for Neon FP patterns. 
Jakob Olesen suggested that we can avoid the need for separate pseudo
instructions here by using COPY_TO_REGCLASS in the patterns.  The pattern
gets pretty ugly but it seems to work well.  Partial fix for Radar 8711675.

llvm-svn: 121718
 2010-12-13 21:58:05 +00:00
Bob Wilson
56b41f8b81 Use pseudo instructions for 2-register Neon instructions for scalar FP. 
Partial fix for Radar 8711675.

llvm-svn: 121716
 2010-12-13 21:05:52 +00:00
Bob Wilson
9a6d75a499 Remove unused instruction class arguments. 
llvm-svn: 121715
 2010-12-13 21:05:44 +00:00
Evan Cheng
c90b20fb74 Generalize BFI isel lowering a bit. 
llvm-svn: 121714
 2010-12-13 20:32:54 +00:00
Owen Anderson
4ec912b842 In Thumb2, direct branches can be encoded as either a "short" conditional branch with a null predicate, or 
as a "long" direct branch.  While the mnemonics are the same, they encode the branch offset differently, and
the Darwin assembler appears to prefer the "long" form for direct branches.  Thus, in the name of bitwise
equivalence, provide encoding and fixup support for it.

llvm-svn: 121710
 2010-12-13 19:31:11 +00:00
Jim Grosbach
9a282f2202 Use 32-bit types for 32-bit values. 
llvm-svn: 121709
 2010-12-13 19:25:46 +00:00
Jim Grosbach
ad058bd082 Trailing whitespace. 
llvm-svn: 121708
 2010-12-13 19:18:13 +00:00
Evan Cheng
190ff7fa88 Disable auto-detection of AVX support since AVX codegen support is not ready. 
llvm-svn: 121677
 2010-12-13 04:23:53 +00:00
Chris Lattner
72f03b62a9 add a note 
llvm-svn: 121656
 2010-12-13 00:15:25 +00:00
Wesley Peck
f842b79b4b Missed some ADDI <-> ADDIK conversions in 121649. 
llvm-svn: 121652
 2010-12-12 22:53:14 +00:00
Wesley Peck
95cebfc460 MBlaze delay slot filler was not capable of using ADDK and variants to fill delay slots. This broke several test cases when 121649 was committed. This fixes the regression. 
llvm-svn: 121650
 2010-12-12 22:22:49 +00:00
Wesley Peck
38688d020c The ADD and ADDK (and all variants) instructions where flip-flopped in the MBlaze backend. This bug fix makes 64-bit math work on the MBlaze backend. 
llvm-svn: 121649
 2010-12-12 22:02:31 +00:00
Wesley Peck
7274c73974 1. Change MBlaze indirect branches to use absolute branch BRALD instead of pc relative branch BRLD. 
2. Make sure that the MBlaze stack is aligned to 4-byte boundaries.
3. Determine frame indexes that should be placed in the callers stack frame, as per the MBlaze ABI, and place them in the correct locations.

llvm-svn: 121639
 2010-12-12 20:52:31 +00:00
Benjamin Kramer
a638216447 Generalize the and-icmp-select instcombine further by allowing selects of the form 
(x & 2^n) ? 2^m+C : C

we can offset both arms by C to get the "(x & 2^n) ? 2^m : 0" form, optimize the
select to a shift and apply the offset afterwards.

llvm-svn: 121609
 2010-12-11 10:49:22 +00:00
Benjamin Kramer
5a1721f4ac Factor the (x & 2^n) ? 2^m : 0 instcombine into its own method and generalize it 
to catch cases where n != m with a shift.

llvm-svn: 121608
 2010-12-11 09:42:59 +00:00
Evan Cheng
b6773d7e1f (or (and (shl A, #shamt), mask), B) => ARMbfi B, A, ~mask where lsb(mask) == #shamt. rdar://8752056 
llvm-svn: 121606
 2010-12-11 04:11:38 +00:00
Jim Grosbach
98dcdf10c2 Add FIXME 
llvm-svn: 121598
 2010-12-10 23:41:10 +00:00
Owen Anderson
47a78db79b Attempt to get Thumb2 branch fixups working properly. 
llvm-svn: 121593
 2010-12-10 23:02:28 +00:00
Owen Anderson
8424ab65e2 Fix merge error in my last fix to Thumb2 vldr fixups. 
llvm-svn: 121588
 2010-12-10 22:53:48 +00:00
Owen Anderson
f310c92333 Fixups for Thumb2 vldr's need to have the effective PC aligned as well. 
llvm-svn: 121587
 2010-12-10 22:46:47 +00:00
Bill Wendling
7f1cea7009 The MCFixupKindInfo table needs to be in the order that the enums were 
declared. Add a note specifying this and spruce up the list a bit.

llvm-svn: 121586
 2010-12-10 22:37:19 +00:00
Owen Anderson
e85fabac75 Provide the necessary post-encoder hook for Thumb2 encodings of VMOV and friends. 
llvm-svn: 121585
 2010-12-10 22:32:08 +00:00
Bob Wilson
d30768fe3e Add float patterns for Neon vld1-lane/dup and vst1-lane operations. 
llvm-svn: 121583
 2010-12-10 22:13:32 +00:00
Bob Wilson
ae683e722f Remove unused arguments. 
llvm-svn: 121582
 2010-12-10 22:13:24 +00:00
Owen Anderson
aaf97da84b Fix encoding of Thumb1 LDRB and STRB. 
llvm-svn: 121581
 2010-12-10 22:11:13 +00:00
Jim Grosbach
d7f424dec3 Trailing whitespace. 
llvm-svn: 121580
 2010-12-10 21:57:34 +00:00
Owen Anderson
44ad90c850 Fix Thumb2 encodings of STREX and LDREX. 
llvm-svn: 121579
 2010-12-10 21:52:38 +00:00
Jim Grosbach
82dd80c956 Correct encoding of rotation immediate for Thumb2 instructions. rdar://8755999 
llvm-svn: 121525
 2010-12-10 21:24:18 +00:00
Jim Grosbach
63853d61e1 Fix encoding of 'U' bit for Thumb2 STRD/LDRD instructions. rdar://8755726 
llvm-svn: 121524
 2010-12-10 21:05:07 +00:00
Jim Grosbach
467e860805 More trivial cleanup. No need to define the EncoderMethod property type. Can 
just assign to it.

llvm-svn: 121523
 2010-12-10 20:53:44 +00:00
Jim Grosbach
5696d964ca Tidy up. 
llvm-svn: 121522
 2010-12-10 20:51:35 +00:00
Jim Grosbach
401391235f Trailing whitespace. 
llvm-svn: 121521
 2010-12-10 20:47:29 +00:00
Bob Wilson
5ff13f9d5c Fix some invalid alignments for Neon vld-dup and vld/st-lane instructions. 
Alignments smaller than the total size of the memory being loaded or stored,
unless the alignment is 8 bytes, are not allowed.  Add tests for this, too.

llvm-svn: 121506
 2010-12-10 19:37:42 +00:00
Jim Grosbach
4a414e1973 Teach isCSRestore() that ARM/Thumb2 functions will use post-modify LDR 
instructions to restore a single register rather than an LDM instruction.
rdar://8754999

llvm-svn: 121498
 2010-12-10 18:41:15 +00:00
Jim Grosbach
a378c43eae Thumb unconditional branch binary encoding. rdar://8754994 
llvm-svn: 121496
 2010-12-10 18:21:33 +00:00
Jim Grosbach
905301a7d8 Thumb conditional branch binary encodings. rdar://8745367 
llvm-svn: 121493
 2010-12-10 17:13:40 +00:00
Rafael Espindola
0e665e502d Fixed version of 121434 with no new memory leaks. 
llvm-svn: 121471
 2010-12-10 07:39:47 +00:00
Rafael Espindola
676ea9d9b4 Fix cmake build. 
llvm-svn: 121462
 2010-12-10 04:28:37 +00:00
Rafael Espindola
011e168728 Revert my previous patch to make the valgrind bots happy. 
llvm-svn: 121461
 2010-12-10 04:01:09 +00:00
NAKAMURA Takumi
e3f485b0dc lib/Target/CMakeLists.txt: Add missing lib/Target/TargetAsmInfo.cpp, following up to r121434. 
llvm-svn: 121454
 2010-12-10 02:15:24 +00:00
Kevin Enderby
a2efb1ad4e Fix the leak from r121401 of the Operands erased in the list but not deleted. 
llvm-svn: 121450
 2010-12-10 01:41:56 +00:00
Nate Begeman
8c00ecd290 Add some missing predicates. 
llvm-svn: 121445
 2010-12-10 00:54:26 +00:00
Nate Begeman
cb6d1c8193 Formalize the notion that AVX and SSE are non-overlapping extensions from the compiler's point of view. Per email discussion, we either want to always use VEX-prefixed instructions or never use them, and are taking "HasAVX" to mean "Always use VEX". Passing -mattr=-avx,+sse42 should serve to restore legacy SSE support when desirable. 
llvm-svn: 121439
 2010-12-10 00:26:57 +00:00
Rafael Espindola
03ad1e8f1f Initial support for the cfi directives. This is just enough to get 
f:
        .cfi_startproc
        nop
        .cfi_endproc

assembled (on ELF).

llvm-svn: 121434
 2010-12-09 23:48:29 +00:00
Bill Wendling
f8eaf8a243 Thumb ldr reg+imm offsets were encoded incorrectly. The scaling factor of the 
t_addrmode_s# address modes is used for ASM printing, not for encoding.
<rdar://problem/8745375>

llvm-svn: 121417
 2010-12-09 21:49:07 +00:00
Nate Begeman
4a62a3e229 Add support for AVX to materialize +0.0 when doing scalar FP. 
llvm-svn: 121415
 2010-12-09 21:43:51 +00:00
Owen Anderson
4be3b6db5c Use the new IsAligned fixup flag to improve fixup encodings for Thumb2 branches. This is still not perfect, 
but it gets many more of them correct than it did previously.

llvm-svn: 121414
 2010-12-09 21:34:47 +00:00
Owen Anderson
a8ac35b468 Fix an issue in some Thumb fixups, where the effective PC address needs to be 4-byte aligned when calculating 
the offset.  Add a new fixup flag to represent this, and use it for the one fixups that I have a testcase for needing
this.  It's quite likely that the other Thumb fixups will need this too, and to have their fixup encoding logic
adjusted accordingly.

llvm-svn: 121408
 2010-12-09 20:27:52 +00:00
Jim Grosbach
61fe7b9ee5 Rename CB/CBZ specific fixup accordingly. 
llvm-svn: 121404
 2010-12-09 19:50:12 +00:00
Kevin Enderby
55cb19813e Add support for parsing ARM arithmetic instructions that update or don't update 
the condition codes.  Where the ones that do have an 's' suffix and the ones
that don't don't have the suffix.  The trick is if MatchInstructionImpl() fails
we try again after adding a CCOut operand with the correct value and removing
the 's' if present.  Four simple test cases added for now, lots more to come.

llvm-svn: 121401
 2010-12-09 19:19:43 +00:00
Jim Grosbach
9b3730fc77 Rename the encoder method for t_cbtarget to match. 
llvm-svn: 121399
 2010-12-09 19:04:53 +00:00
Jim Grosbach
57d420438a Thumb needs a few different encoding schemes for branch targets. Rename 
t_brtarget to be more specific.

llvm-svn: 121398
 2010-12-09 19:01:46 +00:00
Jim Grosbach
8bc33cc6e5 ARM stm/ldm instructions require more than one register in the register list. 
Otherwise, a plain str/ldr should be used instead. Make sure we account for
that in prologue/epilogue code generation.
rdar://8745460

llvm-svn: 121391
 2010-12-09 18:31:13 +00:00
Bruno Cardoso Lopes
93e5c2fb64 Add ROTR and ROTRV mips32 instructions. Patch by Akira Hatanaka 
llvm-svn: 121377
 2010-12-09 17:32:30 +00:00
Bruno Cardoso Lopes
0f5478218e Fix delay slot filler for non mips1 targets. Patch by Akira Hatanaka 
llvm-svn: 121376
 2010-12-09 17:31:11 +00:00
Kalle Raiskila
18da80f675 Dont' feed ILA two inputs - it takes just one. 
llvm-svn: 121372
 2010-12-09 16:17:31 +00:00
Jim Grosbach
4ad6abd006 tidy up. 
llvm-svn: 121371
 2010-12-09 16:15:41 +00:00
Jim Grosbach
9adf657f1a 80 columns. 
llvm-svn: 121370
 2010-12-09 16:14:46 +00:00
Eric Christopher
0e40452eb0 Rewrite the darwin tlv support to use a chain and return to copying 
the output to the correct register. Fixes a hidden problem uncovered
by the last patch where we'd try to DAG combine our MVT::Other node
oddly.

llvm-svn: 121358
 2010-12-09 06:25:53 +00:00
Wesley Peck
33ba317cf6 Reworking the stack layout generated by the MBlaze backend. 
llvm-svn: 121355
 2010-12-09 03:42:04 +00:00
Owen Anderson
96545f21b9 Fix encoding of the immediate operands on post-indexed LDR and friends. 
llvm-svn: 121354
 2010-12-09 02:56:12 +00:00
Eric Christopher
ea350b4c4b Fix up some comments. 
llvm-svn: 121351
 2010-12-09 01:57:45 +00:00
Owen Anderson
767a95816d Fix Thumb2 fixups for ldr. 
llvm-svn: 121350
 2010-12-09 01:51:07 +00:00
Jim Grosbach
5658d982b4 Add a textual message to the assert. 
llvm-svn: 121349
 2010-12-09 01:23:51 +00:00
Jim Grosbach
da9353523f Add a sanity check assert() for t2ADD/SUBrSPi instructions that they really are 
referencing the stack pointer as they say they are.

llvm-svn: 121347
 2010-12-09 01:22:19 +00:00
Jim Grosbach
fb71e10e93 When using multiple instructions to reference a frame index, make sure to 
update the opcode when necessary as well as the source register.

llvm-svn: 121346
 2010-12-09 01:22:13 +00:00
Jim Grosbach
e38a2a39c6 The add/sub SP instructions are really pseudos. The assembler should ignore 
them.

llvm-svn: 121345
 2010-12-09 01:21:27 +00:00
Matt Beaumont-Gay
a8aa446938 Remove unused variables 
llvm-svn: 121343
 2010-12-09 01:04:43 +00:00
Owen Anderson
43177d405a Fix typo in Thumb2 branch fixup. 
llvm-svn: 121342
 2010-12-09 01:02:09 +00:00
Eric Christopher
64e662fce9 Stop confusing people, it's not really a chain, or a tumor. 
llvm-svn: 121340
 2010-12-09 00:57:19 +00:00
Bill Wendling
baf852a1d6 Remove extraneous semicolon. 
llvm-svn: 121338
 2010-12-09 00:51:54 +00:00
Bill Wendling
9205cc6ea8 Attempt to make the bit-twiddling readable resulted in the binary value being 
overwritten.

llvm-svn: 121337
 2010-12-09 00:44:33 +00:00
Bill Wendling
cd8fdfd65f The BLX instruction is encoded differently than the BL, because why not? In 
particular, the immediate has 20-bits of value instead of 21. And bit 0 is '0'
always. Going through the BL fixup encoding was trashing the "bit 0 is '0'"
invariant.

Attempt to get the encoding at slightly more correct with this.

llvm-svn: 121336
 2010-12-09 00:39:08 +00:00
Eric Christopher
0100a8fda4 Remove extraneous copy from DAG conversion for darwin tls. This was 
popping up at O0 when it wasn't folded and the fast allocator would
complain.

llvm-svn: 121330
 2010-12-09 00:27:58 +00:00
Owen Anderson
b956593730 Fix Thumb2 BCC encoding and fixups. 
llvm-svn: 121329
 2010-12-09 00:27:41 +00:00
Eric Christopher
cc8a622ca4 Add rsp to the uses for the same reason as 32-bit. 
llvm-svn: 121328
 2010-12-09 00:26:41 +00:00
Kevin Enderby
988dab6b5c Allow a slash, '/', as a prefix separator for X86. rdar://8741045 
llvm-svn: 121320
 2010-12-08 23:57:59 +00:00
Jason W Kim
e270068021 Style nit and whitespace cleanup 
llvm-svn: 121317
 2010-12-08 23:35:25 +00:00
Jim Grosbach
5a00173ead Clean up the add/sub w/ SP source reg instructions in Thumb2 a bit. Add a FIXME 
for more thorough cleanup.

llvm-svn: 121315
 2010-12-08 23:30:19 +00:00
Jim Grosbach
2eda2e0be9 Fix T2TwoRegImm and use it for t2ADDrSPi12 and friends. 
llvm-svn: 121314
 2010-12-08 23:24:29 +00:00
Jason W Kim
e8047d9ec4 Removed dead comment. 
llvm-svn: 121313
 2010-12-08 23:19:44 +00:00
Jason W Kim
2e6e50c1b0 ARM/MC/ELF TPsoft is now a proper pseudo inst. 
Added test to check bl __aeabi_read_tp gets emitted properly for ELF/ASM
as well as ELF/OBJ (including fixup)

Also added support for ELF::R_ARM_TLS_IE32

llvm-svn: 121312
 2010-12-08 23:14:44 +00:00
Jim Grosbach
7a9e43e642 T2TwoRegImm isn't right for t2SUBrSPi12. Use T2I instead. 
llvm-svn: 121311
 2010-12-08 23:13:01 +00:00
Jim Grosbach
4f11f0f871 Add operand encoding for Thumb2 subw SP + imm. rdar://8745434 
llvm-svn: 121310
 2010-12-08 23:12:09 +00:00
Jim Grosbach
a423fbc4c7 Add operand encoding for Thumb2 addw Rn + imm. rdar://8745434 
llvm-svn: 121309
 2010-12-08 23:04:16 +00:00