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Commit Graph

198727 Commits

Author SHA1 Message Date
Eric Christopher
5111179a5e As part of using inclusive language within the llvm project,
migrate away from the use of blacklist and whitelist.
2020-06-20 00:24:57 -07:00
Eric Christopher
af63c3f94c [Support/Utils] As part of using inclusive language within the
llvm project, migrate away from the use of blacklist and whitelist.
2020-06-20 00:15:50 -07:00
Eric Christopher
4f849f4d44 [Target] As part of using inclusive language within the llvm project,
migrate away from the use of blacklist and whitelist.

This change affects an internal llvm command line option.
2020-06-20 00:06:39 -07:00
Xing GUO
35574dabe2 [DWARFYAML][debug_info] Fix array index out of bounds error
This patch is trying to fix the array index out of bounds error. I observed it in (https://reviews.llvm.org/harbormaster/unit/view/99638/).

Reviewed By: jhenderson, MaskRay

Differential Revision: https://reviews.llvm.org/D82139
2020-06-20 15:08:24 +08:00
Craig Topper
0d00716d4c [X86] Correct the implementation of ud1(a.k.a. ud2b) instruction.
We were missing the modrm byte this instruction has according
to current Intel SDM. Experiments with gcc indicate that different
modrm values are chosen based on 2 operands so I've added those
as well.

I think our previous implementation was based on an older behavior of
binutils that has since been changed.
2020-06-19 23:57:48 -07:00
Craig Topper
ef35532c13 [X86] Ignore bits 2:0 of the modrm byte when disassembling lfence, mfence, and sfence.
These are documented as using modrm byte of 0xe8, 0xf0, and 0xf8
respectively. But hardware ignore bits 2:0. So 0xe9-0xef is treated
the same as 0xe8. Similar for the other two.

Fixing this required adding 8 new formats to the X86 instructions
to convey this information. Could have gotten away with 3, but
adding all 8 made for a more logical conversion from format to
modrm encoding.

I renumbered the format encodings to keep the register modrm
formats grouped together.
2020-06-19 22:24:24 -07:00
Fangrui Song
a92d798d0e [SanitizeCoverage] Rename -fsanitize-coverage-{white,black}list to -fsanitize-coverage-{allow,block}list
Keep deprecated -fsanitize-coverage-{white,black}list as aliases for compatibility for now.

Reviewed By: echristo

Differential Revision: https://reviews.llvm.org/D82244
2020-06-19 22:22:47 -07:00
Yevgeny Rouban
d58eac3927 [IR] Convert profile metadata in createCallMatchingInvoke()
When an invoke instruction is converted to a call its
profile metadata is dropped because it has incompatible
format (see commit 16ad6eeb94ff).
This patch adds an attempt to convert profile data to
format of the call instruction. This used to work well
before the commit dcfa78a4ccec.

Reviewers: reames
Tags: #llvm
Differential Revision: https://reviews.llvm.org/D82071
2020-06-20 12:10:31 +07:00
Wang Rui
070b3d06c0 [Mips] Error if a non-immediate operand is used while an immediate is expected
The 32-bit type relocation (R_MIPS_32) cannot be used for instructions below:

ori $4, $4, start
ori $4, $4, (start - .)

We should print an error instead.

Reviewed By: atanasyan, MaskRay

Differential Revision: https://reviews.llvm.org/D81908
2020-06-19 22:08:59 -07:00
Eric Christopher
71f2701c0a [UpdateTestChecks] As part of using inclusive language within the
llvm project, migrate away from the use of blacklist and whitelist.
2020-06-19 21:35:11 -07:00
Vitaly Buka
4dbd071a15 [StackSafety,NFC] Don't rerun on LiveIn change 2020-06-19 21:29:31 -07:00
Xing GUO
cb1ecb07f3 [ObjectYAML][ELF] Add support for emitting the .debug_info section.
This patch helps add support for emitting the .debug_info section to yaml2elf.

Reviewed By: jhenderson, grimar, MaskRay

Differential Revision: https://reviews.llvm.org/D82073
2020-06-20 12:13:01 +08:00
Carl Ritson
f2504628bd [AMDGPU] Avoid use of V_READLANE into EXEC in SGPR spills
Always prefer to clobber input SGPRs and restore them after the
spill.  This applies to both spills to VGPRs and scratch.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D81914
2020-06-20 12:10:47 +09:00
romanova-ekaterina
8f7a8fd1c3 Error related to ThinLTO caching needs to be downgraded to a remark
This is a fix for PR #46392 (Diagnostic message (error) related to
ThinLTO caching needs to be downgraded to a remark).

There are diagnostic messages related to ThinLTO caching that contain
the word "error", but they are really just notices/remarks for users,
and they don't cause a build failure. The word "error" appearing can be
confusing to users, and may even cause deeper problems.

User's build system might be designed to interpret any error messages
(even a benign error message as the one above) reported by the compiler
as a build failure, thus causing the build to fail "needlessly". In
short, the term "error" in this diagnostic is misleading at best, and
may be causing build systems to fail at worst.

Differential Revision: https://reviews.llvm.org/D82138
2020-06-19 16:03:29 -07:00
Eric Christopher
4c6c241e2d As part of using inclusive language within the llvm project,
migrate away from the use of blacklist and whitelist.
2020-06-19 15:12:18 -07:00
Heejin Ahn
3298d1e5b3 [WebAssembly] Remove TEEs when dests are unstackified
When created in RegStackify pass, `TEE` has two destinations, where
op0 is stackified and op1 is not. But it is possible that
op0 becomes unstackified in `fixUnwindMismatches` function in
CFGStackify pass when a nested try-catch-end is introduced, violating
the invariant of `TEE`s destinations.

In this case we convert the `TEE` into two `COPY`s, which will
eventually be resolved in ExplicitLocals.

Reviewed By: dschuff

Differential Revision: https://reviews.llvm.org/D81851
2020-06-19 14:55:21 -07:00
Eric Christopher
2feb11e8c4 As part of using inclusive language within the llvm project,
migrate away from the use of blacklist and whitelist.
2020-06-19 14:52:01 -07:00
Martin Storsjö
4ded4cd51e [Support] Fix building for mingw on a case sensitive file system
This fixes cross building on a case sensitive file system after
2e613d2ded2c465bd06bd3cac30ffb4576bf72cc. (The official Windows
SDKs don't have self-consistent casing and can't be used as such on
case sentisive file systems without case fixups, while mingw headers
consistently use lower case.)
2020-06-20 00:39:22 +03:00
Arthur Eubanks
c207da9b60 [NFC] Remove unused pass name parser classes
Summary: Looks like these were for the most part touched over a decade ago.

Subscribers: mgorny, cfe-commits, llvm-commits

Tags: #clang, #llvm

Differential Revision: https://reviews.llvm.org/D82231
2020-06-19 13:41:42 -07:00
Amara Emerson
e3c37200f9 [AArch64][GlobalISel] Make G_SEXT_INREG legal and add selection support.
We were defaulting to the lower action for this, resulting in SHL+ASHR
sequences. On AArch64 we can do this in one instruction for an arbitrary
extension using SBFM as we do for G_SEXT.

Differential Revision: https://reviews.llvm.org/D81992
2020-06-19 13:20:41 -07:00
Daniel
ec554713c8 [clang-tidy] remove duplicate fixes of alias checkers
when both a check and its alias are enabled, we should only take the fixes of one of them and not both.
This patch fixes bug 45577
https://bugs.llvm.org/show_bug.cgi?id=45577

Reviewed By: aaron.ballman, njames93

Differential Revision: https://reviews.llvm.org/D80753
2020-06-19 20:40:59 +01:00
Sanjay Patel
46f661f4a4 [VectorCombine] refactor extract-extract logic; NFCI 2020-06-19 14:52:27 -04:00
Thomas Preud'homme
af838d617a Reland [FileCheck, unittest] Improve readability of ExpressionFormat
This was originally cd2553de77f and reverted in a3adfb400ef.
The ADT itostr bug this triggered was fixed in f3e8f961736.
2020-06-19 18:44:34 +01:00
Thomas Preud'homme
b66c895a2d [ADT] Fix itostr handling of min int64_t value
Summary:
UBSan buildbot caught an undefined behavior in itostr with INT64_MIN.
The negation cannot be represented in the promoted operand (long long).
Negation is well defined on unsigned value though so this commit does
the negation after the static cast.

Reviewers: jhenderson, chandlerc, lattner

Reviewed By: lattner

Subscribers: dexonsmith, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82200
2020-06-19 18:38:43 +01:00
Lang Hames
57d74cd85f [JITLink] Allow zero-length symbols at the end of blocks.
This relaxes an assertion that required symbols to start before the end
of a block. Instead, symbols are now required to end on or before the
end of a block. This fixes two important corner cases: Symbols at the
start of empty blocks/sections, and block/section end symbols.
2020-06-19 10:05:02 -07:00
Lang Hames
832526028d [JITLink] Display host -> target address mapping in debugging output.
This can be helpful for sanity checking JITLink memory manager behavior.
2020-06-19 10:05:02 -07:00
Sanjay Patel
54234e8ffc [VectorCombine] fix crash while transforming constants
This is a variation of the proposal in D82049 with an extra test.
2020-06-19 12:30:32 -04:00
Stanislav Mekhanoshin
ca27e2e8a4 [AMDGPU] Some formatting fixes. NFC. 2020-06-19 09:02:59 -07:00
Thomas Preud'homme
25010a100a Revert "[FileCheck, unittest] Improve readability of ExpressionFormat"
This reverts commit cd2553de77f2c3206deaa261a15cc7520ff2ff56.
2020-06-19 15:52:39 +01:00
Piotr Sobczak
b9c5311c77 Revert "[AMDGPU] Select s_cselect"
This caused some failures detected by the buildbot with
expensive checks enabled.

This reverts commit 4067de569f119a81419fbf2e79d5f3307dfdda5b.
2020-06-19 16:41:04 +02:00
Jay Foad
e95847e213 [AMDGPU] Add some missing -LABEL checks 2020-06-19 15:34:14 +01:00
dfukalov
c53b1ee136 [AMDGPU][CostModel] Add fneg cost estimation
Summary: The estimation uses AMDGPUTargetLowering::isFNegFree()

Reviewers: rampitec

Reviewed By: rampitec

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82065
2020-06-19 17:31:35 +03:00
Simon Pilgrim
6be38f15ce [X86][SSE] movmsk-cmp.ll - cleanup check prefixes and add SSE41 target tests 2020-06-19 15:24:59 +01:00
Piotr Sobczak
3a8e847d39 [AMDGPU] Select s_cselect
Summary:
Add patterns to select s_cselect in the isel.

Handle more cases of implicit SCC accesses in si-fix-sgpr-copies
to allow new patterns to work.

Subscribers: arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye, hiraditya, asbirlea, kerbowa, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81925
2020-06-19 16:17:46 +02:00
Sjoerd Meijer
c43371a1bf [ARM][MVE] tail-predication: renamed internal option.
Renamed -force-tail-predication to -force-mve-tail-predication because
that's more descriptive and consistent.
2020-06-19 15:07:06 +01:00
Mikhail Maltsev
23628b352d [ARM][BFloat] Implement lowering of bf16 load/store intrinsics
Reviewers: labrinea, dmgreen, pratlucas, LukeGeeson

Reviewed By: dmgreen

Subscribers: kristof.beyls, hiraditya, danielkiss, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D81486
2020-06-19 14:02:35 +00:00
Thomas Preud'homme
3691e53520 [FileCheck, unittest] Improve readability of ExpressionFormat
Summary:
Factor out repetetitive code into helper function and split massive
ExpressionFormat method test into separate test for each method,
removing dead code in passing. Also add a MinInt64 and MaxInt64 checks
when testing getMatchingString.

Reviewers: jhenderson, jdenny, probinson, grimar, arichardson

Reviewed By: jhenderson, grimar

Subscribers: llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D82132
2020-06-19 14:47:37 +01:00
Dmitry Preobrazhensky
11123346d5 [AMDGPU][MC][NFC] Updated and enabled MC lit tests
Updated tests disabled by change 5f5f566.

5f5f566b26
2020-06-19 16:27:40 +03:00
Simon Pilgrim
3abf59dab4 [X86][SSE] Add tests for (missing) MOVMSK(PCMPEQ(X,0)) != -1 -> PTESTZ(X,X) allof folds 2020-06-19 14:11:46 +01:00
Mikhail Maltsev
c955b9f411 [ARM][BFloat] Lowering of create/get/set/dup intrinsics
This patch adds codegen for the following BFloat
operations to the ARM backend:
* concatenation of bf16 vectors
* bf16 vector element extraction
* bf16 vector element insertion
* duplication of a bf16 value into each lane of a vector
* duplication of a bf16 vector lane into each lane

Differential Revision: https://reviews.llvm.org/D81411
2020-06-19 12:52:40 +00:00
Georgii Rymar
40767ae0bd [llvm-readobj] - Add a validation of the GNU hash table to printGnuHashHistogram().
Similar to D81937, we might crash when printing a histogram for a GNU hash table
with a 'symndx' index that is larger than the number of dynamic symbols.

This patch adopts and reuses the `getGnuHashTableChains()` helper which performs
a validation of the table. As a side effect the warning reported for
the --gnu-hash-table was improved.

Also with this change we start to report a warning when the histogram is requested for
the GNU hash table, but the dynamic symbols table is empty (size == 0).

Differential revision: https://reviews.llvm.org/D82010
2020-06-19 14:24:51 +03:00
Florian Hahn
21433e6c3f [DSE,MSSA] Enable XFAIL'd merge-stores.ll test (NFC).
All cases in the test are supported now, it only still failed because an
over-eager regex match not accounting for `, align ` being added to each
load/store now.
2020-06-19 12:10:47 +01:00
Simon Pilgrim
ecfc482b0d [X86][SSE] combineHorizontalPredicateResult - improve all_of(X == 0) for vXi64 on pre-SSE41 targets
Without SSE41 we don't have the PCMPEQQ instruction, making cmp-with-zero reductions more complicated than necessary. We can compare as vXi32 (PCMPEQD) and tweak the MOVMSK comparison to test upper/lower DWORD comparisons.

This pre-fixes something that occurs with null tests for vectors of (64-bit) pointers such as in PR35129.
2020-06-19 11:43:25 +01:00
LLVM GN Syncbot
c06cf3682a [gn build] Port 0628705efaf 2020-06-19 10:15:53 +00:00
Vitaly Buka
3e39d691ff [StackSafety,NFC] Fix comment 2020-06-19 03:11:13 -07:00
Tyker
24b4a03b33 try to fix build bot after b7338fb1a6a464472850211165391983d2c8fdf3 2020-06-19 12:02:09 +02:00
Simon Pilgrim
20c58341f7 [X86][SSE] combineSetCCMOVMSK - fold MOVMSK(SHUFFLE(X,u)) -> MOVMSK(X)
If we're permuting ALL the elements of a single vector, then for allof/anyof MOVMSK tests we can avoid the shuffle entirely.
2020-06-19 10:57:52 +01:00
David Sherwood
c46fc6adbe [SVE] Fall back on DAG ISel at -O0 when encountering scalable types
At the moment we use Global ISel by default at -O0, however it is
currently not capable of dealing with scalable vectors for two
reasons:

1. The register banks know nothing about SVE registers.
2. The LLT (Low Level Type) class knows nothing about scalable
   vectors.

For now, the easiest way to avoid users hitting issues when using
the SVE ACLE is to fall back on normal DAG ISel when encountering
instructions that operate on scalable vector types.

I've added a couple of RUN lines to existing SVE tests to ensure
we can compile at -O0. I've also added some new tests to

  CodeGen/AArch64/GlobalISel/arm64-fallback.ll

that demonstrate we correctly fallback to DAG ISel at -O0 when
lowering formal arguments or translating instructions that involve
scalable vector types.

Differential Revision: https://reviews.llvm.org/D81557
2020-06-19 10:57:00 +01:00
David Sherwood
589444b8e2 [CodeGen,AArch64] Fix up warnings in performExtendCombine
Try to avoid calling getVectorNumElements() or relying upon the
TypeSize conversion to uin64_t.

Differential Revision: https://reviews.llvm.org/D81573
2020-06-19 10:34:51 +01:00
Vitaly Buka
aacaa16559 [StackSafety] Add StackLifetime::isAliveAfter
This function is going to be added into StackSafety checks.
This patch uses function in ::print implementation to make sure
that it works as expected.
2020-06-19 02:32:17 -07:00