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Commit Graph

678 Commits

Author SHA1 Message Date
Dan Gohman
51e7be7b8f Fix the comments for the 'fast' parameter in addPassesToEmitFile.
llvm-svn: 40592
2007-07-30 15:04:59 +00:00
Dan Gohman
23f9a3ad3b Fix the comment for getClosestTargetForJIT to reflect the fact that
it does not have a Module parameter.

llvm-svn: 40590
2007-07-30 14:58:59 +00:00
Dan Gohman
75473b49ea More explicit keywords.
llvm-svn: 40589
2007-07-30 14:51:59 +00:00
Duncan Sands
e8bb2c6d32 Support for trampolines, except for X86 codegen which is
still under discussion.

llvm-svn: 40549
2007-07-27 12:58:54 +00:00
Christopher Lamb
7bef240f69 Have register info provide the inverse mapping of register->superregisters. PR1350
llvm-svn: 40519
2007-07-26 08:01:58 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350
llvm-svn: 40518
2007-07-26 07:48:21 +00:00
Evan Cheng
cdb4e7949f Added -print-emitted-asm to print out JIT generated asm to cerr.
llvm-svn: 40123
2007-07-20 21:56:13 +00:00
Dan Gohman
0ba554c0c8 Fix comments about vectors to use the current wording.
llvm-svn: 39921
2007-07-16 14:29:03 +00:00
Anton Korobeynikov
5635277c36 Long live the exception handling!
This patch fills the last necessary bits to enable exceptions
handling in LLVM. Currently only on x86-32/linux.

In fact, this patch adds necessary intrinsics (and their lowering) which
represent really weird target-specific gcc builtins used inside unwinder.

After corresponding llvm-gcc patch will land (easy) exceptions should be
more or less workable. However, exceptions handling support should not be 
thought as 'finished': I expect many small and not so small glitches
everywhere.

llvm-svn: 39855
2007-07-14 14:06:15 +00:00
Evan Cheng
6125079452 Add OptionalDefOperand. Remove clobbersPred. Also add DefinesPredicate to be used by if-converter.
llvm-svn: 38499
2007-07-10 18:06:29 +00:00
Dan Gohman
3f7558673e Fix a typo in a comment.
llvm-svn: 38456
2007-07-09 15:15:24 +00:00
Dan Gohman
61966b8551 Remove redundant declarations.
llvm-svn: 37946
2007-07-06 13:59:28 +00:00
Dan Gohman
c6bdcfa8c0 Add new TargetLowering code to provide the final register type that an
illegal value type will be transformed to, for code that needs the
register type after all transformations instead of just after the first
transformation.

Factor out the code that uses this information to do copy-from-regs and
copy-to-regs for various purposes into separate functions so that they
are done consistently.

llvm-svn: 37781
2007-06-28 23:29:44 +00:00
Dan Gohman
cb89e19a6d Rename ("shrinkify") MVT::isExtendedValueType to MVT::isExtendedVT.
llvm-svn: 37758
2007-06-27 16:08:04 +00:00
Evan Cheng
30adb50aaf Add comment.
llvm-svn: 37741
2007-06-26 21:19:07 +00:00
Evan Cheng
ac10d44736 Add immediate sub-registers.
llvm-svn: 37738
2007-06-26 20:59:16 +00:00
Dan Gohman
eea90f90af Replace ?: with if statements, for clarity.
llvm-svn: 37735
2007-06-26 16:19:08 +00:00
Dan Gohman
fb8c9beba3 Simplify the expression for TargetLowering::isTypeLegal.
llvm-svn: 37732
2007-06-26 15:16:27 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
2007-06-26 00:48:07 +00:00
Dan Gohman
354f02e03d Generalize MVT::ValueType and associated functions to be able to represent
extended vector types. Remove the special SDNode opcodes used for pre-legalize
vector operations, and the special MVT::Vector type used with them. Adjust
lowering and legalize to work with the normal SDNode kinds instead, and to
use the normal MVT functions to work with vector types instead of using the
two special operands that the pre-legalize nodes held.

This allows pre-legalize and post-legalize DAGs, and the code that operates
on them, to be more consistent. Pre-legalize vector operators can be handled
more consistently with scalar operators. And, -view-dag-combine1-dags and
-view-legalize-dags now look prettier for vector code.

llvm-svn: 37719
2007-06-25 16:23:39 +00:00
Dan Gohman
a62327ea40 Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.

llvm-svn: 37704
2007-06-22 14:59:07 +00:00
Dan Gohman
1815e9bdb3 Rename TargetLowering::getNumElements and friends to
TargetLowering::getNumRegisters and similar, to avoid confusion with
the actual number of elements for vector types.

llvm-svn: 37687
2007-06-21 14:42:22 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
2007-06-19 01:48:05 +00:00
Evan Cheng
4358a7f1e9 Replace CanBeDuplicated() with a M_NOT_DUPLICABLE bit.
llvm-svn: 37642
2007-06-19 01:21:41 +00:00
Evan Cheng
34a6cb0b2e Added CanBeDuplicated(). It returns true if an instruction can be safely duplicated (e.g. during ifcvt).
llvm-svn: 37605
2007-06-15 21:13:54 +00:00
Dale Johannesen
62f49dd524 Do not treat FP_REG_KILL as terminator in branch analysis (X86).
llvm-svn: 37578
2007-06-14 22:03:45 +00:00
Dan Gohman
35f2b4d716 Add a target hook to allow loads from constant pools to be rematerialized, and an
implementation for x86.

llvm-svn: 37576
2007-06-14 20:50:44 +00:00
Dan Gohman
74c92798d8 Eliminate some redundant newlines in asm output.
llvm-svn: 37574
2007-06-14 15:00:27 +00:00
Christopher Lamb
68017d151b Add support to tablegen for specifying subregister classes on a per register class basis.
llvm-svn: 37572
2007-06-13 22:20:15 +00:00
Evan Cheng
1a6c0341fd Add a utility routine to check for unpredicated terminator instruction.
llvm-svn: 37528
2007-06-08 21:59:56 +00:00
Evan Cheng
4de6599e83 Add a machine instruction flag indicating the instruction can clobber condition code / register(s) used to predicate instructions.
llvm-svn: 37464
2007-06-06 10:13:55 +00:00
Evan Cheng
0dc7a8cac6 Target specific ifcvt code duplication limit.
llvm-svn: 37384
2007-06-01 08:25:24 +00:00
Dale Johannesen
1ba04f7d87 Make stable_sort in tail merging actually be stable (it never was, but didn't
matter until my last change).  Reenable tail merging by default.

llvm-svn: 37354
2007-05-29 23:47:50 +00:00
Evan Cheng
d8b25a2091 Add missing const qualifiers.
llvm-svn: 37341
2007-05-29 18:35:22 +00:00
Devang Patel
3eb349409f Disable Tail Merging for now.
llvm-svn: 37329
2007-05-25 01:00:24 +00:00
Evan Cheng
f2d1d0124e Add a couple of target hooks for predication.
llvm-svn: 37306
2007-05-23 07:19:12 +00:00
Dale Johannesen
738f94210c name change requested by review of previous patch
llvm-svn: 37289
2007-05-22 18:31:04 +00:00
Dale Johannesen
fe0fe14411 Make tail merging the default, except on powerPC. There was no prior art
for a target-dependent default with a command-line override; this way
should be generally usable.

llvm-svn: 37285
2007-05-22 17:14:46 +00:00
Evan Cheng
7d3f771e9c Consistency.
llvm-svn: 37274
2007-05-22 01:21:58 +00:00
Evan Cheng
234aab208a RemoveBranch() and InsertBranch() now returns number of instructions deleted / inserted.
llvm-svn: 37192
2007-05-18 00:05:48 +00:00
Evan Cheng
3ce37e8d78 Fix comment.
llvm-svn: 37191
2007-05-18 00:00:30 +00:00
Evan Cheng
dc9e574073 Remove. Not needed.
llvm-svn: 37139
2007-05-17 00:11:35 +00:00
Evan Cheng
3163b77d5e Add target hook to specify block size limit for if-conversion.
llvm-svn: 37134
2007-05-16 23:45:53 +00:00
Evan Cheng
973f4a19cb PredicateInstruction returns true if the operation was successful.
llvm-svn: 37124
2007-05-16 21:53:07 +00:00
Evan Cheng
3b10540b5e Rename M_PREDICATED to M_PREDICABLE; Move TargetInstrInfo::isPredicatable() to MachineInstr::isPredicable().
llvm-svn: 37115
2007-05-16 20:43:42 +00:00
Evan Cheng
770584a8cd Fix comments.
llvm-svn: 37096
2007-05-16 05:09:34 +00:00
Evan Cheng
7fe6d7cb7e Add TargetInstrInfo predication hooks.
llvm-svn: 37091
2007-05-16 01:58:56 +00:00
Evan Cheng
71c4d42bd7 All operands that made up of the predicate operands are maked M_PREDICATE_OPERAND.
llvm-svn: 37062
2007-05-15 01:21:27 +00:00
Nick Lewycky
c2306ff5b4 Fix typo in comment.
llvm-svn: 36873
2007-05-06 13:37:16 +00:00
Anton Korobeynikov
ce48606d7a Emit sections/directives in the proper order. This fixes PR1376. Also,
some small cleanup was made.

llvm-svn: 36780
2007-05-05 09:04:50 +00:00