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Author SHA1 Message Date
Evan Cheng
5307ec12d7 Check for FiniteOnlyFPMath as well. 
llvm-svn: 107904
 2010-07-08 20:12:24 +00:00
Devang Patel
69b391b5b1 Reuse DIEInteger for 1. This is frequently used while emitting an attribute using dwarf::DW_FORM_flag form. 
llvm-svn: 107903
 2010-07-08 20:10:35 +00:00
Jakob Stoklund Olesen
f9441b5025 Teach the x86 floating point stackifier to handle COPY instructions. 
This pass runs before COPY instructions are passed to copyPhysReg, so we simply
translate COPY to the proper pseudo instruction. Note that copyPhysReg does not
handle floating point stack copies.

Once COPY is used everywhere, this can be cleaned up a bit, and most of the
pseudo instructions can be removed.

llvm-svn: 107899
 2010-07-08 19:46:30 +00:00
Jakob Stoklund Olesen
aed86b1af7 Implement X86InstrInfo::copyPhysReg 
llvm-svn: 107898
 2010-07-08 19:46:25 +00:00
Bob Wilson
12922e6bec The NEONPreAllocPass should never have to assign fixed registers anymore. 
This pass can go away entirely soon.

llvm-svn: 107892
 2010-07-08 17:45:26 +00:00
Bob Wilson
fca7a252fb For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap the 
words within the 64-bit D registers.  Use VLD1/VST1 with 64-bit elements
instead.

llvm-svn: 107890
 2010-07-08 17:44:00 +00:00
Jim Grosbach
8e0f47b37d After r107880, findSurvivorReg() no longer needs to be public. 
llvm-svn: 107887
 2010-07-08 17:27:23 +00:00
Kevin Enderby
9bf8ee521c Added the darwin .weak_def_can_be_hidden directive. 
llvm-svn: 107886
 2010-07-08 17:22:42 +00:00
Gabor Greif
3e4b85cd99 only dereference iterator once in the loop 
(by caching the result we save a potentially expensive dereference)

also use typedefs to shorten type declarations

llvm-svn: 107883
 2010-07-08 16:56:18 +00:00
Bob Wilson
b07d97d333 Clean up a comment. 
llvm-svn: 107882
 2010-07-08 16:54:45 +00:00
Gabor Greif
2a21837ee1 remove unneeded parens 
llvm-svn: 107881
 2010-07-08 16:52:57 +00:00
Jim Grosbach
38aae4a067 Clean up scavengeRegister() a bit to prefer available regs, which allows 
the simplification of frame index register scavenging to not have to check
for available registers directly and instead just let scavengeRegister()
handle it.

llvm-svn: 107880
 2010-07-08 16:49:26 +00:00
Jakob Stoklund Olesen
30aacf68b9 Convert EXTRACT_SUBREG to COPY when emitting machine instrs. 
EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead.

Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg().
The isMoveInstr hook will be removed later.

llvm-svn: 107879
 2010-07-08 16:40:22 +00:00
Jakob Stoklund Olesen
8983ea915c Remove references to INSERT_SUBREG after de-SSA. 
Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of
INSERT_SUBREG.

llvm-svn: 107878
 2010-07-08 16:40:15 +00:00
Duncan Sands
5338c9f877 Use std::vector rather than SmallVector here because SmallVector 
causes some versions of gcc to crash when building LLVM.

llvm-svn: 107869
 2010-07-08 13:06:08 +00:00
Benjamin Kramer
c1ae755ba7 Merge the duplicated iabs optimization in DAGCombiner and let it detected a few more idioms. 
llvm-svn: 107868
 2010-07-08 12:09:56 +00:00
Duncan Sands
dcc1398f44 Do not use std::stack because it causes obscure failures when 
compiled with MSVC 2010 (PR7367).  Instead use a SmallVector.

llvm-svn: 107867
 2010-07-08 11:54:27 +00:00
Benjamin Kramer
27eb255a70 Teach instcombine to transform 
(X >s -1) ? C1 : C2 and (X <s  0) ? C2 : C1
into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional.

This optimization could be extended to take non-const C1 and C2 but we better
stay conservative to avoid code size bloat for now.

for
int sel(int n) {
     return n >= 0 ? 60 : 100;
}

we now generate
  sarl  $31, %edi
  andl  $40, %edi
  leal  60(%rdi), %eax

instead of
  testl %edi, %edi
  movl  $60, %ecx
  movl  $100, %eax
  cmovnsl %ecx, %eax

llvm-svn: 107866
 2010-07-08 11:39:10 +00:00
Duncan Sands
896788595d Tweak some docs now that the default build is called Debug+Asserts. 
llvm-svn: 107862
 2010-07-08 08:27:18 +00:00
Eric Christopher
091bf69467 A slight reworking of the custom patterns for x86-64 tpoff codegen and 
correct the testcase for valid assembly.

Needs more tests.

llvm-svn: 107860
 2010-07-08 07:36:46 +00:00
Evan Cheng
3e8530bf14 r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0. 
llvm-svn: 107856
 2010-07-08 06:01:49 +00:00
Jakob Stoklund Olesen
c0c27a2b2a Add TargetInstrInfo::copyPhysReg hook and use it from LowerSubregs. 
This target hook is intended to replace copyRegToReg entirely, but for now it
calls copyRegToReg.

Any remaining calls to copyRegToReg wil be replaced by COPY instructions.

llvm-svn: 107854
 2010-07-08 05:01:41 +00:00
Evan Cheng
ed3f224f04 Optimize some vfp comparisons to integer ones. This patch implements the simplest case when the following conditions are met: 
1. The arguments are f32.
2. The arguments are loads and they have no uses other than the comparison.
3. The comparison code is EQ or NE.

e.g.
        vldr.32 s0, [r1]
        vldr.32 s1, [r0]
        vcmpe.f32       s1, s0
        vmrs    apsr_nzcv, fpscr
	beq     LBB0_2
=>
        ldr     r1, [r1]
        ldr     r0, [r0]
        cmp     r0, r1
        beq     LBB0_2

More complicated cases will be implemented in subsequent patches.

llvm-svn: 107852
 2010-07-08 02:08:50 +00:00
Dale Johannesen
2df647f882 Changes to ARM tail calls, mostly cosmetic. 
Add explicit testcases for tail calls within the same module.
Duplicate some code to humor those who think .w doesn't apply on ARM.
Leave this disabled on Thumb1, and add some comments explaining why it's hard
and won't gain much.

llvm-svn: 107851
 2010-07-08 01:18:23 +00:00
Dan Gohman
4dcc56a102 Revert 107840 107839 107813 107804 107800 107797 107791. 
Debug info intrinsics win for now.

llvm-svn: 107850
 2010-07-08 01:00:56 +00:00
Jim Grosbach
b934d25d5f When processing frame index virtual registers, consider all available registers 
(if there are any) and use the one which remains available for the longest
rather than just using the first one. This should help enable better re-use
of the loaded frame index values. rdar://7318760

llvm-svn: 107847
 2010-07-08 00:38:54 +00:00
Chris Lattner
bf009b527a Fix the second half of PR7437: scalarrepl wasn't preserving 
address spaces when SRoA'ing memcpy's.

llvm-svn: 107846
 2010-07-08 00:27:05 +00:00
Dan Gohman
636476bc0b Don't forward-declare registers for static allocas, which we'll 
prefer to materialize as local constants. This fixes the clang
bootstrap abort.

llvm-svn: 107840
 2010-07-07 23:52:58 +00:00
Dan Gohman
10195fc7f7 Fix -fast-isel-abort to check the right instruction. 
llvm-svn: 107839
 2010-07-07 23:47:25 +00:00
Chris Lattner
20161998c6 use PrintEscapedString to handle attribute section with escapes in it, 
PR7399.  The asm parser already handles this.  This is of dubious 
utility (see the PR) but the asmprinter was clearly broken here.

llvm-svn: 107834
 2010-07-07 23:16:37 +00:00
Jakob Stoklund Olesen
6afcd69bee fix copies to/from GR8_ABCD_H even more 
llvm-svn: 107832
 2010-07-07 23:04:56 +00:00
Jim Grosbach
46d94f1c1e grammar 
llvm-svn: 107831
 2010-07-07 22:53:35 +00:00
Jim Grosbach
8f27ad0d9d Handle cases where the post-RA scheduler may move instructions between the 
address calculation instructions leading up to a jump table when we're trying
to convert them into a TB[H] instruction in Thumb2. This realistically
shouldn't happen much, if at all, for well formed inputs, but it's more correct
to handle it. rdar://7387682

llvm-svn: 107830
 2010-07-07 22:51:22 +00:00
Chris Lattner
155420f59f finish up support for callw: PR7195 
llvm-svn: 107826
 2010-07-07 22:35:13 +00:00
Chris Lattner
6a5db9c9c9 Implement the major chunk of PR7195: support for 'callw' 
in the integrated assembler.  Still some discussion to be
done.

llvm-svn: 107825
 2010-07-07 22:27:31 +00:00
Bruno Cardoso Lopes
b92b51191e Add more assembly opcodes for SSE compare instructions 
llvm-svn: 107823
 2010-07-07 22:24:03 +00:00
Devang Patel
3d7c71dbbb One MDNode may be used to create regular DIE as well as abstract DIE. 
Keep track of abstract subprogram DIEs. 

llvm-svn: 107822
 2010-07-07 22:20:57 +00:00
Evan Cheng
22b3e8f3b1 Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument for consistency sake. 
llvm-svn: 107820
 2010-07-07 22:15:37 +00:00
Devang Patel
82ccfed750 Print undefined/unknown debug value as "undef". 
llvm-svn: 107818
 2010-07-07 21:52:21 +00:00
Dan Gohman
a88ae239b8 Not all custom inserters create new basic blocks. If the inserter 
didn't create a new block, don't reset the insert position.

llvm-svn: 107813
 2010-07-07 21:18:22 +00:00
Jim Grosbach
d13cc7716e grammar and trailing whitespace 
llvm-svn: 107811
 2010-07-07 21:06:51 +00:00
Devang Patel
3e07e4eb8b Rename couple of maps. 
llvm-svn: 107810
 2010-07-07 20:49:57 +00:00
Jakob Stoklund Olesen
34ec644313 Allow copies between GR8_ABCD_L and GR8_ABCD_H. 
This fixes PR7540.

llvm-svn: 107809
 2010-07-07 20:33:27 +00:00
Reid Kleckner
65635f9231 Update the docs for debugging JITed code with GDB. 
llvm-svn: 107808
 2010-07-07 20:16:45 +00:00
Devang Patel
6aef3e8bb3 80 cols. 
llvm-svn: 107807
 2010-07-07 20:12:52 +00:00
Dan Gohman
d0caefa601 Implement bottom-up fast-isel. This has the advantage of not requiring 
a separate DCE pass over MachineInstrs.

llvm-svn: 107804
 2010-07-07 19:20:32 +00:00
Dan Gohman
424cc6b616 Add X86FastISel support for return statements. This entails refactoring 
a bunch of stuff, to allow the target-independent calling convention
logic to be employed.

llvm-svn: 107800
 2010-07-07 18:32:53 +00:00
Bruno Cardoso Lopes
8d350872d4 Add AVX AES instructions 
llvm-svn: 107798
 2010-07-07 18:24:20 +00:00
Dan Gohman
317e584821 Update the insert position after scheduling, which may change the 
position when emitting multiple blocks when executing a custom
inserter.

llvm-svn: 107797
 2010-07-07 18:22:13 +00:00
Devang Patel
c5344b8cc5 Update comment. 
llvm-svn: 107796
 2010-07-07 18:18:18 +00:00