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264 Commits

Author SHA1 Message Date
Chris Lattner
1707a88a2c Sink InstructionSelect() out of each target into SDISel, and rename it 
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
 2010-03-02 06:34:30 +00:00
Evan Cheng
b5fe25544c Split SelectionDAGISel::IsLegalAndProfitableToFold to 
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
 2010-02-15 19:41:07 +00:00
Chris Lattner
7acf9be6c4 move target-independent opcodes out of TargetInstrInfo 
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
 2010-02-09 19:54:29 +00:00
Evan Cheng
f1a3f81a1d Fix r93758. Use isel patterns instead of c++ selection code to select rbit and make sure we pick different instructions for ARM vs. Thumb2. 
llvm-svn: 93829
 2010-01-19 00:44:15 +00:00
Jim Grosbach
70af2216fd Patch by David Conrad: 
"On ARMv6T2 this turns cttz into rbit, clz instead of the 4 instruction
 sequence it is now."

llvm-svn: 93758
 2010-01-18 19:58:49 +00:00
Bob Wilson
b4c16ab0b3 Fix an off-by-one error that caused the chain operand to be dropped from Neon 
vector load-lane and store-lane instructions.

llvm-svn: 93673
 2010-01-17 05:58:23 +00:00
Dan Gohman
9bcfdf98f1 Change SelectCode's argument from SDValue to SDNode *, to make it more 
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
 2010-01-05 01:24:18 +00:00
Anton Korobeynikov
0f885eb7fd Materialize global addresses via movt/movw pair, this is always better 
than doing the same via constpool:
1. Load from constpool costs 3 cycles on A9, movt/movw pair - just 2.
2. Load from constpool might stall up to 300 cycles due to cache miss.
3. Movt/movw does not use load/store unit.
4. Less constpool entries => better compiler performance.

This is only enabled on ELF systems, since darwin does not have needed
relocations (yet).

llvm-svn: 89720
 2009-11-24 00:44:37 +00:00
Evan Cheng
a7496ef9a6 Add predicate operand to NEON instructions. Fix lots (but not all) 80 col violations in ARMInstrNEON.td. 
llvm-svn: 89542
 2009-11-21 06:21:52 +00:00
Evan Cheng
405012b096 Fix codegen of conditional move of immediates. We were not making use of the immediate forms of cmov instructions at all. 
llvm-svn: 89423
 2009-11-20 00:54:03 +00:00
Evan Cheng
af22254deb Refactor cmov selection code out to a separate function. No functionality change. 
llvm-svn: 89396
 2009-11-19 21:45:22 +00:00
Evan Cheng
9730c9113e 80 col violation. 
llvm-svn: 89337
 2009-11-19 08:16:50 +00:00
Jim Grosbach
ea6c9c17f5 Use Unified Assembly Syntax for the ARM backend. 
llvm-svn: 86494
 2009-11-09 00:11:35 +00:00
Jim Grosbach
73c1e315e1 Support alignment specifier for NEON vld/vst instructions 
llvm-svn: 86404
 2009-11-07 21:25:39 +00:00
Dan Gohman
eec0f1c506 Remove uninteresting and confusing debug output. 
llvm-svn: 86149
 2009-11-05 18:47:09 +00:00
Bob Wilson
ac53e0c640 Prune unnecessary include. 
llvm-svn: 85805
 2009-11-02 16:58:31 +00:00
Johnny Chen
37851c95e8 Test commit. Added '.' to the comment line. 
llvm-svn: 85255
 2009-10-27 17:25:15 +00:00
Evan Cheng
8fdd1661fa Don't generate sbfx / ubfx with negative lsb field. Patch by David Conrad. 
llvm-svn: 84813
 2009-10-22 00:40:00 +00:00
Evan Cheng
275a09e55d Match more patterns to movt. 
llvm-svn: 84751
 2009-10-21 08:15:52 +00:00
Bob Wilson
1554029c7c Remove unused variables to fix build warning. 
llvm-svn: 84144
 2009-10-14 21:40:45 +00:00
Bob Wilson
320891060f Refactor code to select NEON VST intrinsics. 
llvm-svn: 84122
 2009-10-14 18:32:29 +00:00
Bob Wilson
2b19bbea06 Refactor code to select NEON VLD intrinsics. 
llvm-svn: 84117
 2009-10-14 17:28:52 +00:00
Bob Wilson
5dbe1c0143 More refactoring. NEON vst lane intrinsics can share almost all the code for 
vld lane intrinsics.

llvm-svn: 84110
 2009-10-14 16:46:45 +00:00
Bob Wilson
7623a1ce5c Refactor code for selecting NEON load lane intrinsics. 
llvm-svn: 84109
 2009-10-14 16:19:03 +00:00
Bob Wilson
a98883deaa More Neon clean-up: avoid the need for custom-lowering vld/st-lane intrinsics 
by creating TargetConstants during instruction selection instead of during
legalization.

llvm-svn: 84042
 2009-10-13 22:29:24 +00:00
Bob Wilson
d66a3fd73b Revise ARM inline assembly memory operands to require the memory address to 
be in a register.  The previous use of ARM address mode 2 was completely
arbitrary and inappropriate for Thumb.  Radar 7137468.

llvm-svn: 84022
 2009-10-13 20:50:28 +00:00
Sandeep Patel
af459ed32d Fix method name in comment, per Bob Wilson. 
llvm-svn: 84017
 2009-10-13 20:25:58 +00:00
Sandeep Patel
1584038783 Add ARMv6T2 SBFX/UBFX instructions. Approved by Anton Korobeynikov. 
llvm-svn: 84009
 2009-10-13 18:59:48 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
0159d0d864 Clean up some unnecessary initializations. 
llvm-svn: 83566
 2009-10-08 18:52:56 +00:00
Bob Wilson
c62c9946e2 Clean up a comment (indentation was wrong). 
llvm-svn: 83565
 2009-10-08 18:51:31 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00
Bob Wilson
bbcf30c05c Pass the optimization level when constructing the ARM instruction selector. 
Otherwise, it is always set to "default", which prevents debug info from
even being generated during isel.  Radar 7250345.

llvm-svn: 82988
 2009-09-28 14:30:20 +00:00