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53a8f3981c
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1549 Commits

Author SHA1 Message Date
Jeffrey Yasskin
53a8f3981c Fix http://llvm.org/PR5729: x86-64 tail calls were putting their targets into 
R11, and then asserting that the target was in R9.  Since R9 isn't reserved for
the target anymore, and is used as an argument, this patch changes the
assertion.

llvm-svn: 93065
 2010-01-09 18:56:43 +00:00
Dan Gohman
3708af1c59 Revert an earlier change to SIGN_EXTEND_INREG for vectors. The VTSDNode 
really does need to be a vector type, because
TargetLowering::getOperationAction for SIGN_EXTEND_INREG uses that type,
and it needs to be able to distinguish between vectors and scalars.

Also, fix some more issues with legalization of vector casts.

llvm-svn: 93043
 2010-01-09 02:13:55 +00:00
Evan Cheng
2e497d1ed4 Fix a critical bug in 64-bit atomic operation lowering for 32-bit. The results of the cmpxchg8b instructions are being thrown away when it branches back to the top of the checking loop. This means the loop always compares against the old value and this can result in a dead lock. 
llvm-svn: 93028
 2010-01-08 23:41:50 +00:00
Evan Cheng
f96a9ec02b ReplaceAllUsesOfValueWith may delete other nodes that the one being replaced. Do not delete dead nodes again. 
llvm-svn: 92988
 2010-01-08 02:36:12 +00:00
Chris Lattner
e0199dff81 Fix rdar://7517201, a regression introduced by r92849. 
When folding a and(any_ext(load)) both the any_ext and the
load have to have only a single use.

This removes the anyext-uses.ll testcase which started failing
because it is unreduced and unclear what it is testing.

llvm-svn: 92950
 2010-01-07 21:59:23 +00:00
Evan Cheng
51d86260ff Fix a minor regression from my dag combiner changes. One more place which needs to look pass truncates. 
llvm-svn: 92885
 2010-01-07 00:54:06 +00:00
Evan Cheng
25dcf9b830 Teach dag combine to fold the following transformation more aggressively: 
(OP (trunc x), (trunc y)) -> (trunc (OP x, y))

Unfortunately this simple change causes dag combine to infinite looping. The problem is the shrink demanded ops optimization tend to canonicalize expressions in the opposite manner. That is badness. This patch disable those optimizations in dag combine but instead it is done as a late pass in sdisel.

This also exposes some deficiencies in dag combine and x86 setcc / brcond lowering. Teach them to look pass ISD::TRUNCATE in various places.

llvm-svn: 92849
 2010-01-06 19:38:29 +00:00
Dan Gohman
93a28a6ce9 Move this test from test/Transforms/IndVarSimplify to 
test/CodeGen/X86, as doesn't use -indvars, and it does use
llc -march=x86-64.

llvm-svn: 92799
 2010-01-05 22:52:54 +00:00
Bill Wendling
7e9607ab56 Don't assign the shift the same type as the variable being shifted. This could 
result in illegal types for the SHL operator.

llvm-svn: 92797
 2010-01-05 22:39:10 +00:00
Dan Gohman
5fa04f2707 Delete useless trailing semicolons. 
llvm-svn: 92740
 2010-01-05 17:55:26 +00:00
Dan Gohman
73b0882c6e Make this test more portable. 
llvm-svn: 92514
 2010-01-04 21:23:34 +00:00
Dan Gohman
b71bc40eed Add some tests and update an existing test to reflect recent 
x86 isel peeps.

llvm-svn: 92509
 2010-01-04 20:53:54 +00:00
Chris Lattner
8e83066d12 fix PR5930, allowing the asmprinter to emit difference between 
two labels as a truncate.

llvm-svn: 92455
 2010-01-03 18:33:18 +00:00
Chris Lattner
49cda26f7e add PR# 
llvm-svn: 92451
 2010-01-03 18:10:58 +00:00
Chris Lattner
7246a69d2b differences between two blockaddress's don't cause a 
global variable initializer to require relocations.

llvm-svn: 92450
 2010-01-03 18:09:40 +00:00
Chris Lattner
9e64bad0da allow this to work on linux hosts. 
llvm-svn: 92407
 2010-01-02 00:22:15 +00:00
Chris Lattner
fe8af82cd4 Teach codegen to handle: 
(X != null) | (Y != null) --> (X|Y) != 0
 (X == null) & (Y == null) --> (X|Y) == 0

so that instcombine can stop doing this for pointers.  This is part of PR3351,
which is a case where instcombine doing this for pointers (inserting ptrtoint)
is pessimizing code.

llvm-svn: 92406
 2010-01-02 00:00:03 +00:00
Chris Lattner
4e49a69ec5 rename file. 
llvm-svn: 92405
 2010-01-01 23:55:04 +00:00
Chris Lattner
44298d184a Teach codegen to lower llvm.powi to an efficient (but not optimal) 
multiply sequence when the power is a constant integer.  Before, our
codegen for std::pow(.., int) always turned into a libcall, which was
really inefficient.

This should also make many gfortran programs happier I'd imagine.

llvm-svn: 92388
 2010-01-01 03:32:16 +00:00
Chris Lattner
4e96d36f72 handle equality memcmp of 8 bytes on x86-64 with two unaligned loads and a 
compare.  On other targets we end up with a call to memcmp because we don't
want 16 individual byte loads.  We should be able to use movups as well, but
we're failing to select the generated icmp.

llvm-svn: 92107
 2009-12-24 01:07:17 +00:00
Chris Lattner
5d3919d5f9 move an optimization for memcmp out of simplifylibcalls and into 
SDISel.  This optimization was causing simplifylibcalls to 
introduce type-unsafe nastiness.  This is the first step, I'll be 
expanding the memcmp optimizations shortly, covering things that
we really really wouldn't want simplifylibcalls to do.

llvm-svn: 92098
 2009-12-24 00:37:38 +00:00
Eric Christopher
ce677a909d Update objectsize intrinsic and associated dependencies. Fix 
lowering code and update testcases.

llvm-svn: 91979
 2009-12-23 02:51:48 +00:00
Evan Cheng
7cd6bfe549 Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size. 
llvm-svn: 91910
 2009-12-22 17:47:23 +00:00
Evan Cheng
bc37151dea Increase opportunities to optimize (brcond (srl (and c1), c2)). 
llvm-svn: 91717
 2009-12-18 21:31:31 +00:00
Evan Cheng
d97d025eba On recent Intel u-arch's, folding loads into some unary SSE instructions can 
be non-optimal. To be precise, we should avoid folding loads if the instructions
only update part of the destination register, and the non-updated part is not
needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these instructions breaks
the partial register dependency and it can improve performance. e.g.

movss (%rdi), %xmm0
cvtss2sd %xmm0, %xmm0

instead of
cvtss2sd (%rdi), %xmm0

An alternative method to break dependency is to clear the register first. e.g.
xorps %xmm0, %xmm0
cvtss2sd (%rdi), %xmm0

llvm-svn: 91672
 2009-12-18 07:40:29 +00:00
Dan Gohman
d97f165eb2 Tidy up this testcase and add test for tailcall optimization 
with unreachable.

llvm-svn: 91650
 2009-12-18 01:05:06 +00:00
Dan Gohman
c382d6519c Remove "tail" keywords. These calls are not intended to be tail calls. 
This protects this test from depending on codegen not performing the
tail call optimization by default.

llvm-svn: 91648
 2009-12-18 01:02:18 +00:00
Sean Callanan
06b6feb2e1 Instruction fixes, added instructions, and AsmString changes in the 
X86 instruction tables.

Also (while I was at it) cleaned up the X86 tables, removing tabs and
80-line violations.

This patch was reviewed by Chris Lattner, but please let me know if
there are any problems.

* X86*.td
	Removed tabs and fixed 80-line violations

* X86Instr64bit.td
	(IRET, POPCNT, BT_, LSL, SWPGS, PUSH_S, POP_S, L_S, SMSW)
		Added
	(CALL, CMOV) Added qualifiers
	(JMP) Added PC-relative jump instruction
	(POPFQ/PUSHFQ) Added qualifiers; renamed PUSHFQ to indicate
		that it is 64-bit only (ambiguous since it has no
		REX prefix)
	(MOV) Added rr form going the other way, which is encoded
		differently
	(MOV) Changed immediates to offsets, which is more correct;
		also fixed MOV64o64a to have to a 64-bit offset
	(MOV) Fixed qualifiers
	(MOV) Added debug-register and condition-register moves
	(MOVZX) Added more forms
	(ADC, SUB, SBB, AND, OR, XOR) Added reverse forms, which
		(as with MOV) are encoded differently
	(ROL) Made REX.W required
	(BT) Uncommented mr form for disassembly only
	(CVT__2__) Added several missing non-intrinsic forms
	(LXADD, XCHG) Reordered operands to make more sense for
		MRMSrcMem
	(XCHG) Added register-to-register forms
	(XADD, CMPXCHG, XCHG) Added non-locked forms
* X86InstrSSE.td
	(CVTSS2SI, COMISS, CVTTPS2DQ, CVTPS2PD, CVTPD2PS, MOVQ)
		Added
* X86InstrFPStack.td
	(COM_FST0, COMP_FST0, COM_FI, COM_FIP, FFREE, FNCLEX, FNOP,
	 FXAM, FLDL2T, FLDL2E, FLDPI, FLDLG2, FLDLN2, F2XM1, FYL2X,
	 FPTAN, FPATAN, FXTRACT, FPREM1, FDECSTP, FINCSTP, FPREM,
	 FYL2XP1, FSINCOS, FRNDINT, FSCALE, FCOMPP, FXSAVE,
	 FXRSTOR)
		Added
	(FCOM, FCOMP) Added qualifiers
	(FSTENV, FSAVE, FSTSW) Fixed opcode names
	(FNSTSW) Added implicit register operand
* X86InstrInfo.td
	(opaque512mem) Added for FXSAVE/FXRSTOR
	(offset8, offset16, offset32, offset64) Added for MOV
	(NOOPW, IRET, POPCNT, IN, BTC, BTR, BTS, LSL, INVLPG, STR,
	 LTR, PUSHFS, PUSHGS, POPFS, POPGS, LDS, LSS, LES, LFS,
	 LGS, VERR, VERW, SGDT, SIDT, SLDT, LGDT, LIDT, LLDT,
	 LODSD, OUTSB, OUTSW, OUTSD, HLT, RSM, FNINIT, CLC, STC,
	 CLI, STI, CLD, STD, CMC, CLTS, XLAT, WRMSR, RDMSR, RDPMC,
	 SMSW, LMSW, CPUID, INVD, WBINVD, INVEPT, INVVPID, VMCALL,
	 VMCLEAR, VMLAUNCH, VMRESUME, VMPTRLD, VMPTRST, VMREAD,
	 VMWRITE, VMXOFF, VMXON) Added
	(NOOPL, POPF, POPFD, PUSHF, PUSHFD) Added qualifier
	(JO, JNO, JB, JAE, JE, JNE, JBE, JA, JS, JNS, JP, JNP, JL,
	 JGE, JLE, JG, JCXZ) Added 32-bit forms
	(MOV) Changed some immediate forms to offset forms
	(MOV) Added reversed reg-reg forms, which are encoded
		differently
	(MOV) Added debug-register and condition-register moves
	(CMOV) Added qualifiers
	(AND, OR, XOR, ADC, SUB, SBB) Added reverse forms, like MOV
	(BT) Uncommented memory-register forms for disassembler
	(MOVSX, MOVZX) Added forms
	(XCHG, LXADD) Made operand order make sense for MRMSrcMem
	(XCHG) Added register-register forms
	(XADD, CMPXCHG) Added unlocked forms
* X86InstrMMX.td
	(MMX_MOVD, MMV_MOVQ) Added forms
* X86InstrInfo.cpp: Changed PUSHFQ to PUSHFQ64 to reflect table
	change

* X86RegisterInfo.td: Added debug and condition register sets
* x86-64-pic-3.ll: Fixed testcase to reflect call qualifier
* peep-test-3.ll: Fixed testcase to reflect test qualifier
* cmov.ll: Fixed testcase to reflect cmov qualifier
* loop-blocks.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-11.ll: Fixed testcase to reflect call qualifier
* 2009-11-04-SubregCoalescingBug.ll: Fixed testcase to reflect call
  qualifier
* x86-64-pic-2.ll: Fixed testcase to reflect call qualifier
* live-out-reg-info.ll: Fixed testcase to reflect test qualifier
* tail-opts.ll: Fixed testcase to reflect call qualifiers
* x86-64-pic-10.ll: Fixed testcase to reflect call qualifier
* bss-pagealigned.ll: Fixed testcase to reflect call qualifier
* x86-64-pic-1.ll: Fixed testcase to reflect call qualifier
* widen_load-1.ll: Fixed testcase to reflect call qualifier

llvm-svn: 91638
 2009-12-18 00:01:26 +00:00
Evan Cheng
aaf2f58a04 Re-enable 91381 with fixes. 
llvm-svn: 91489
 2009-12-16 00:53:11 +00:00
Dale Johannesen
365ae431a7 Do better with physical reg operands (typically, from inline asm) 
in local register allocator.  If a reg-reg copy has a phys reg
input and a virt reg output, and this is the last use of the phys
reg, assign the phys reg to the virt reg.  If a reg-reg copy has
a phys reg output and we need to reload its spilled input, reload
it directly into the phys reg than passing it through another reg.

Following 76208, there is sometimes no dependency between the def of
a phys reg and its use; this creates a window where that phys reg
can be used for spilling (this is true in linear scan also).  This
is bad and needs to be fixed a better way, although 76208 works too
well in practice to be reverted.  However, there should normally be
no spilling within inline asm blocks.  The patch here goes a long way
towards making this actually be true.

llvm-svn: 91485
 2009-12-16 00:29:41 +00:00
Kenneth Uildriks
c0ab5a6e88 For fastcc on x86, let ECX be used as a return register after EAX and EDX 
llvm-svn: 91410
 2009-12-15 03:27:52 +00:00
Evan Cheng
4adb4acc7b Disable 91381 for now. It's miscompiling ARMISelDAG2DAG.cpp. 
llvm-svn: 91405
 2009-12-15 03:07:11 +00:00
Evan Cheng
c531da60aa Make 91378 more conservative. 
1. Only perform (zext (shl (zext x), y)) -> (shl (zext x), y) when y is a constant. This makes sure it remove at least one zest.
2. If the shift is a left shift, make sure the original shift cannot shift out bits.

llvm-svn: 91399
 2009-12-15 03:00:32 +00:00
Evan Cheng
cd8f0de016 Use sbb x, x to materialize carry bit in a GPR. The result is all one's or all zero's. 
llvm-svn: 91381
 2009-12-15 00:53:42 +00:00
Evan Cheng
f3b2e55b34 Propagate zest through logical shift. 
llvm-svn: 91378
 2009-12-15 00:41:36 +00:00
Dan Gohman
57dc006590 Fix integer cast code to handle vector types. 
llvm-svn: 91362
 2009-12-14 23:40:38 +00:00
Evan Cheng
ee5b5917fd Disable r91104 for x86. It causes partial register stall which pessimize code in 32-bit. 
llvm-svn: 91223
 2009-12-12 20:03:14 +00:00
Dan Gohman
2e616e859b Implement vector widening, splitting, and scalarizing for SIGN_EXTEND_INREG. 
llvm-svn: 91158
 2009-12-11 21:31:27 +00:00
Dan Gohman
0a78e32f6b Change this to the correct PR number. 
llvm-svn: 91148
 2009-12-11 20:09:21 +00:00
Dan Gohman
b2cbb1e37e Fix the result type of SELECT nodes lowered from Select instructions with 
aggregate return values. This fixes PR5754.

llvm-svn: 91145
 2009-12-11 19:50:50 +00:00
Anton Korobeynikov
f8b2e2868e Honour setHasCalls() set from isel. 
This is used in some weird cases like general dynamic TLS model.
This fixes PR5723

llvm-svn: 91144
 2009-12-11 19:39:55 +00:00
Evan Cheng
4c304eebe9 Tests for 91103 and 91104. 
llvm-svn: 91105
 2009-12-11 06:02:21 +00:00
Evan Cheng
4b7cf3ed41 It's not safe to coalesce a move where src and dst registers have different subregister indices. e.g.: 
%reg16404:1<def> = MOV8rr %reg16412:2<kill>

llvm-svn: 91061
 2009-12-10 20:59:45 +00:00
Evan Cheng
bc633478bd Fix test. 
llvm-svn: 90988
 2009-12-09 22:24:42 +00:00
Evan Cheng
9e2442c0be Optimize splat of a scalar load into a shuffle of a vector load when it's legal. e.g. 
vector_shuffle (scalar_to_vector (i32 load (ptr + 4))), undef, <0, 0, 0, 0>
=>
vector_shuffle (v4i32 load ptr), undef, <1, 1, 1, 1>

iff ptr is 16-byte aligned (or can be made into 16-byte aligned).

llvm-svn: 90984
 2009-12-09 21:00:30 +00:00
David Greene
73ad44c6b6 Use FileCheck and set nounwind on calls. 
llvm-svn: 90790
 2009-12-07 19:40:26 +00:00
Dan Gohman
44e25ed254 Don't enable the post-RA scheduler on x86 except at -O3. In its 
current form, it is too expensive in compile time.

llvm-svn: 90781
 2009-12-07 19:04:31 +00:00
Bill Wendling
887646a585 Temporarily revert r90502. It was causing the llvm-gcc bootstrap on PPC to fail. 
llvm-svn: 90653
 2009-12-05 07:30:23 +00:00
Jakob Stoklund Olesen
7c5af26d12 Also attempt trivial coalescing for live intervals that end in a copy. 
The coalescer is supposed to clean these up, but when setting up parameters
for a function call, there may be copies to physregs. If the defining
instruction has been LICM'ed far away, the coalescer won't touch it.

The register allocation hint does not always work - when the register
allocator is backtracking, it clears the hints.

This patch takes care of a few more cases that r90163 missed.

llvm-svn: 90502
 2009-12-04 00:16:04 +00:00
Nate Begeman
3a9c51f256 Don't pull vector sext through both hands of a logical operation, since doing so prevents the fusion of vector sext and setcc into vsetcc. 
Add a testcase for the above transformation.
Fix a bogus use of APInt noticed while tracking this down.

llvm-svn: 90423
 2009-12-03 07:11:29 +00:00