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32751 Commits

Author SHA1 Message Date
Chris Lattner
525c0272aa make jump threading on a phi with undef inputs happen. 
llvm-svn: 83754
 2009-10-11 04:18:15 +00:00
Chris Lattner
8b521613d3 rewrite LCSSA to use SSAUpdate, to only return true if it modifies 
the IR, and to implement the FIXME'd optimization.

llvm-svn: 83748
 2009-10-11 02:53:37 +00:00
Chris Lattner
1b8c1d1d29 clean up and simplify some code. Don't use setvector when things will be 
inserted only once, just use vector.  Don't compute ExitBlocks unless we
need it, change std::sort to array_pod_sort.

llvm-svn: 83747
 2009-10-11 01:07:15 +00:00
Chris Lattner
37ff3c0ed1 switch GVN to use SSAUpdater. Besides removing a lot of complexity 
from GVN, this also speeds it up, inserts fewer PHI nodes (see the
testcase) and allows it to remove more loads (due to fewer PHI nodes
standing in the way).

llvm-svn: 83746
 2009-10-10 23:50:30 +00:00
Chris Lattner
0aa320ae4d add a simple helper method. 
llvm-svn: 83745
 2009-10-10 23:41:48 +00:00
Chris Lattner
acf73d9839 add ability for clients of SSAUpdater to find out about the 
PHI nodes inserted.

llvm-svn: 83744
 2009-10-10 23:15:24 +00:00
Chris Lattner
31d3137c01 remove dead code 
llvm-svn: 83742
 2009-10-10 23:04:12 +00:00
Chris Lattner
db4d523cca add the ability to get a rewritten value from the middle of a block, 
not just at the end.  Add a big comment explaining when this could
be useful (which never happens for jump threading).

llvm-svn: 83741
 2009-10-10 23:00:11 +00:00
Chris Lattner
9899ce267c rename GetValueInBlock -> GetValueAtEndOfBlock to better reflect 
what it does.

llvm-svn: 83740
 2009-10-10 22:41:58 +00:00
Anton Korobeynikov
1f9ff55cbc It seems that OR operation does not affect status reg at all. 
Remove impdef of SRW. This fixes PR4779

llvm-svn: 83739
 2009-10-10 22:17:47 +00:00
Chris Lattner
0561804097 use a typedef instead of spelling out an insane type. Yay for auto someday. 
llvm-svn: 83707
 2009-10-10 09:09:20 +00:00
Chris Lattner
75e5de9243 Change jump threading to use the new SSAUpdater class instead of 
DemoteRegToStack.  This makes it more efficient (because it isn't
creating a ton of load/stores that are eventually removed by a later
mem2reg), and more slightly more effective (because those load/stores
don't get in the way of threading).

llvm-svn: 83706
 2009-10-10 09:05:58 +00:00
Chris Lattner
9c5aa00411 Implement an efficient and fully general SSA update mechanism that 
works on unstructured CFGs.  This implements PR217, our oldest open PR.

llvm-svn: 83705
 2009-10-10 09:04:27 +00:00
Chris Lattner
317eb8ff20 random tidying 
llvm-svn: 83701
 2009-10-10 06:22:45 +00:00
Dan Gohman
605f85e0e6 Create a new InstrEmitter class for translating SelectionDAG nodes 
into MachineInstrs. This is mostly just moving the code from
ScheduleDAGSDNodesEmit.cpp into a new class. This decouples MachineInstr
emitting from scheduling.

llvm-svn: 83699
 2009-10-10 01:32:21 +00:00
Dan Gohman
3b025b778b Make getMachineNode return a MachineSDNode* instead of a generic SDNode* 
since it won't do any folding. This will help avoid some inconvenient
casting.

llvm-svn: 83698
 2009-10-10 01:29:16 +00:00
Dan Gohman
84a61978de Remove a no-longer-necessary #include. 
llvm-svn: 83697
 2009-10-10 00:36:09 +00:00
Dan Gohman
177b8de981 Replace X86's CanRematLoadWithDispOperand by calling the target-independent 
MachineInstr::isInvariantLoad instead, which has the benefit of being
more complete.

llvm-svn: 83696
 2009-10-10 00:34:18 +00:00
Dan Gohman
b98d95f4f9 Fix a missing initialization of PostRAScheduler's AA member. 
llvm-svn: 83695
 2009-10-10 00:15:38 +00:00
Dan Gohman
5141b26ffa The ScheduleDAG framework now requires an AliasAnalysis argument, though 
it isn't needed in the ScheduleDAGSDNodes schedulers.

llvm-svn: 83691
 2009-10-09 23:33:48 +00:00
Dan Gohman
168ae2c7d5 Mark the LDR instruction with isReMaterializable, as it is rematerializable 
when loading from an invariant memory location.

llvm-svn: 83688
 2009-10-09 23:28:27 +00:00
Dan Gohman
5bfc2416fe Factor out LiveIntervalAnalysis' code to determine whether an instruction 
is trivially rematerializable and integrate it into
TargetInstrInfo::isTriviallyReMaterializable. This way, all places that
need to know whether an instruction is rematerializable will get the
same answer.

This enables the useful parts of the aggressive-remat option by
default -- using AliasAnalysis to determine whether a memory location
is invariant, and removes the questionable parts -- rematting operations
with virtual register inputs that may not be live everywhere.

llvm-svn: 83687
 2009-10-09 23:27:56 +00:00
Devang Patel
c97c44b584 Extract scope information from the variable itself, instead of relying on alloca or llvm.dbg.declare location. 
While recording beginning of a function, use scope info from the first location entry instead of just relying on first location entry itself.

llvm-svn: 83684
 2009-10-09 22:42:28 +00:00
Jeffrey Yasskin
7edab17bef ExecutionEngine::clearGlobalMappingsFromModule failed to remove reverse 
mappings, which could cause errors and assert-failures.  This patch fixes that,
adds a test, and refactors the global-mapping-removal code into a single place.

llvm-svn: 83678
 2009-10-09 22:10:27 +00:00
Dan Gohman
14aaff93fc Add a const qualifier. 
llvm-svn: 83677
 2009-10-09 22:09:05 +00:00
Dale Johannesen
7691b73da0 Use names instead of numbers for some of the magic 
constants used in inlining heuristics (especially
those used in more than one file).  No functional change.

llvm-svn: 83675
 2009-10-09 21:42:02 +00:00
Kevin Enderby
430e05312d Added another bit of the ARM target assembler to llvm-mc to parse register 
lists.  Changed ARMAsmParser::MatchRegisterName to return -1 instead of 0 on
errors so 0-15 values could be returned as register numbers.  Also added the
rest of the arm register names to the currently hacked up version to allow more
testing.  Some changes to ARMAsmParser::ParseOperand to give different errors
for things not yet supported and some additions to the hacked
ARMAsmParser::MatchInstruction to allow more testing for now.

llvm-svn: 83673
 2009-10-09 21:12:28 +00:00
Dan Gohman
3005d6bf9f isTriviallyReMaterializable checks the 
TargetInstrDesc::isRematerializable flag, so it isn't necessary to do
this check in its callers.

llvm-svn: 83671
 2009-10-09 21:02:10 +00:00
Dan Gohman
f2ae9c6220 Fix the x86 test-shrink optimization so that it doesn't shrink comparisons 
when one of the bits being tested would end up being the sign bit in the
narrower type, and a signed comparison is being performed, since this would
change the result of the signed comparison. This fixes PR5132.

llvm-svn: 83670
 2009-10-09 20:35:19 +00:00
Dan Gohman
4fe1a982ed Add basic infrastructure and x86 support for preserving MachineMemOperand 
information when unfolding memory references.

llvm-svn: 83656
 2009-10-09 18:10:05 +00:00
Devang Patel
a772046766 Check invalid debug info for enums. This may happen when underlyng enum is optimized away. Eventually DwarfChecker will clean this up during llvm verification stage. 
llvm-svn: 83655
 2009-10-09 17:51:49 +00:00
Jim Grosbach
809d1bfdd3 when previous scratch register is killed, flag the value as no longer tracking 
llvm-svn: 83653
 2009-10-09 17:33:33 +00:00
Dan Gohman
731afb3b6e Revert r83606 and add comments explaining why it isn't safe. 
llvm-svn: 83649
 2009-10-09 16:35:06 +00:00
Evan Cheng
ec853b9ba5 Give Dan and my recent changes, machine LICM is now code size neutral. 
llvm-svn: 83624
 2009-10-09 06:31:25 +00:00
Evan Cheng
439044f330 Fix a logic error that caused non-rematable loop invariants loads to be licm'ed out of loop. 
llvm-svn: 83622
 2009-10-09 06:21:52 +00:00
Evan Cheng
b1f6b5fccc Reset kill markers after live interval is reconstructed. 
llvm-svn: 83608
 2009-10-09 01:17:11 +00:00
Dan Gohman
e81a040ce7 Preserve HasNSW and HasNUW when constructing SCEVs for Add and Mul 
instructions.

llvm-svn: 83606
 2009-10-09 00:41:22 +00:00
Dale Johannesen
10c870b46f When considering whether to inline Callee into Caller, 
and that will make Caller too big to inline, see if it
might be better to inline Caller into its callers instead.
This situation is described in PR 2973, although I haven't
tried the specific case in SPASS.

llvm-svn: 83602
 2009-10-09 00:11:32 +00:00
Dan Gohman
4cdd530887 Add the ability to track HasNSW and HasNUW on more kinds of SCEV expressions. 
llvm-svn: 83601
 2009-10-09 00:10:36 +00:00
Bob Wilson
8092fef09a Add codegen support for NEON vst4lane intrinsics with 128-bit vectors. 
llvm-svn: 83600
 2009-10-09 00:01:36 +00:00
Bob Wilson
979cb24a81 Add codegen support for NEON vst3lane intrinsics with 128-bit vectors. 
llvm-svn: 83598
 2009-10-08 23:51:31 +00:00
Bob Wilson
233992bc56 Add codegen support for NEON vst2lane intrinsics with 128-bit vectors. 
llvm-svn: 83596
 2009-10-08 23:38:24 +00:00
Bob Wilson
5b96a53ffe Add codegen support for NEON vld4lane intrinsics with 128-bit vectors. 
Also fix some copy-and-paste errors in previous changes.

llvm-svn: 83590
 2009-10-08 22:53:57 +00:00
Evan Cheng
8eb0ce14d9 Remove code that makes no sense. 
llvm-svn: 83589
 2009-10-08 22:42:35 +00:00
Bob Wilson
7209d78713 Add codegen support for NEON vld3lane intrinsics with 128-bit vectors. 
llvm-svn: 83585
 2009-10-08 22:27:33 +00:00
Douglas Gregor
57f2c22857 Update CMake build yet again after a source file was removed 
llvm-svn: 83575
 2009-10-08 21:24:34 +00:00
Bill Wendling
d47d348cdf It's possible for a global variable to be optimized out of a metadata object. So 
we should allow a "null" with this dyn_cast.

llvm-svn: 83573
 2009-10-08 20:52:51 +00:00
Anton Korobeynikov
f9c811c948 Use lower16 / upper16 imm modifiers to asmprint 32-bit imms splitted via movt/movw pair. 
llvm-svn: 83572
 2009-10-08 20:43:22 +00:00
Devang Patel
dcfcba3a71 Clear variable debug info map at the end of the function. 
llvm-svn: 83571
 2009-10-08 20:41:17 +00:00
Bob Wilson
3a55fe2105 Add codegen support for NEON vld2lane intrinsics with 128-bit vectors. 
llvm-svn: 83568
 2009-10-08 18:56:10 +00:00
Bob Wilson
0159d0d864 Clean up some unnecessary initializations. 
llvm-svn: 83566
 2009-10-08 18:52:56 +00:00
Bob Wilson
c62c9946e2 Clean up a comment (indentation was wrong). 
llvm-svn: 83565
 2009-10-08 18:51:31 +00:00
Bob Wilson
72c8f63e50 Add a SelectionDAG getTargetInsertSubreg convenience function, 
similar to getTargetExtractSubreg.

llvm-svn: 83564
 2009-10-08 18:49:46 +00:00
Devang Patel
e16aac2206 Do not record line number to implicitly mark start of function if function has arguments. Extra line number entries trip gdb in some cases. 
llvm-svn: 83563
 2009-10-08 18:48:03 +00:00
Richard Osborne
5e56dfa489 Add missing names for the XCore specific LADD and LSUB nodes. 
llvm-svn: 83556
 2009-10-08 17:14:57 +00:00
Dan Gohman
68e044e81a Add a form of addPreserved which takes a string argument, to allow passes 
to declare that they preserve other passes without needing to pull in
additional header file or library dependencies. Convert MachineFunctionPass
and CodeGenLICM to make use of this.

llvm-svn: 83555
 2009-10-08 17:00:02 +00:00
Richard Osborne
1719935e3f Add some peepholes for signed comparisons using ashr X, X, 32. 
llvm-svn: 83549
 2009-10-08 15:38:17 +00:00
Chris Lattner
41b5fd5218 remove LoopVR pass. According to Nick: 
"LoopVR's logic was copied into ScalarEvolution::getUnsignedRange and 
::getSignedRange. Please delete LoopVR."

llvm-svn: 83531
 2009-10-08 06:42:44 +00:00
Bob Wilson
276bdabb9a Add codegen support for NEON vst4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83526
 2009-10-08 05:18:18 +00:00
Jim Grosbach
9f57f9bee6 Cleanup up unused R3LiveIn tracking. 
llvm-svn: 83522
 2009-10-08 01:50:26 +00:00
Jim Grosbach
a3e1149941 Re-enable register scavenging in Thumb1 by default. 
llvm-svn: 83521
 2009-10-08 01:46:59 +00:00
Jim Grosbach
a8e8c8a28f bugfix. The target may use virtual registers that aren't tracked for re-use but are allocated by the scavenger. The re-use algorithm needs to watch for that. 
llvm-svn: 83519
 2009-10-08 01:09:45 +00:00
Bob Wilson
8aa1d328b5 Add codegen support for NEON vst3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83518
 2009-10-08 00:28:28 +00:00
Bob Wilson
958e4ae815 Add codegen support for NEON vst2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83513
 2009-10-08 00:21:01 +00:00
Jeffrey Yasskin
e36facef86 In instcombine's debug output, avoid printing ADD for instructions that are 
already on the worklist, and print Visited when an instruction is about to be
visited.  Net, on one input, this reduced the output size by at least 9x.

llvm-svn: 83510
 2009-10-08 00:12:24 +00:00
Bob Wilson
729cd181a2 Add codegen support for NEON vld4 intrinsics with <1 x i64> vectors. 
llvm-svn: 83508
 2009-10-07 23:54:04 +00:00
Bob Wilson
3cbf156518 Add codegen support for NEON vld3 intrinsics with <1 x i64> vectors. 
llvm-svn: 83506
 2009-10-07 23:39:57 +00:00
Bob Wilson
0ffa9679a5 Add codegen support for NEON vld2 intrinsics with <1 x i64> vectors. 
llvm-svn: 83502
 2009-10-07 22:57:01 +00:00
Jim Grosbach
cb905d28a8 reverting thumb1 scavenging default due to test failure while I figure out what's up. 
llvm-svn: 83501
 2009-10-07 22:49:41 +00:00
Chris Lattner
41e4cd7ef4 second half of lazy liveness removal. 
llvm-svn: 83500
 2009-10-07 22:49:30 +00:00
Dale Johannesen
ba62bb565d Fix handling of x86 'R' constraint. 
llvm-svn: 83499
 2009-10-07 22:47:20 +00:00
Jim Grosbach
cc952b2ff8 Enable thumb1 register scavenging by default. 
llvm-svn: 83496
 2009-10-07 22:26:31 +00:00
Jim Grosbach
a9d83ba92c Enable thumb1 register scavenging by default. 
llvm-svn: 83494
 2009-10-07 22:26:14 +00:00
Devang Patel
a7456a1335 Extract subprogram and compile unit information from the debug info attached to an instruction. 
llvm-svn: 83491
 2009-10-07 22:04:08 +00:00
Bob Wilson
e7173601a3 Add some instruction encoding bits for NEON load/store instructions. 
llvm-svn: 83490
 2009-10-07 21:53:04 +00:00
Eric Christopher
a42e55349d 80-column and whitespace fixes. 
llvm-svn: 83489
 2009-10-07 21:14:25 +00:00
Kevin Enderby
ef201aaa04 Fixed MCSectionMachO::ParseSectionSpecifier to allow an attribute of "none" so 
that a symbol stub section with no attributes can be parsed as in:
.section __TEXT,__picsymbolstub4,symbol_stubs,none,16

llvm-svn: 83488
 2009-10-07 20:57:20 +00:00
Bob Wilson
cee91108da Add codegen support for NEON vst4 intrinsics with 128-bit vectors. 
llvm-svn: 83486
 2009-10-07 20:49:18 +00:00
Bob Wilson
af14187764 Add codegen support for NEON vst3 intrinsics with 128-bit vectors. 
llvm-svn: 83484
 2009-10-07 20:30:08 +00:00
Jim Grosbach
0609c91ec4 grammar 
llvm-svn: 83483
 2009-10-07 19:08:36 +00:00
Bob Wilson
62a3e55cea Add codegen support for NEON vst2 intrinsics with 128-bit vectors. 
llvm-svn: 83482
 2009-10-07 18:47:39 +00:00
Jim Grosbach
5db951c6a2 add initializers for clarity. Add missing assignment of PrevLastUseOp. 
llvm-svn: 83481
 2009-10-07 18:44:24 +00:00
Owen Anderson
132727997c Remove LazyLiveness from the tree. It doesn't work right now, and I'm not going to have the time 
to finish it any time soon.  If someone's interested it, they can resurrect it from SVN history.

llvm-svn: 83480
 2009-10-07 18:40:17 +00:00
Bob Wilson
9bb47b3e5d Add codegen support for NEON vld4 intrinsics with 128-bit vectors. 
llvm-svn: 83479
 2009-10-07 18:09:32 +00:00
Kevin Enderby
c0d0a1ec58 Add another bit of the ARM target assembler to llvm-mc to parse registers 
with writeback, things like "sp!", etc.  Also added some more stuff to the
temporarily hacked methods ARMAsmParser::MatchRegisterName and
ARMAsmParser::MatchInstruction to allow more parser testing.

llvm-svn: 83477
 2009-10-07 18:01:35 +00:00
Dan Gohman
0447afe915 Replace some code for aggressive-remat with MachineInstr::isInvariantLoad, and 
teach it how to recognize invariant physical registers.

llvm-svn: 83476
 2009-10-07 17:47:20 +00:00
Dan Gohman
b95136e649 Replace TargetInstrInfo::isInvariantLoad and its target-specific 
implementations with a new MachineInstr::isInvariantLoad, which uses
MachineMemOperands and is target-independent. This brings MachineLICM
and other functionality to targets which previously lacked an
isInvariantLoad implementation.

llvm-svn: 83475
 2009-10-07 17:38:06 +00:00
Dan Gohman
aa09eaa3e8 Add a few simple MachineVerifier checks for MachineMemOperands. 
llvm-svn: 83474
 2009-10-07 17:36:00 +00:00
Bob Wilson
b38401ccef Add codegen support for NEON vld3 intrinsics with 128-bit vectors. 
llvm-svn: 83471
 2009-10-07 17:24:55 +00:00
Bob Wilson
a77f6a7814 Rearrange code for selecting vld2 intrinsics. No functionality change. 
This is just to be more consistent with the forthcoming code for vld3/4.

llvm-svn: 83470
 2009-10-07 17:23:09 +00:00
Jim Grosbach
61c5ce1bde Add register-reuse to frame-index register scavenging. When a target uses 
a virtual register to eliminate a frame index, it can return that register
and the constant stored there to PEI to track. When scavenging to allocate
for those registers, PEI then tracks the last-used register and value, and
if it is still available and matches the value for the next index, reuses
the existing value rather and removes the re-materialization instructions.
Fancier tracking and adjustment of scavenger allocations to keep more
values live for longer is possible, but not yet implemented and would likely
be better done via a different, less special-purpose, approach to the
problem.

eliminateFrameIndex() is modified so the target implementations can return
the registers they wish to be tracked for reuse.

ARM Thumb1 implements and utilizes the new mechanism. All other targets are
simply modified to adjust for the changed eliminateFrameIndex() prototype.

llvm-svn: 83467
 2009-10-07 17:12:56 +00:00
Devang Patel
c411175393 Do not assume that the module is set. 
llvm-svn: 83462
 2009-10-07 16:37:55 +00:00
Torok Edwin
6a66b4edd1 Add PR to this FIXME, looks like I didn't commit this change after all. 
llvm-svn: 83457
 2009-10-07 09:22:55 +00:00
Duncan Sands
27cb155f76 Make getPointerTo return a const PointerType* rather than 
an unqualified PointerType* because it seems more correct.

llvm-svn: 83454
 2009-10-07 07:35:19 +00:00
Eric Christopher
e6bebc66a7 Add FreeInst to the "is a call" check for Insts that are calls, but 
not intrinsics.

llvm-svn: 83441
 2009-10-07 00:54:08 +00:00
Dan Gohman
564b5f75ac Fix this comment. The loop header is the loop entry point. 
llvm-svn: 83437
 2009-10-07 00:33:10 +00:00
Anton Korobeynikov
aba66ae89b Add PseudoSourceValues for constpool stuff on ELF (Darwin should use something similar) 
and register spills.

llvm-svn: 83435
 2009-10-07 00:06:35 +00:00
Eric Christopher
8720c9ca69 While we still have a MallocInst treat it as a call like any other 
for inlining.

When MallocInst goes away this code will be subsumed as part of
calls and work just fine...

llvm-svn: 83434
 2009-10-07 00:02:18 +00:00
Kevin Enderby
2c772c1ae9 Added bits of the ARM target assembler to llvm-mc to parse some load instruction 
operands.  Some parsing of arm memory operands for preindexing and postindexing
forms including with register controled shifts.  This is a work in progress.

llvm-svn: 83424
 2009-10-06 22:26:42 +00:00
Bob Wilson
8cd1ea81c4 Add codegen support for NEON vld2 operations on quad registers. 
llvm-svn: 83422
 2009-10-06 22:01:59 +00:00