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55043ef46a
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15378 Commits

Author SHA1 Message Date
Chris Lattner
55043ef46a fix a long standing wart: all the ComplexPattern's were being 
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
 2010-09-21 20:31:19 +00:00
Chris Lattner
c153d48869 even though I'm about to rip it out, simplify the address mode stuff 
llvm-svn: 114468
 2010-09-21 19:41:58 +00:00
Chris Lattner
3dde58c15a convert a couple more places to use the new getStore() 
llvm-svn: 114463
 2010-09-21 18:51:21 +00:00
Chris Lattner
8cdc5e75f7 update a bunch of code to use the MachinePointerInfo version of getStore. 
llvm-svn: 114461
 2010-09-21 18:41:36 +00:00
Owen Anderson
97a8fdc19c When adding the carry bit to another value on X86, exploit the fact that the carry-materialization 
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460
 2010-09-21 18:41:19 +00:00
Bob Wilson
c4345abcc0 Define the TargetLowering::getTgtMemIntrinsic hook for ARM so that NEON load 
and store intrinsics are represented with MemIntrinsicSDNodes.

llvm-svn: 114454
 2010-09-21 17:56:22 +00:00
Chris Lattner
5f584efd31 eliminate some uses of the getStore overload. 
llvm-svn: 114453
 2010-09-21 17:50:43 +00:00
Chris Lattner
86b3f287ce eliminate an old SelectionDAG::getTruncStore method, propagating 
MachinePointerInfo around more.

llvm-svn: 114452
 2010-09-21 17:42:31 +00:00
Chris Lattner
cdfd993df0 propagate MachinePointerInfo through various uses of the old 
SelectionDAG::getExtLoad overload, and eliminate it.

llvm-svn: 114446
 2010-09-21 17:04:51 +00:00
Jim Grosbach
32cfcf5bba Fix errant printing of [v]ldm instructions that aren't a pop 
llvm-svn: 114445
 2010-09-21 16:45:31 +00:00
Gabor Greif
324a43436f Fix buglet when the TST instruction directly uses the AND result. 
I am unable to write a test for this case, help is solicited, though...
What I did is to tickle the code in the debugger and verify that we do the right thing.

llvm-svn: 114430
 2010-09-21 13:30:57 +00:00
Gabor Greif
99c07b1d95 Move the search for the appropriate AND instruction 
into OptimizeCompareInstr.
This necessitates the passing of CmpValue around,
so widen the virtual functions to accomodate.

No functionality changes.

llvm-svn: 114428
 2010-09-21 12:01:15 +00:00
Chris Lattner
4320dda4fb convert the targets off the non-MachinePointerInfo of getLoad. 
llvm-svn: 114410
 2010-09-21 06:44:06 +00:00
Chris Lattner
112cf9bc89 it's more elegant to put the "getConstantPool" and 
"getFixedStack" on the MachinePointerInfo class.  While
this isn't the problem I'm setting out to solve, it is the
right way to eliminate PseudoSourceValue, so lets go with it.

llvm-svn: 114406
 2010-09-21 06:22:23 +00:00
Chris Lattner
810a630851 update the X86 backend to use the MachinePointerInfo version of one 
of the getLoad methods.  This fixes at least one bug where an incorrect
svoffset is passed in (a potential combiner-aa miscompile).

llvm-svn: 114404
 2010-09-21 06:02:19 +00:00
Chris Lattner
80d9e51351 Fix a bug where the x86 backend would lower memcpy/memset of segment relative operations 
into non-segment-relative copies.

llvm-svn: 114402
 2010-09-21 05:43:34 +00:00
Chris Lattner
f94de5bf46 reimplement memcpy/memmove/memset lowering to use MachinePointerInfo 
instead of srcvalue/offset pairs.  This corrects SV info for mem 
operations whose size is > 32-bits.

llvm-svn: 114401
 2010-09-21 05:40:29 +00:00
Chris Lattner
2edbad8a3d convert targets to the new MF.getMachineMemOperand interface. 
llvm-svn: 114391
 2010-09-21 04:39:43 +00:00
Chris Lattner
ecdba24738 fix rdar://8453210, a crash handling a call through a GS relative load. 
For now, just disable folding the load into the call.

llvm-svn: 114386
 2010-09-21 03:37:00 +00:00
Jim Grosbach
cf90f8beb1 Simplify ARM callee-saved register handling by removing the distinction 
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635

llvm-svn: 114340
 2010-09-20 19:32:20 +00:00
Chris Lattner
3203bf3688 idiom recognition should catch this. 
llvm-svn: 114304
 2010-09-19 00:37:34 +00:00
Chris Lattner
ac0afb0fbe add a readme. 
llvm-svn: 114303
 2010-09-19 00:34:58 +00:00
NAKAMURA Takumi
a4a0276d4f X86Subtarget.h: Fix Cygwin's TD. 
llvm-svn: 114297
 2010-09-18 19:50:42 +00:00
Eric Christopher
2901b19344 Add the exit instruction to the PTX target. 
Patch by Che-Liang Chiou <clchiou@gmail.com>!

llvm-svn: 114294
 2010-09-18 18:52:28 +00:00
Michael J. Spencer
3a9b3aae55 Fix build. 
llvm-svn: 114292
 2010-09-18 17:54:37 +00:00
Eric Christopher
0c5e912e21 Thumb opcodes for thumb calls. 
llvm-svn: 114263
 2010-09-18 02:32:38 +00:00
Eric Christopher
c9fef312c8 Add addrmode5 fp load support. Swap float/thumb operand adding to handle 
thumb with floating point.

llvm-svn: 114256
 2010-09-18 01:59:37 +00:00
Eric Christopher
b6ce0ab878 Floating point stores have a 3rd addressing mode type. 
llvm-svn: 114254
 2010-09-18 01:23:38 +00:00
Jim Grosbach
c909422ee9 factor out a simple helper function to create a label for PC-relative 
instructions (PICADD, PICLDR, et.al.)

llvm-svn: 114243
 2010-09-18 00:05:05 +00:00
Jim Grosbach
a19f7799fb PC-relative pseudo instructions are lowered and printed directly. Any encounter 
with one in the generic printing code is an error.

llvm-svn: 114242
 2010-09-18 00:04:53 +00:00
Benjamin Kramer
1cad9b6521 Fix vmov.f64 disassembly on targets where sizeof(long) != 8. 
llvm-svn: 114240
 2010-09-17 23:48:07 +00:00
Jim Grosbach
8b988eb1d4 Add MC-inst handling for tPICADD 
llvm-svn: 114237
 2010-09-17 23:41:53 +00:00
Bob Wilson
670e1915c0 Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.

llvm-svn: 114233
 2010-09-17 22:59:05 +00:00
Jim Grosbach
8ae5cfffdd Teach the (non-MC) instruction printer to use the cannonical names for push/pop, 
and shift instructions on ARM. Update the tests to match.

llvm-svn: 114230
 2010-09-17 22:36:38 +00:00
Eric Christopher
716614f126 Rework arm fast isel branch and compare code. 
llvm-svn: 114226
 2010-09-17 22:28:18 +00:00
Jim Grosbach
6e477cd3d8 Hook up verbose asm comment printing for SOImm operands in MC printer 
llvm-svn: 114215
 2010-09-17 21:33:25 +00:00
Jim Grosbach
352a616f23 trailing whitespace 
llvm-svn: 114212
 2010-09-17 21:25:10 +00:00
Dan Gohman
aaed2c137f Avoid emitting a PIC base register if no PIC addresses are needed. 
This fixes rdar://8396318.

llvm-svn: 114201
 2010-09-17 20:24:24 +00:00
Jim Grosbach
1703c92cf5 Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim! 
llvm-svn: 114195
 2010-09-17 18:46:17 +00:00
Jim Grosbach
34a1adb4ea handle the upper16/lower16 target operand flags on symbol references for MC 
instruction lowering.

llvm-svn: 114191
 2010-09-17 18:25:25 +00:00
Chris Lattner
4bce01542c fix rdar://8444631 - encoder crash on 'enter' 
What a weird instruction.

llvm-svn: 114190
 2010-09-17 18:02:29 +00:00
Jim Grosbach
23ac157064 expand PICLDR MC lowering to handle other PICLDR and PICSTR versions. 
llvm-svn: 114183
 2010-09-17 16:25:52 +00:00
NAKAMURA Takumi
cfded91183 AlphaSchedule.td: 7bit-ize. 
llvm-svn: 114173
 2010-09-17 09:56:43 +00:00
Chris Lattner
73fc5e794d fix rdar://8438816 - unrecognized 'fildq' instruction 
llvm-svn: 114116
 2010-09-16 20:46:38 +00:00
Jim Grosbach
73f2f39001 MC-ization of the PICLDR pseudo. Next up, adding the other variants 
(PICLDRB, et. al.) and PICSTR*

llvm-svn: 114098
 2010-09-16 17:43:25 +00:00
Jim Grosbach
9131eb8bf0 Make sure to promote single precision floats to double before extracting them 
from the APFloat.

llvm-svn: 114096
 2010-09-16 17:37:30 +00:00
Kalle Raiskila
68e2c15954 Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction. 
This cleans up after the mess r108567 left in the CellSPU backend.
ORCvt-instruction were used to reinterpret registers, and the ORs were then
removed by isMoveInstr(). This patch now removes 350 instrucions of format:
	or $3, $3, $3
(from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is
checked for.

Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain.

llvm-svn: 114074
 2010-09-16 12:29:33 +00:00
Bob Wilson
622f0a7592 Remove support for "dregpair" operand modifier, now that it is no longer being 
used for anything.

llvm-svn: 114067
 2010-09-16 04:55:00 +00:00
Bob Wilson
76c730bdbd When expanding ARM pseudo registers, copy the existing predicate operands 
instead of using default predicates on the expanded instructions.

llvm-svn: 114066
 2010-09-16 04:25:37 +00:00
Jim Grosbach
1c3e1420e1 store MC FP immediates as a double instead of as an APFloat, thus avoiding an 
unnecessary dtor for MCOperand.

llvm-svn: 114064
 2010-09-16 03:45:21 +00:00