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11554 Commits

Author SHA1 Message Date
Devang Patel
efd9ac540a Use frameindex, if available, as a last resort to emit debug info for a parameter. 
llvm-svn: 118020
 2010-11-02 17:01:30 +00:00
Owen Anderson
9d85c89ade Add correct NEON encodings for vld2, vld3, and vld4 basic variants. 
llvm-svn: 117997
 2010-11-02 01:24:55 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bob Wilson
411b511ac0 Add support for alignment operands on VLD1-lane instructions. 
This is another part of the fix for Radar 8599955.

llvm-svn: 117976
 2010-11-01 23:40:51 +00:00
Bob Wilson
8f0cf81f09 Add VLD1-lane testcases for quad-register types. 
llvm-svn: 117975
 2010-11-01 23:40:46 +00:00
Bob Wilson
b6bc135df8 Add NEON VLD1-lane instructions. Partial fix for Radar 8599955. 
llvm-svn: 117964
 2010-11-01 22:04:05 +00:00
Bill Wendling
af717e3c58 Use ARM-style comments. 
llvm-svn: 117955
 2010-11-01 21:16:39 +00:00
Owen Anderson
47f0efad86 When folding away a (shl (shr)) pair, we need to check that the bits that will BECOME the low 
bits are zero, not that the current low bits are zero.  Fixes <rdar://problem/8606771>.

llvm-svn: 117953
 2010-11-01 21:08:20 +00:00
Bill Wendling
4340c9449a When we look at instructions to convert to setting the 's' flag, we need to look 
at more than those which define CPSR. You can have this situation:

(1)  subs  ...
(2)  sub   r6, r5, r4
(3)  movge ...
(4)  cmp   r6, 0
(5)  movge ...

We cannot convert (2) to "subs" because (3) is using the CPSR set by
(1). There's an analogous situation here:

(1)  sub   r1, r2, r3
(2)  sub   r4, r5, r6
(3)  cmp   r4, ...
(5)  movge ...
(6)  cmp   r1, ...
(7)  movge ...

We cannot convert (1) to "subs" because of the intervening use of CPSR.

llvm-svn: 117950
 2010-11-01 20:41:43 +00:00
Owen Anderson
09920faec7 Use ARM-style comment syntax. 
llvm-svn: 117941
 2010-11-01 18:33:37 +00:00
Bob Wilson
a9c593e696 NEON does not support truncating vector stores. Radar 8598391. 
llvm-svn: 117940
 2010-11-01 18:31:39 +00:00
Owen Anderson
dbba9bcc36 Covert this test to .s form. 
llvm-svn: 117939
 2010-11-01 18:30:39 +00:00
Owen Anderson
38af2df6e5 Convert this test to .s form. 
llvm-svn: 117938
 2010-11-01 18:26:43 +00:00
Owen Anderson
8d4bfde002 Covert this test to .s form. 
llvm-svn: 117937
 2010-11-01 18:13:11 +00:00
Owen Anderson
d5757a8585 Covert this test to .s form. 
llvm-svn: 117935
 2010-11-01 18:03:16 +00:00
Rafael Espindola
eff645265a Fix test. 
llvm-svn: 117932
 2010-11-01 17:10:53 +00:00
Rafael Espindola
2f114f8430 Write the line info to .debug_line. 
llvm-svn: 117930
 2010-11-01 17:07:14 +00:00
Jim Grosbach
76910aa62f Mark ARM subtarget features that are available for the assembler. 
llvm-svn: 117929
 2010-11-01 16:59:54 +00:00
Rafael Espindola
a7f92c500c Add support for .value. 
llvm-svn: 117922
 2010-11-01 15:29:07 +00:00
Rafael Espindola
7a38cb0144 Implement .weakref. 
llvm-svn: 117911
 2010-11-01 14:28:48 +00:00
Bill Wendling
a59bb03780 More tests to XFAIL. The arm-and-txt-peephole.ll test passes even when the 
peephole optimizer is disabled. That's not good at all.

llvm-svn: 117905
 2010-11-01 05:59:43 +00:00
Bill Wendling
bfdbe6b369 Disable because peephole is disabled. 
llvm-svn: 117903
 2010-11-01 05:48:44 +00:00
Chris Lattner
d595d1f4d7 "mov[zs]x (mem), GR16" are not ambiguous: the mem 
must be 8 bits.  Support this memory form.

llvm-svn: 117902
 2010-11-01 05:41:10 +00:00
Chris Lattner
81d051481e Implement enough of the missing instalias support to get 
aliases installed and working.  They now work when the
matched pattern and the result instruction have exactly
the same operand list.

This is now enough for us to define proper aliases for
movzx and movsx, implementing rdar://8017633 and PR7459.

Note that we do not accept instructions like:
  movzx 0(%rsp), %rsi

GAS accepts this instruction, but it doesn't make any
sense because we don't know the size of the memory
operand.  It could be 8/16/32 bits.

llvm-svn: 117901
 2010-11-01 05:34:34 +00:00
Owen Anderson
ccef9fc4fc Convert this test to .s form. 
llvm-svn: 117900
 2010-11-01 05:23:58 +00:00
Chris Lattner
0a4807eefc make the asm matcher emitter reject instructions that have comments 
in their asmstring.  Fix the two x86 "NOREX" instructions that have them.
If these comments are important, the instlowering stuff can print them.

llvm-svn: 117897
 2010-11-01 04:44:29 +00:00
Chris Lattner
54892b4d8d fix an encoding mismatch where "sal %eax, 1" was not using the short encoding 
for shl.  Caught by inspection.

llvm-svn: 117820
 2010-10-30 18:13:10 +00:00
Chris Lattner
f0bb464017 add a test for the ud2a alias. 
llvm-svn: 117803
 2010-10-30 17:01:25 +00:00
Duncan Sands
a7198342e7 If a function does a volatile load from a global constant, do not 
consider it to be readonly.  In fact, don't even consider it to be
readonly if it does a volatile load from an AllocaInst either (it
is debatable as to whether readonly would be correct or not in this
case; play safe for the moment).  This fixes PR8279.

llvm-svn: 117783
 2010-10-30 12:59:44 +00:00
Bob Wilson
183c466006 Overhaul memory barriers in the ARM backend. Radar 8601999. 
There were a number of issues to fix up here:
* The "device" argument of the llvm.memory.barrier intrinsic should be
used to distinguish the "Full System" domain from the "Inner Shareable"
domain.  It has nothing to do with using DMB vs. DSB instructions.
* The compiler should never need to emit DSB instructions.  Remove the
ARMISD::SYNCBARRIER node and also remove the instruction patterns for DSB.
* Merge the separate DMB/DSB instructions for options only used for the
disassembler with the default DMB/DSB instructions.  Add the default
"full system" option ARM_MB::SY to the ARM_MB::MemBOpt enum.
* Add a separate ARMISD::MEMBARRIER_MCR node for subtargets that implement
a data memory barrier using the MCR instruction.
* Fix up encodings for these instructions (except MCR).
I also updated the tests and added a few new ones to check for DMB options
that were not currently being exercised.

llvm-svn: 117756
 2010-10-30 00:54:37 +00:00
Bill Wendling
b68e0d0ee3 Some instructions end with an "ls" prefix, but it doesn't indicate that they are 
conditional. Check for those instructions explicitly.

llvm-svn: 117747
 2010-10-29 23:50:21 +00:00
Evan Cheng
d81c33d91e Teach machine cse to eliminate instructions with multiple physreg uses and defs. rdar://8610857. 
llvm-svn: 117745
 2010-10-29 23:36:03 +00:00
Rafael Espindola
0d9ac34ffa Be more strict on when we produce an undefined reference. In gas a file with 
just

.type   foo,@object

will produce an undefined reference to foo. On the other hand, a file with
just

.weakref bar, foo

will not. It is somewhat hard to support both in MC since both statements
should create the symbols. It should be possible if we really need to by
adding to the flags, but hopefully that is not necessary.

With this patch we do not produce a undefined reference in any of those cases.
The assembly file needs an actual use for the undefined reference to be
present.

This is in preparation for a patch implementing .weakref.

llvm-svn: 117735
 2010-10-29 23:09:31 +00:00
Bob Wilson
d7f24e831f Change instcombine's getShuffleMask to represent undef with negative values. 
This code had previously used 2*N, where N is the mask length, to represent
undef.  That is not safe because the shufflevector operands may have more
than N elements -- they don't have to match the result type.

llvm-svn: 117721
 2010-10-29 22:03:05 +00:00
Bob Wilson
d67dddb134 Remove DAG combiner patch to fold vector splats. Instcombiner does it now. 
llvm-svn: 117720
 2010-10-29 22:03:02 +00:00
Bob Wilson
996353fb5d Make instcombine a little more aggressive in combining vector shuffles. 
Allow splats even if they don't match either of the original shuffles,
possibly due to undef entries in the shuffles masks.  Radar 8597790.
Also fix some 80-column violations.

llvm-svn: 117719
 2010-10-29 22:02:50 +00:00
Owen Anderson
14cf6bfa0f Update testcase since we're no longer doing the constant forwarding inline with correlated value propagation. 
llvm-svn: 117712
 2010-10-29 21:18:23 +00:00
Owen Anderson
ccbb8e7b65 Convert this test to .s form. 
llvm-svn: 117708
 2010-10-29 20:39:19 +00:00
Owen Anderson
7e3af87961 Convert this test to .s form. 
llvm-svn: 117704
 2010-10-29 20:23:45 +00:00
Owen Anderson
1b3d8432b1 Convert this test to .s form. 
llvm-svn: 117699
 2010-10-29 20:17:07 +00:00
Owen Anderson
fc007fef16 Convert this test to .s form. 
llvm-svn: 117696
 2010-10-29 20:12:34 +00:00
Owen Anderson
2119e59322 Covert this test to .s form. 
llvm-svn: 117694
 2010-10-29 19:56:07 +00:00
Owen Anderson
b75ef99b0c Convert this test to .s form. 
llvm-svn: 117693
 2010-10-29 19:51:11 +00:00
Owen Anderson
9e3265d3da Convert this test to .s form. 
llvm-svn: 117690
 2010-10-29 19:45:32 +00:00
Owen Anderson
f9a6495d0a Convert this test to .s form. 
llvm-svn: 117689
 2010-10-29 19:37:05 +00:00
Owen Anderson
8fb42c665e Convert this test to .s form. 
llvm-svn: 117686
 2010-10-29 19:17:08 +00:00
Owen Anderson
230358caab Convert this test to .s form. 
llvm-svn: 117685
 2010-10-29 19:09:08 +00:00
Owen Anderson
4176d55f79 Covert this test to .s form. 
llvm-svn: 117684
 2010-10-29 19:05:26 +00:00
Owen Anderson
cc7d9dcb52 Convert this test to .s form. 
llvm-svn: 117683
 2010-10-29 18:58:30 +00:00
Owen Anderson
4e1532000b Convert this test to .s form. 
llvm-svn: 117682
 2010-10-29 18:48:59 +00:00
Owen Anderson
a84837747c Convert this file to less fragile .s form. 
llvm-svn: 117681
 2010-10-29 18:41:40 +00:00
Owen Anderson
8e290aafbd Replace this test with the less fragile .s version. Still XFAIL'd, since the ASM parser doesn't parse vabal yet. 
llvm-svn: 117679
 2010-10-29 18:31:26 +00:00
Owen Anderson
840931e8ed Covert this test to a .s file to reduce fragility. 
llvm-svn: 117676
 2010-10-29 18:18:40 +00:00
Evan Cheng
392d2cbdcc Avoiding overly aggressive latency scheduling. If the two nodes share an 
operand and one of them has a single use that is a live out copy, favor the
one that is live out. Otherwise it will be difficult to eliminate the copy
if the instruction is a loop induction variable update. e.g.

BB:
sub r1, r3, #1
str r0, [r2, r3]
mov r3, r1
cmp
bne BB

=>

BB:
str r0, [r2, r3]
sub r3, r3, #1
cmp
bne BB

This fixed the recent 256.bzip2 regression.

llvm-svn: 117675
 2010-10-29 18:09:28 +00:00
NAKAMURA Takumi
a1491c3c47 test/Scripts/macho-dump: Make hack for Python-2.4. [PR7995] 
With Python-2.4, Reader::read64 always returns (unexpected) long integer.
FileCheck detects failure on test/MC/MachO among '0' and '0L'.

CentOS5(aka RHEL5 clone) provides python-2.4.

llvm-svn: 117637
 2010-10-29 01:14:16 +00:00
Dan Gohman
753c9ce807 Teach memdep to use pointsToConstantMemory to determine that loads 
from constant memory don't alias any stores.

llvm-svn: 117636
 2010-10-29 01:14:04 +00:00
Owen Anderson
9930e7bcb6 Convert this test to a .s file, so that it's not sensitive to codegen changes. 
llvm-svn: 117633
 2010-10-29 01:01:56 +00:00
Dan Gohman
a592a0f539 Add a basic testcase for TBAA-aware DSE. 
llvm-svn: 117632
 2010-10-29 00:54:02 +00:00
Chris Lattner
115cd02d22 add simple support for addrmode5 operands, allowing 
vldr.64 to work.  I have no idea if this is fully right, but 
it is in the right direction.

llvm-svn: 117626
 2010-10-29 00:27:31 +00:00
Andrew Trick
e77cdffcf3 The ARM jit cannot handle these tests as of 2010-10-27. 
(A PR will be linked to this rev.)

llvm-svn: 117620
 2010-10-29 00:23:43 +00:00
Rafael Espindola
913ce7ebc8 Improvements to .section parsing: 
* If we have a M or a G, reject sections without the type
* Only parse the flag specific arguments if we have M or G
* Parse the corresponding arguments for M and G

We ignore the G arguments and flag for now.

llvm-svn: 117608
 2010-10-28 21:33:33 +00:00
Chris Lattner
1917294eb5 most simple arm instructions match correctly now, 
it looks like we're not handling [] operands though

llvm-svn: 117607
 2010-10-28 21:31:07 +00:00
Chris Lattner
bd838d16e5 fix the asmmatcher generator to handle targets with no RegisterPrefix 
(like ARM) correctly.  With this change, we can now match "bx lr"
because we recognize lr as a register.

llvm-svn: 117606
 2010-10-28 21:28:42 +00:00
Rafael Espindola
b562975139 Add support for the .string directive. 
llvm-svn: 117592
 2010-10-28 20:02:27 +00:00
Rafael Espindola
f230319275 Defined weak symbols should have non-zero value. 
llvm-svn: 117585
 2010-10-28 19:39:57 +00:00
Rafael Espindola
862d688cbd Fix relocations with renamed symbols. 
llvm-svn: 117575
 2010-10-28 19:08:03 +00:00
Rafael Espindola
e62cf892ae Aliases defined with .symver should copy the binding of the symbols they alias. 
Move the existing patching for undefined symbols so that all the patching
is done in the same function.

llvm-svn: 117570
 2010-10-28 18:33:03 +00:00
Bob Wilson
65124cd7c7 Teach the DAG combiner to fold a splat of a splat. Radar 8597790. 
Also do some minor refactoring to reduce indentation.

llvm-svn: 117558
 2010-10-28 17:06:14 +00:00
Roman Divacky
8555f153e9 Implement .equ directive as a synonym to .set. 
llvm-svn: 117553
 2010-10-28 16:22:58 +00:00
Duncan Sands
60f016b0f9 Testcase for PR8494 (invalid bitcode crashing the bitcode reader). 
llvm-svn: 117552
 2010-10-28 15:57:30 +00:00
Rafael Espindola
ff7e4e4e43 Implement R_X86_64_DTPOFF32. 
llvm-svn: 117548
 2010-10-28 15:11:03 +00:00
Rafael Espindola
1d1ff5485c Implement TLSLD. 
llvm-svn: 117547
 2010-10-28 15:02:40 +00:00
Rafael Espindola
8372247e83 Implement DTPOFF. 
llvm-svn: 117546
 2010-10-28 14:48:59 +00:00
Rafael Espindola
c44c5b374a Implement TLSLDM. 
llvm-svn: 117544
 2010-10-28 14:37:09 +00:00
Rafael Espindola
d8ef67f8b9 Implement VK_GOTNTPOFF and switch RelocNeedsGOT to use VariantKind. 
llvm-svn: 117543
 2010-10-28 14:22:44 +00:00
Evan Cheng
bc4588c439 Re-commit 117518 and 117519 now that ARM MC test failures are out of the way. 
llvm-svn: 117531
 2010-10-28 06:47:08 +00:00
Evan Cheng
72be097417 Disable most of the ARM vfp / NEON MC tests. These are too fragile to be useful. 
I'll work with Jim, Owen, and Bill on an alternative testing strategy until
the assembly parser is available.

llvm-svn: 117530
 2010-10-28 06:46:17 +00:00
NAKAMURA Takumi
b89aaebdde test/Transforms/SimplifyLibCalls/floor.ll: Mark as XFAIL:win32 due to lack of nearbyintf on MSVC. [PR8466] 
llvm-svn: 117529
 2010-10-28 06:46:04 +00:00
Evan Cheng
fdc80a0316 Revert 117518 and 117519 for now. They changed scheduling and cause MC tests to fail. Ugh. 
llvm-svn: 117520
 2010-10-28 02:00:25 +00:00
Evan Cheng
5c358e02ea - Assign load / store with shifter op address modes the right itinerary classes. 
- For now, loads of [r, r] addressing mode is the same as the
  [r, r lsl/lsr/asr #] variants. ARMBaseInstrInfo::getOperandLatency() should
  identify the former case and reduce the output latency by 1.
- Also identify [r, r << 2] case. This special form of shifter addressing mode
  is "free".

llvm-svn: 117519
 2010-10-28 01:49:06 +00:00
Dale Johannesen
b78530f9b0 Fix pastos in handling of AVX cvttsd2si, PR8491. 
Bruno, please review, but I'm pretty sure this is right.
Patch by Alex Mac!

llvm-svn: 117514
 2010-10-28 00:35:54 +00:00
Owen Anderson
e75f7c5419 Add correct NEON encodings for vtbl and vtbx. 
llvm-svn: 117513
 2010-10-28 00:18:46 +00:00
Owen Anderson
008116cb71 Add correct NEON encodings for vext, vtrn, vuzp, and vzip. 
llvm-svn: 117512
 2010-10-27 23:56:39 +00:00
Dale Johannesen
454b9243bd Teach InstCombine not to use Add and Neg on FP. PR 8490. 
llvm-svn: 117510
 2010-10-27 23:45:18 +00:00
Evan Cheng
44d2802e1d Shifter ops are not always free. Do not fold them (especially to form 
complex load / store addressing mode) when they have higher cost and
when they have more than one use.

llvm-svn: 117509
 2010-10-27 23:41:30 +00:00
Owen Anderson
27049dbce3 Tests for NEON encoding of vrev. 
llvm-svn: 117502
 2010-10-27 22:54:49 +00:00
Owen Anderson
9437a20a72 Provide correct encodings for NEON vcvt, which has its own special immediate encoding 
for specifying fractional bits for fixed point conversions.

llvm-svn: 117501
 2010-10-27 22:49:00 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Rafael Espindola
68ec803155 Add support for R_386_TLS_GD, R_386_TLS_LE_32, R_386_TLS_IE and R_386_TLS_LE. 
llvm-svn: 117494
 2010-10-27 21:23:52 +00:00
Kevin Enderby
a53cc6a764 Added the x86 instruction ud2b (2nd official undefined instruction). 
llvm-svn: 117485
 2010-10-27 20:46:49 +00:00
Bob Wilson
cdc8dff3ac SelectionDAG shuffle nodes do not allow operands with different numbers of 
elements than the result vector type.  So, when an instruction like:

%8 = shufflevector <2 x float> %4, <2 x float> %7, <4 x i32> <i32 1, i32 0, i32 3, i32 2>

is translated to a DAG, each operand is changed to a concat_vectors node that appends 2 undef elements.  That is:

shuffle [a,b], [c,d] is changed to:
shuffle [a,b,u,u], [c,d,u,u]

That's probably the right thing for x86 but for NEON, we'd much rather have:

shuffle [a,b,c,d], undef

Teach the DAG combiner how to do that transformation for ARM.  Radar 8597007.

llvm-svn: 117482
 2010-10-27 20:38:28 +00:00
Rafael Espindola
2ea1239070 Implement R_X86_64_GOTTPOFF, R_X86_64_TLSGD and R_X86_64_TPOFF32. 
llvm-svn: 117481
 2010-10-27 20:28:07 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Rafael Espindola
4db628cd34 Set default type and flags for .init and .fini. 
llvm-svn: 117471
 2010-10-27 18:45:20 +00:00
Owen Anderson
dbed42aff5 Tests for NEON encoding of vmovl, vmovn, vqmovn, and vqmovun. 
llvm-svn: 117469
 2010-10-27 18:17:12 +00:00
Owen Anderson
25d75e80ba Tests for NEON encoding of vcls, vclz, and vcnt. 
llvm-svn: 117466
 2010-10-27 18:05:25 +00:00
Owen Anderson
a5643da004 Tests for NEON encoding of vneg and vqneg. 
llvm-svn: 117463
 2010-10-27 17:57:26 +00:00
Rafael Espindola
ca302c994a Produce an error for an invalid use of .symver. 
llvm-svn: 117462
 2010-10-27 17:56:18 +00:00
Owen Anderson
32da0e6e3f Tests for NEON encoding of vabs and vqabs. 
llvm-svn: 117460
 2010-10-27 17:50:07 +00:00
Owen Anderson
c8757eb137 Add correct NEON encodings for vsli and vsri. 
llvm-svn: 117459
 2010-10-27 17:40:08 +00:00
Owen Anderson
e64b7187a9 Add correct NEON encodings for vsra and vrsra. 
llvm-svn: 117458
 2010-10-27 17:29:29 +00:00
Rafael Espindola
58a0ea80a4 Symbols defined as the difference of other two end up in the ABS section. 
llvm-svn: 117451
 2010-10-27 16:04:30 +00:00
Rafael Espindola
23d05a8675 Add support for the .symver directive. This is really ugly, but most of it is 
contained in the ELF object writer.

llvm-svn: 117448
 2010-10-27 15:18:17 +00:00
Kevin Enderby
74a2614673 Yet another tweak to X86 instructions to add ud2a as an alias to ud2 
(still to add ud2b).

llvm-svn: 117435
 2010-10-27 03:01:02 +00:00
Kevin Enderby
d22f3b9de7 Another tweak to X86 instructions to add the missing flex instruction (without 
the wait prefix).

llvm-svn: 117434
 2010-10-27 02:53:04 +00:00
Kevin Enderby
e812b356cc Tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler
allows for these instructions.  Done differently than in r117031 that
caused a valgrind error which was later reverted.

llvm-svn: 117433
 2010-10-27 02:32:19 +00:00
Kevin Enderby
d5235bb45c Added some aliases to the fcomip and fucompi Intel instructions. So that llvm-mc 
will accept versions that the darwin assembler allows.  Forms ending in "pi" and
forms without all the operands.

llvm-svn: 117427
 2010-10-27 00:59:28 +00:00
Owen Anderson
1dc05f20e2 Add correct NEON encodings for vqshl, vqshrn, vqshrun, vqrshl, vqshrn, and vqrshrun. 
llvm-svn: 117411
 2010-10-26 22:50:46 +00:00
Owen Anderson
55c0bad37d Correct NEON encodings for vshrn, vrshl, vrshr, vrshrn. 
llvm-svn: 117402
 2010-10-26 21:58:41 +00:00
Jim Grosbach
afc1e913c0 FileCheck'ize 
llvm-svn: 117401
 2010-10-26 21:26:47 +00:00
Owen Anderson
71deab0da0 Add tests for NEON encoding of vshll. 
llvm-svn: 117399
 2010-10-26 21:21:47 +00:00
Owen Anderson
31c1429a2c Tests for NEON encoding of vshr. 
llvm-svn: 117396
 2010-10-26 21:08:42 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Rafael Espindola
50d3c29c30 Add support for .ident. 
llvm-svn: 117389
 2010-10-26 19:35:47 +00:00
Owen Anderson
ee9f7e6c20 Tests for NEON encoding of vrecpe, vrecps, vrsqrte, and vsqrts. 
llvm-svn: 117385
 2010-10-26 18:43:13 +00:00
Owen Anderson
9e49cae184 Tests for NEON encodings of vpmin and vpmax. 
llvm-svn: 117382
 2010-10-26 18:31:47 +00:00
Owen Anderson
d8e5d26a56 Add correct NEON encoding for vpadal. 
llvm-svn: 117380
 2010-10-26 18:18:03 +00:00
Owen Anderson
1940ad62ca Tests for NEON encoding of vpadd and vpaddl. 
llvm-svn: 117377
 2010-10-26 18:04:51 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Rafael Espindola
e38790534e Implement some relaxations for arithmetic instructions. The limitation 
on RIP relative relocations looks artificial, but this is a superset of
what we were able to do before.

llvm-svn: 117364
 2010-10-26 14:09:12 +00:00
Kalle Raiskila
64680cd5b8 Change v64 datalayout in SPU. 
The SPU ABI does not mention v64, and all examples
in C suggest v128 are treated similarily to arrays, 
we use array alignment for v64 too. This makes the 
alignment of e.g. [2 x <2 x i32>] behave "intuitively"
and similar to as if the elements were e.g. i32s.

This also makes an "unaligned store" test to be 
aligned, with different (but functionally equivalent)
code generated.

llvm-svn: 117360
 2010-10-26 10:45:47 +00:00
Bob Wilson
309484bb46 When the "true" and "false" blocks of a diamond if-conversion are the same, 
do not double-count the duplicate instructions by counting once from the
beginning and again from the end.  Keep track of where the duplicates from
the beginning ended and don't go past that point when counting duplicates
at the end.  Radar 8589805.

This change causes one of the MC/ARM/simple-fp-encoding tests to produce
different (better!) code without the vmovne instruction being tested.
I changed the test to produce vmovne and vmoveq instructions but moving
between register files in the opposite direction.  That's not quite the same
but predicated versions of those instructions weren't being tested before,
so at least the test coverage is not any worse, just different.

llvm-svn: 117333
 2010-10-26 00:02:24 +00:00
Owen Anderson
67684a0bae Tests for NEON encoding of vmax. 
llvm-svn: 117327
 2010-10-25 23:45:34 +00:00
Owen Anderson
10a13e5063 Tests for NEON encoding of vmin. 
llvm-svn: 117326
 2010-10-25 23:35:36 +00:00
Dale Johannesen
2566d39d07 An stdcall function calling a non-stdcall function 
cannot use tailcall.  PR 8461.

llvm-svn: 117322
 2010-10-25 22:17:05 +00:00
Owen Anderson
e5e0dcd665 Add correct encodings for NEON vabal. 
llvm-svn: 117315
 2010-10-25 21:29:04 +00:00
Owen Anderson
3eff0b86a5 Add correct NEON encodings for vaba. 
llvm-svn: 117309
 2010-10-25 20:52:57 +00:00
Owen Anderson
a45478aef9 Tests for NEON encoding of vabdl. 
llvm-svn: 117303
 2010-10-25 20:36:28 +00:00
Owen Anderson
3e03c142fd Add tests for NEON encoding of vabd. 
llvm-svn: 117302
 2010-10-25 20:29:27 +00:00
Daniel Dunbar
5cbb066ea3 MC/AsmParser: Fix relative precedence of {+,-} and comparison ops. 
llvm-svn: 117299
 2010-10-25 20:18:56 +00:00
Daniel Dunbar
97fa30f53b MC/AsmLexer: Fix bug in source location for Slash token. 
llvm-svn: 117298
 2010-10-25 20:18:53 +00:00
Daniel Dunbar
9de1fe630b tweak test. 
llvm-svn: 117297
 2010-10-25 20:18:49 +00:00
Daniel Dunbar
4e52e15868 MC/AsmParser: Rewrite test to actually check some parts of expression parsing, 
now that we have macros and friends. Uncovered a bug in macro expansion...

llvm-svn: 117295
 2010-10-25 20:18:41 +00:00
Owen Anderson
61f5b3f2dc Attempt to provide correct encodings for NEON vbit and vbif, even though we can't test them at the moment. 
llvm-svn: 117294
 2010-10-25 20:17:22 +00:00
Owen Anderson
072692331e Provide correct NEON encodings for vbsl. 
llvm-svn: 117293
 2010-10-25 20:13:13 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Owen Anderson
1693a4c5d5 Add tests for NEON encoding of vtst. 
llvm-svn: 117277
 2010-10-25 18:10:34 +00:00
Owen Anderson
ba261b092c Add NEON encoding tests for vcgt and vacgt. 
llvm-svn: 117276
 2010-10-25 18:03:59 +00:00
Rafael Espindola
5748458e7d Add support for emitting ARM file attributes. 
llvm-svn: 117275
 2010-10-25 17:50:35 +00:00
Owen Anderson
3a5f798790 Add tests for NEON encodings of vcge and vacge. 
llvm-svn: 117274
 2010-10-25 17:49:32 +00:00
Owen Anderson
757022131f Add a warning about our inability to test the encoding of vceq with immediate zero. 
llvm-svn: 117273
 2010-10-25 17:33:02 +00:00
Owen Anderson
8ad139dce6 Add tests for NEON encoding of vceq. 
llvm-svn: 117270
 2010-10-25 17:20:26 +00:00
Owen Anderson
d7968b1d9c Add tests for NEON encoding of vsubhn and vrsubhn. 
llvm-svn: 117269
 2010-10-25 17:12:46 +00:00
Dan Gohman
96e34e87ca Fix a case where instcombine was stripping metadata (and alignment) 
from stores when folding in bitcasts.

llvm-svn: 117265
 2010-10-25 16:16:27 +00:00
Duncan Sands
5b25503aab Fix PR8445: a block with no predecessors may be the entry block, in which case 
it isn't unreachable and should not be zapped.  The check for the entry block
was missing in one case: a block containing a unwind instruction.  While there,
do some small cleanups: "M" is not a great name for a Function* (it would be
more appropriate for a Module*), change it to "Fn"; use Fn in more places.

llvm-svn: 117224
 2010-10-24 12:23:30 +00:00
Owen Anderson
2710687363 Add tests for NEON encoding of vqsub. 
llvm-svn: 117214
 2010-10-23 18:02:16 +00:00
Michael J. Spencer
87c8212d41 X86: Emit _fltused instead of __fltused on Windows x64. 
llvm-svn: 117205
 2010-10-23 09:06:59 +00:00
Mikhail Glushenkov
858566ac15 Remove -llvmc-temp-hack from tblgen. 
llvm-svn: 117197
 2010-10-23 07:32:53 +00:00
Owen Anderson
1e091f8c58 Add tests for NEON encoding of vhsub. 
llvm-svn: 117189
 2010-10-22 23:58:22 +00:00
Jim Grosbach
7de028efd2 Add a CMP test. 
llvm-svn: 117187
 2010-10-22 23:48:01 +00:00
Owen Anderson
3416940e43 Add tests for NEON encoding of vsubw. 
llvm-svn: 117186
 2010-10-22 23:46:07 +00:00
Jim Grosbach
1df6f11838 tidy up 
llvm-svn: 117185
 2010-10-22 23:46:04 +00:00
Owen Anderson
a9c3c6c610 Add tests for NEON encoding of vsubl. 
llvm-svn: 117183
 2010-10-22 23:36:36 +00:00
Owen Anderson
8bc3d6ec45 Add tests for NEON encoding of vsub. 
llvm-svn: 117177
 2010-10-22 23:21:04 +00:00
Owen Anderson
2d807f4ed0 Add tests for NEON encoding of vqdmlsl. 
llvm-svn: 117173
 2010-10-22 23:08:47 +00:00
Owen Anderson
593d941f2f Add tests for NEON encoding of vmlsl. 
llvm-svn: 117171
 2010-10-22 23:02:27 +00:00
Jim Grosbach
de52e11864 tidy up. 
llvm-svn: 117166
 2010-10-22 22:15:48 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach
172f52fb3d Remove duplicate test. 
llvm-svn: 117158
 2010-10-22 22:04:28 +00:00
Jim Grosbach
3cb3f83374 tidy up. 
llvm-svn: 117157
 2010-10-22 22:01:56 +00:00
Jim Grosbach
4366bb4852 FileCheck-ize a few tests. 
llvm-svn: 117156
 2010-10-22 21:55:03 +00:00
Bob Wilson
0290dbe7d4 Teach instcombine to set the alignment arguments for NEON load/store intrinsics. 
llvm-svn: 117154
 2010-10-22 21:41:48 +00:00
Owen Anderson
8c38a57413 Add tests for the correct encoding of NEON vmls. 
llvm-svn: 117145
 2010-10-22 20:31:24 +00:00
Owen Anderson
424434414e Add correct NEON encodings for vqdmlal. 
llvm-svn: 117134
 2010-10-22 19:35:48 +00:00
Jim Grosbach
10195e9b73 Add the encoding information for the rest of the ARM mode multiply instructions. 
llvm-svn: 117133
 2010-10-22 19:15:30 +00:00
Owen Anderson
2bbdc62e17 Provide correct encodings for NEON vmlal. 
llvm-svn: 117131
 2010-10-22 19:05:25 +00:00
Owen Anderson
ada2b33321 Provide correct NEON encodings for vmla. 
llvm-svn: 117126
 2010-10-22 18:54:37 +00:00
Stuart Hastings
772bf86028 Temporarily revert r117079; it broke a tester. Radar 6635085. 
llvm-svn: 117122
 2010-10-22 18:44:22 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Owen Anderson
399ec622e4 Add testscases for encoding of NEON vdqmull. 
llvm-svn: 117115
 2010-10-22 17:57:37 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
NAKAMURA Takumi
00eaed4fe8 test/Makefile: Force lit -j1 on Cygwin. 
lit -jN causes crash on Cygwin's python.

llvm-svn: 117093
 2010-10-22 09:40:37 +00:00
Andrew Trick
b9e8700beb Reverting r117031 to cleanup valgrind errors. 
It doesn't look like anything is wrong with the checkin,
but the new test cases expose a mem bug in AsmParser.

llvm-svn: 117087
 2010-10-22 03:58:29 +00:00
Sean Callanan
9a40554de4 Fixed handling of immediate operand sizes, which 
weren't properly reflecting the OperandSize attribute
of the instruction leading to improper decoding of
certain instructions with the 66H prefix.  Also added
a test case for this.

llvm-svn: 117084
 2010-10-22 01:24:11 +00:00
Stuart Hastings
c6b2d77375 Test case for r117075. Radar 6635085. 
llvm-svn: 117079
 2010-10-21 22:43:32 +00:00
Owen Anderson
bba3b2050e Add tests for NEON encoding of vmull. 
llvm-svn: 117077
 2010-10-21 22:19:53 +00:00
Jim Grosbach
7c42142b71 ARM binary encodings for MVN variants. 
llvm-svn: 117076
 2010-10-21 22:19:32 +00:00
Owen Anderson
653fc9304a Add tests for NEON encoding of vqdmulh and vqrdmulh. 
llvm-svn: 117074
 2010-10-21 22:05:33 +00:00
Jim Grosbach
cb41e97b5c ARM Binary encoding information for BFC/BFI instructions. 
llvm-svn: 117072
 2010-10-21 22:03:21 +00:00
Owen Anderson
2c25ce7af1 Add tests for NEON vmul encoding. 
llvm-svn: 117069
 2010-10-21 21:51:58 +00:00
Owen Anderson
b0bddd3282 Rename this test to better reflect its contents. 
llvm-svn: 117067
 2010-10-21 21:40:15 +00:00
Owen Anderson
77c5078d4a Add tests for NEON encodings of vaddhn and vraddhn. 
llvm-svn: 117064
 2010-10-21 20:56:57 +00:00
Owen Anderson
ba6ee305cf Add tests for NEON encodings of vqadd, which was already correctly encoded. 
llvm-svn: 117059
 2010-10-21 20:42:04 +00:00
Owen Anderson
51a6bc3b27 Add correct NEON encodings for vhadd and vrhadd. 
llvm-svn: 117047
 2010-10-21 18:55:04 +00:00
Owen Anderson
dce283c7db Add correct encodings for NEON vaddw.s* and vaddw.u*. 
llvm-svn: 117040
 2010-10-21 18:20:25 +00:00
Owen Anderson
7d90c72edf Provide correct NEON encodings for vaddl.u* and vaddl.s*. 
llvm-svn: 117039
 2010-10-21 18:09:17 +00:00
Rafael Espindola
69c973fbfd Do not recurse into symbol refs that have a variant kind. This prevents us 
from losing the variant when producing a relocation on an alias.

llvm-svn: 117037
 2010-10-21 18:00:20 +00:00
Kevin Enderby
c63105a064 More tweaks to X86 instructions to allow the 'w' suffix in places it makes 
sense, when the instruction takes the 16-bit ax register or m16 memory
location.  These changes to llvm-mc matches what the darwin assembler allows
for these instructions.  Also added the missing flex (without the wait prefix)
and ud2a as an alias to ud2 (still to add ud2b).

llvm-svn: 117031
 2010-10-21 17:16:46 +00:00
Bill Wendling
8b2c8a5856 Fix whitespace. 
llvm-svn: 117002
 2010-10-21 06:25:08 +00:00
Wesley Peck
d646a12f25 Recommit 116986 with capitalization typo fixed. 
llvm-svn: 116993
 2010-10-21 03:57:26 +00:00
Andrew Trick
4a3b819c1f putback r116983 and fix simple-fp-encoding.ll tests 
llvm-svn: 116992
 2010-10-21 03:40:16 +00:00
Wesley Peck
3478e641b9 Reverting the commit 116986. It was breaking the build on llvm-x86_64-linux though it 
compiles on OS X. I'll ensure that it builds on a linux machine before committing
again.

llvm-svn: 116991
 2010-10-21 03:34:22 +00:00
Owen Anderson
7da515c665 Revert r116983, which is breaking all the buildbots. 
llvm-svn: 116987
 2010-10-21 03:11:16 +00:00
Wesley Peck
c50372298d Major update of the MicroBlaze backend. The new features are: 
1. A delay slot filler that searches for valid instructions
       to fill the delay slot with. Previously NOPs would always
       be inserted into delay slots.
    2. Support for MC based instruction printer added.
    3. Support for MC based machine code generation and ELF
       file generation. ELF file generation does not yet
       completely work as much of the ELF support infrastructure
       is still x86/x86-64 specific.
    4. General clean up of the MBlaze backend code. Much of the
       tablegen code has been cleanup and simplified.

Bug Fixes:
    1. Removed duplicate periods from subtarget feature descriptions.
    2. Many of the instructions had bad machine code information
       in the tablegen files. Much of this has been fixed.

llvm-svn: 116986
 2010-10-21 03:09:55 +00:00
Evan Cheng
0b9eaaf45d Add missing scheduling itineraries for transfers between core registers and VFP registers. 
llvm-svn: 116983
 2010-10-21 01:12:00 +00:00
Owen Anderson
a685f8e90a Implement correct encodings for NEON vadd, both integer and floating point. 
llvm-svn: 116981
 2010-10-21 00:48:00 +00:00
Bill Wendling
c7ef66fcf2 Add encoding for moving a value between two ARM core registers and a doublework 
extension register.

llvm-svn: 116970
 2010-10-20 23:37:40 +00:00
Bill Wendling
0f96ff63b3 Add encodings for movement between ARM core registers and single-precision 
registers.

llvm-svn: 116961
 2010-10-20 22:44:54 +00:00
Dan Gohman
afaaf2f56b Add some comments. 
llvm-svn: 116957
 2010-10-20 22:04:02 +00:00
Evan Cheng
9a06e4c7c8 More accurate estimate / tracking of register pressure. 
- Initial register pressure in the loop should be all the live defs into the
  loop. Not just those from loop preheader which is often empty.
- When an instruction is hoisted, update register pressure from loop preheader
  to the original BB.
- Treat only use of a virtual register as kill since the code is still SSA.

llvm-svn: 116956
 2010-10-20 22:03:58 +00:00
Dale Johannesen
a324c8c6bd Fix crash introduced in 116852. 8573915. 
llvm-svn: 116955
 2010-10-20 22:03:37 +00:00
Jason W Kim
3dc75181ae Cut unneeded global variable. 
llvm-svn: 116953
 2010-10-20 22:01:39 +00:00
Rafael Espindola
0a50bbaee1 Handle _GLOBAL_OFFSET_TABLE_ correctly. 
llvm-svn: 116932
 2010-10-20 16:46:08 +00:00
Dale Johannesen
ee87cbe4e9 Enable using vdup for vector constants which are splat of 
integers by default, and remove the controlling flag, now
that LICM will hoist such vdup's.  8003375.

llvm-svn: 116852
 2010-10-19 20:00:17 +00:00
Evan Cheng
1c8dafd12a Re-enable register pressure aware machine licm with fixes. Hoist() may have 
erased the instruction during LICM so UpdateRegPressureAfter() should not
reference it afterwards.

llvm-svn: 116845
 2010-10-19 18:58:51 +00:00
Jason W Kim
ccbc75257a Fixing r116753 r116756 r116777 
The failures in r116753 r116756 were caused by a python issue -
Python likes to append 'L' suffix to stringified numbers if the number
is larger than a machine int. Unfortunately, this causes a divergence of
behavior between 32 and 64 bit python versions.

I re-crafted elf-dump/common_dump to take care of these issues by:

1. always printing 0x (makes for easy sed/regex)
2. always print fixed length (exactly 2 + numBits/4 digits long)
   by mod ((2^numBits) - 1)
3. left-padded with '0'

There is a residual common routine that is also used by
macho-dump (dataToHex) , so I left the 'section_data' test values alone.

llvm-svn: 116823
 2010-10-19 17:39:10 +00:00
Daniel Dunbar
6ff550c84d Revert r116781 "- Add a hook for target to determine whether an instruction def 
is", which breaks some nightly tests.

llvm-svn: 116816
 2010-10-19 17:14:24 +00:00
Mikhail Glushenkov
0c09a4b97f GlobalOpt: EvaluateFunction() must not evaluate stores to weak_odr globals. 
Fixes PR8389.

llvm-svn: 116812
 2010-10-19 16:47:23 +00:00
Che-Liang Chiou
1733b45be9 Add test case mov.ll for PTX device function 
llvm-svn: 116806
 2010-10-19 13:21:51 +00:00
Rafael Espindola
2ba55832f3 Fix PR8300 by remembering to keep the bitcast in all cases. 
llvm-svn: 116788
 2010-10-19 02:02:57 +00:00
Evan Cheng
9c3f6f486e - Add a hook for target to determine whether an instruction def is 
"long latency" enough to hoist even if it may increase spilling. Reloading
  a value from spill slot is often cheaper than performing an expensive
  computation in the loop. For X86, that means machine LICM will hoist
  SQRT, DIV, etc. ARM will be somewhat aggressive with VFP and NEON
  instructions.
- Enable register pressure aware machine LICM by default.

llvm-svn: 116781
 2010-10-19 00:55:07 +00:00
Eric Christopher
a039d14f9b Speculatively revert 116753 and 116756 to attempt to fix the bots. 
llvm-svn: 116777
 2010-10-19 00:19:49 +00:00
Bob Wilson
c3fb4427f4 Support alignment for NEON vld-lane and vst-lane instructions. 
llvm-svn: 116776
 2010-10-19 00:16:32 +00:00
Kevin Enderby
8a3030c6af Added a few tweaks to the Intel Descriptor-table support instructions to allow 
word forms and suffixed versions to match the darwin assembler in 32-bit and
64-bit modes.  This is again for use just with assembly source for llvm-mc .

llvm-svn: 116773
 2010-10-19 00:01:44 +00:00
Eric Christopher
5850afe5f2 Revert r116220 - thus turning arm fast isel back on by default. 
llvm-svn: 116762
 2010-10-18 22:53:53 +00:00
Jason W Kim
1f55cad0e3 Get rid of unneeded FormatOutput global variable 
llvm-svn: 116756
 2010-10-18 21:59:38 +00:00
Jason W Kim
a60bcd8bb1 Changed elf-dump to output hex format by default. 
Also updated tests. 

llvm-svn: 116753
 2010-10-18 21:32:41 +00:00
Dan Gohman
6efd04961b Don't pass the raw invalid pointer used to represent conflicting 
TBAA information to AliasAnalysis.

llvm-svn: 116751
 2010-10-18 21:28:00 +00:00
Dan Gohman
ed8fc1b23f Add a basic testcase for TBAA-aware LICM. 
llvm-svn: 116745
 2010-10-18 21:00:09 +00:00
Rafael Espindola
9a98116bb7 Implement R_386_GOT32. 
llvm-svn: 116744
 2010-10-18 20:47:21 +00:00
Rafael Espindola
c75defe576 Relocate with .bss instead of using the symbol. Matches gas behavior. 
llvm-svn: 116741
 2010-10-18 20:25:33 +00:00
Dan Gohman
2427af80d1 Run tbaa before basicaa, since that's how it's expected to be used. 
llvm-svn: 116731
 2010-10-18 18:45:59 +00:00
Rafael Espindola
7cc236c87f Produce ELF::R_386_GOTPC relocations. 
llvm-svn: 116728
 2010-10-18 18:36:12 +00:00
Dan Gohman
7820328076 Make TypeBasedAliasAnalysis default to doing nothing, with a command-line 
option to enable it.

llvm-svn: 116722
 2010-10-18 18:17:47 +00:00
Dan Gohman
6aff5b94ff Make BasicAliasAnalysis a normal AliasAnalysis implementation which 
does normal initialization and normal chaining. Change the default
AliasAnalysis implementation to NoAlias.

Update StandardCompileOpts.h and friends to explicitly request
BasicAliasAnalysis.

Update tests to explicitly request -basicaa.

llvm-svn: 116720
 2010-10-18 18:04:47 +00:00
Kevin Enderby
cb18d38b76 Added a handful of x86-32 instructions that were missing so that llvm-mc would 
be more complete.  These are only expected to be used by llvm-mc with assembly
source so there is no pattern, [], in the .td files.  Most are being added to
X86InstrInfo.td as Chris suggested and only comments about register uses are
added.  Suggestions welcome on the .td changes as I'm not sure on every detail
of the x86 records.  More missing instructions will be coming.

llvm-svn: 116716
 2010-10-18 17:04:36 +00:00
Rafael Espindola
bf9107e924 Produce a R_386_PLT32 when needed. Moved the default cases of switches to the 
start for consistency.

llvm-svn: 116715
 2010-10-18 16:58:03 +00:00
Rafael Espindola
4a7459403a Handle GOTOFF correctly on i386. 
llvm-svn: 116711
 2010-10-18 16:38:04 +00:00
Kalle Raiskila
3cdfdd9383 Improve lowering of sext to i128 on SPU. 
The old algorithm inserted a 'rotqmbyi' instruction which was
both redundant and wrong - it made shufb select bytes from the
wrong end of the input quad.

llvm-svn: 116701
 2010-10-18 09:34:19 +00:00
Rafael Espindola
be5c52d2dc Add a MCObjectFormat class so that code common to all targets that use a 
single object format can be shared.

This also adds support for

mov zed+(bar-foo), %eax

on ELF and COFF targets.

llvm-svn: 116675
 2010-10-16 18:23:53 +00:00
Benjamin Kramer
9c81b592e7 Unbreak test on non-COFF targets. 
llvm-svn: 116669
 2010-10-16 11:27:13 +00:00
Michael J. Spencer
f9a7c39ecc MC-COFF: Add support for default-null weak externals. 
llvm-svn: 116666
 2010-10-16 08:25:57 +00:00
Michael J. Spencer
e57b670425 X86-Windows: Emit an undefined global __fltused symbol when targeting Windows 
if any floating point arguments are passed to an external function.

llvm-svn: 116665
 2010-10-16 08:25:41 +00:00
Owen Anderson
4373b4516b Generalize MemCpyOpt's handling of call slot forwarding to function properly when the call slot 
forwarding is implemented with a load/store pair rather than a memcpy.

llvm-svn: 116637
 2010-10-15 22:52:12 +00:00
Mikhail Glushenkov
65e099eb3c llvmc: Add a test for the -c flag. 
llvm-svn: 116611
 2010-10-15 19:30:49 +00:00
Jim Grosbach
67f94c42d8 ARM mode encoding information for UBFX and SBFX instructions. 
llvm-svn: 116588
 2010-10-15 17:15:16 +00:00
Jakob Stoklund Olesen
7c0c554397 FileCheckize 
llvm-svn: 116581
 2010-10-15 16:06:42 +00:00
Rafael Espindola
9b114d966a Refactor code a bit and avoid creating unnecessary entries in the string 
map.

llvm-svn: 116579
 2010-10-15 15:39:06 +00:00
Bob Wilson
fcc42f2f3a ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563
 2010-10-15 03:23:44 +00:00
Jim Grosbach
608e4fd221 Simplify test file a bit. 
llvm-svn: 116540
 2010-10-14 23:32:44 +00:00
Jim Grosbach
26842cb893 Add testcase for RRX and ASRS (which effectively tests MOVs, since those 
are just forms of that instruction).

llvm-svn: 116538
 2010-10-14 23:29:18 +00:00
Jim Grosbach
804505c7d4 Refactor the MOVsr[al]_flag and RRX pseudo-instructions to really be pseudos 
and let the ARMExpandPseudoInsts pass fix them up into the real (MOVs)
instruction form.

llvm-svn: 116534
 2010-10-14 22:57:13 +00:00
Jim Grosbach
29dc23398f Tweak the ARM backend to use the RRX mnemonic instead of the 'mov a, b, rrx' 
pseudonym.

llvm-svn: 116512
 2010-10-14 20:43:44 +00:00
Jim Grosbach
73c78f8790 MOVi16 and MOVT ARM mode encodings. 
llvm-svn: 116498
 2010-10-14 18:54:27 +00:00
Rafael Espindola
2cdc3d6235 Remove some code duplication. 
llvm-svn: 116484
 2010-10-14 16:34:44 +00:00
Mikhail Glushenkov
bfe6fa281e Comments. 
llvm-svn: 116476
 2010-10-14 13:43:20 +00:00
Bill Wendling
2c335d364c Add support for vmov.f64/.f32 encoding. There's a bit of a hack going on 
here. The f32 in FCONSTS is handled as a double instead of a float in the
code. So the encoding of the immediate into the instruction isn't exactly in
line with the documentation in that regard. But given that we know it's handled
as a double, it doesn't cause any harm.

llvm-svn: 116471
 2010-10-14 02:33:26 +00:00
Bill Wendling
33a2ecd5e4 Add encoding for 'fmstat'. 
llvm-svn: 116466
 2010-10-14 01:19:34 +00:00
Bill Wendling
cd41f22ec1 - Add encodings for multiply add/subtract instructions in all their glory. 
- Add missing patterns for some multiply add/subtract instructions.
- Add encodings for VMRS and VMSR.

llvm-svn: 116464
 2010-10-14 01:02:08 +00:00