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Commit Graph

118659 Commits

Author SHA1 Message Date
Benjamin Kramer
572b3d1ca5 [DAGCombiner] Preserve the exact bit when simplifying SRA to SRL.
Allows more aggressive folding of ashr/shl pairs.

llvm-svn: 240788
2015-06-26 14:51:49 +00:00
Benjamin Kramer
c1ddcdcab5 [DAGCombine] fold (X >>?,exact C1) << C2 --> X << (C2-C1)
Instcombine also does this but many opportunities only become visible
after GEPs are lowered.

llvm-svn: 240787
2015-06-26 14:51:36 +00:00
Aaron Ballman
15cdc33a19 Silencing spurious MSVC C4189 warnings regarding local variables that are initialized but not used; NFC. This bug has been reported to Microsoft (https://connect.microsoft.com/VisualStudio/feedback/details/1475983).
llvm-svn: 240786
2015-06-26 14:51:22 +00:00
Rafael Espindola
db0cb3137a Rename getObjectFile to getObject for consistency.
llvm-svn: 240785
2015-06-26 14:51:16 +00:00
Rafael Espindola
c8e8a6fc0f Simplify isSymbolList64Bit. NFC.
llvm-svn: 240784
2015-06-26 14:11:54 +00:00
Rafael Espindola
8a0e03cffd Simplify isObject. NFC.
llvm-svn: 240783
2015-06-26 13:24:23 +00:00
Toma Tabacu
c9c0571983 [mips] [IAS] Add partial support for the ULW pseudo-instruction.
Summary:
This only adds support for ULW of an immediate address with/without a source register.
It does not include support for ULW of the address of a symbol.

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D9663

llvm-svn: 240782
2015-06-26 13:20:17 +00:00
Rafael Espindola
b7cf20c06e Implement elf_section_iterator and getELFType().
And with those, simplify getSymbolNMTypeChar.

llvm-svn: 240780
2015-06-26 13:11:15 +00:00
Rafael Espindola
e0fa1f9b53 Expose getFlags via ELFSectionRef.
llvm-svn: 240779
2015-06-26 12:44:10 +00:00
Rafael Espindola
4ef84ab21f Add a ELFSectionRef class and use it to expose getSectionType.
llvm-svn: 240778
2015-06-26 12:33:37 +00:00
Rafael Espindola
400aa8ffe6 Simplify getSymbolType.
This is still a really odd function. Most calls are in object format specific
contexts and should probably be replaced with a more direct query, but at least
now this is not too obnoxious to use.

llvm-svn: 240777
2015-06-26 12:18:49 +00:00
Javed Absar
d4144d8279 [ARM] Cortex-R4F is not VFPOnlySP
Cortex-R4F TRM states that fpu supports both single and double precision.
This patch corrects the information in ARM.td file and corresponding test.

Reviewers: rengolin

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D10763

llvm-svn: 240776
2015-06-26 12:14:56 +00:00
Rafael Espindola
386eef5084 Make getOther ELF only.
No other format has this field.

llvm-svn: 240774
2015-06-26 11:39:57 +00:00
Rafael Espindola
9b4c1d87c6 Optimize the creation of mapping symbols.
No need to create two symbols just to assign one to the other.

llvm-svn: 240773
2015-06-26 11:31:13 +00:00
Sergey Dmitrouk
0913967b80 Do not ignore projects/LLVMBuild.txt in git repo
Without explicit exception for the path, it matches projects/* rule.

llvm-svn: 240771
2015-06-26 10:13:56 +00:00
David Majnemer
f499207c44 [X86] Cleanup X86WindowsTargetObjectFile::getSectionForConstant
No functionality changed, just keeping things clean.

llvm-svn: 240762
2015-06-26 07:03:12 +00:00
Hao Liu
bfe90ecb2e [InterleavedAccess] Fix failures "undefined type 'llvm::raw_ostream'" on windows.
llvm-svn: 240760
2015-06-26 04:38:21 +00:00
Hao Liu
fc6114fe0f [ARM] Lower interleaved memory accesses to vldN/vstN intrinsics.
This patch also adds a function to calculate the cost of interleaved memory accesses.

E.g. Lower an interleaved load:
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr, align 4
        %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
        %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
     into:
        %vld2 = { <4 x i32>, <4 x i32> } call llvm.arm.neon.vld2(%ptr, 4)
        %vec0 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 0
        %vec1 = extractelement { <4 x i32>, <4 x i32> } %vld2, i32 1

E.g. Lower an interleaved store:
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr, align 4
     into:
        %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
        %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
        %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
        call void llvm.arm.neon.vst3(%ptr, %sub.v0, %sub.v1, %sub.v2, 4)

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240755
2015-06-26 02:45:36 +00:00
Hao Liu
1dc438bc4e [AArch64] Lower interleaved memory accesses to ldN/stN intrinsics. This patch also adds a function to calculate the cost of interleaved memory accesses.
E.g. Lower an interleaved load:
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle %wide.vec, undef, <0, 2, 4, 6>
        %v1 = shuffle %wide.vec, undef, <1, 3, 5, 7>
     into:
        %ld2 = { <4 x i32>, <4 x i32> } call llvm.aarch64.neon.ld2(%ptr)
        %vec0 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 0
        %vec1 = extractelement { <4 x i32>, <4 x i32> } %ld2, i32 1

E.g. Lower an interleaved store:
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
     into:
        %sub.v0 = shuffle <8 x i32> %v0, <8 x i32> v1, <0, 1, 2, 3>
        %sub.v1 = shuffle <8 x i32> %v0, <8 x i32> v1, <4, 5, 6, 7>
        %sub.v2 = shuffle <8 x i32> %v0, <8 x i32> v1, <8, 9, 10, 11>
        call void llvm.aarch64.neon.st3(%sub.v0, %sub.v1, %sub.v2, %ptr)

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240754
2015-06-26 02:32:07 +00:00
Hao Liu
00aff8cc17 [InterleavedAccess] Add a pass InterleavedAccess to identify interleaved memory accesses and transform into target specific intrinsics.
E.g. An interleaved load (Factor = 2):
        %wide.vec = load <8 x i32>, <8 x i32>* %ptr
        %v0 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <0, 2, 4, 6>
        %v1 = shuffle <8 x i32> %wide.vec, <8 x i32> undef, <1, 3, 5, 7>
It can be transformed into a ld2 intrinsic in AArch64 backend or a vld2 intrinsic in ARM backend.

E.g. An interleaved store (Factor = 3):
        %i.vec = shuffle <8 x i32> %v0, <8 x i32> %v1, <0, 4, 8, 1, 5, 9, 2, 6, 10, 3, 7, 11>
        store <12 x i32> %i.vec, <12 x i32>* %ptr
It can be transformed into a st3 intrinsic in AArch64 backend or a vst3 intrinsic in ARM backend.

Differential Revision: http://reviews.llvm.org/D10533

llvm-svn: 240751
2015-06-26 02:10:27 +00:00
Duncan P. N. Exon Smith
f3712066fc AsmPrinter: More explicitly scope iterator for MSVC
r240748 seems to be on the right path.  Be more explicit.

http://lab.llvm.org:8011/builders/clang-x64-ninja-win7/builds/1961/

llvm-svn: 240750
2015-06-26 00:53:44 +00:00
Duncan P. N. Exon Smith
6f5f78b174 AsmPrinter: Explicitly scope iterator for MSVC
Try to placate bots by explicitly scoping a conversion constructor from
`iterator` to `const_iterator`.

http://lab.llvm.org:8011/builders/sanitizer-windows/builds/5931/

llvm-svn: 240748
2015-06-26 00:41:53 +00:00
Matthias Braun
917f1e4a7f Revert "X86: Reject register operands with obvious type mismatches."
Revert until http://llvm.org/PR23955 is investigated.

This reverts commit r239309.

llvm-svn: 240746
2015-06-26 00:26:49 +00:00
Matthias Braun
9fff5d5c61 Fix mismatched architectures in test
llvm-svn: 240745
2015-06-26 00:26:46 +00:00
Matthias Braun
d4a6e1c29f aad/fix labels in test/CodeGen/X86/StackColoring.ll
llvm-svn: 240744
2015-06-26 00:26:44 +00:00
Alexey Samsonov
4c3b8a043f [ASan] Use llvm::getDISubprogram() to get function entry debug location.
It can be more robust than copying debug info from first non-alloca
instruction in the entry basic block. We use the same strategy in
coverage instrumentation.

llvm-svn: 240738
2015-06-26 00:00:47 +00:00
Duncan P. N. Exon Smith
b8e0101e11 AsmPrinter: Use an intrusively linked list for DIE::Children
Replace the `std::vector<>` for `DIE::Children` with an intrusively
linked list.  This is a strict memory improvement: it requires no
auxiliary storage, and reduces `sizeof(DIE)` by one pointer.  It also
factors out the DIE-related malloc traffic.

This drops llc memory usage from 735 MB down to 718 MB, or ~2.3%.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)

llvm-svn: 240736
2015-06-25 23:52:10 +00:00
Duncan P. N. Exon Smith
249d680189 AsmPrinter: Convert DIE::Values to a linked list
Change `DIE::Values` to a singly linked list, where each node is
allocated on a `BumpPtrAllocator`.  In order to support `push_back()`,
the list is circular, and points at the tail element instead of the
head.  I abstracted the core list logic out to `IntrusiveBackList` so
that it can be reused for `DIE::Children`, which also cares about
`push_back()`.

This drops llc memory usage from 799 MB down to 735 MB, about 8%.

(I'm looking at `llc` memory usage on `verify-uselistorder.lto.opt.bc`;
see r236629 for details.)

llvm-svn: 240733
2015-06-25 23:46:41 +00:00
Michael J. Spencer
d9fc5d4945 [ELF] Move ELF{32,64}{L,B}E typedefs to llvm.
llvm-svn: 240731
2015-06-25 23:41:23 +00:00
Michael J. Spencer
ee3a17187e [ELF] Add some accessors for lld.
llvm-svn: 240730
2015-06-25 23:40:41 +00:00
Alexey Samsonov
c200b66742 Make llvm-dwarfdump exit with non-zero exit code if error was occured.
llvm-svn: 240729
2015-06-25 23:40:15 +00:00
NAKAMURA Takumi
a5b2580063 PPCISelLowering.cpp: Appease PR23956. [-Wdocumentation]
llvm-svn: 240727
2015-06-25 23:38:44 +00:00
Adrian Prantl
f20b24ae65 Split test up into two target-spcific directories.
llvm-svn: 240726
2015-06-25 23:38:22 +00:00
Anna Zaks
faa9b1561e [asan] Do not instrument special purpose LLVM sections.
Do not instrument globals that are placed in sections containing "__llvm"
in their name.

This fixes a bug in ASan / PGO interoperability. ASan interferes with LLVM's
PGO, which places its globals into a special section, which is memcpy-ed by
the linker as a whole. When those goals are instrumented, ASan's memcpy wrapper
reports an issue.

http://reviews.llvm.org/D10541

llvm-svn: 240723
2015-06-25 23:35:48 +00:00
Anna Zaks
494d337bdd [asan] Don't run stack malloc on functions containing inline assembly.
It makes LLVM run out of registers even on 64-bit platforms. For example, the
following test case fails on darwin.

clang -cc1 -O0 -triple x86_64-apple-macosx10.10.0 -emit-obj -fsanitize=address -mstackrealign -o ~/tmp/ex.o -x c ex.c
error: inline assembly requires more registers than available

void TestInlineAssembly(const unsigned char *S, unsigned int pS, unsigned char *D, unsigned int pD, unsigned int h) {

unsigned int sr = 4, pDiffD = pD - 5;
unsigned int pDiffS = (pS << 1) - 5;
char flagSA = ((pS & 15) == 0),
flagDA = ((pD & 15) == 0);
asm volatile (
  "mov %0,  %%"PTR_REG("si")"\n"
  "mov %2,  %%"PTR_REG("cx")"\n"
  "mov %1,  %%"PTR_REG("di")"\n"
  "mov %8,  %%"PTR_REG("ax")"\n"
  :
  : "m" (S), "m" (D), "m" (pS), "m" (pDiffS), "m" (pDiffD), "m" (sr), "m" (flagSA), "m" (flagDA), "m" (h)
  : "%"PTR_REG("si"), "%"PTR_REG("di"), "%"PTR_REG("ax"), "%"PTR_REG("cx"), "%"PTR_REG("dx"), "memory"
);
}

http://reviews.llvm.org/D10719

llvm-svn: 240722
2015-06-25 23:35:45 +00:00
Adrian Prantl
4d6e5ab0b9 Debug Info: Add basic test coverage for the DWARF encoding of bitfields.
While looking at a couple of bugs in the debug info output for bitfields
I noticed that there wasn't a single regression test to test my changes
against, so here's a start.

llvm-svn: 240717
2015-06-25 23:19:19 +00:00
Matt Arsenault
f547928c2c DAGCombiner: Use pop_back_val()
llvm-svn: 240709
2015-06-25 22:15:05 +00:00
Rafael Espindola
9195b6922c Add an ELFSymbolRef type.
This allows user code to say Sym.getSize() instead of having to manually fetch
the object.

llvm-svn: 240708
2015-06-25 22:10:04 +00:00
Frederic Riss
a084fef0e8 IAS: Use the root macro instanciation for location
r224810 fixed the handling of macro debug locations in AsmParser. This patch
fixes the logic to actually do what was intended: it uses the first macro of
the macro stack instead of the last one. The updated testcase shows that the
current scheme doesn't work when macro instanciations are nested and multiple
files are used.

Reviewers: compnerd

Differential Revision: http://reviews.llvm.org/D10463

llvm-svn: 240705
2015-06-25 21:57:33 +00:00
Michael J. Spencer
3370428756 [Object][ELF] Add support for dumping dynamic relocations when sections are stripped.
llvm-svn: 240703
2015-06-25 21:47:32 +00:00
Duncan P. N. Exon Smith
5bbb9d7150 dsymutil: Split out patchStmtList(), NFC
Split out code to patch up the `DW_AT_stmt_list` for the cloned DIE, and
reorganize it so that it doesn't depend on `DIE::values_begin()` and
`DIE::values_end()` (which I'm trying to kill off).

David Blaikie and I talked about adding a range-algorithm version of
`std::find_if()`, but the assertion *still* required getting at the end
iterator.  IMO, a separate helper function with an early return is
easier to reason about here.

A follow-up commit that removes `DIE::setValue()` and mutates the
`DIEValue` directly is coming shortly.

llvm-svn: 240701
2015-06-25 21:42:46 +00:00
Sanjay Patel
9c692291d3 fix typos; NFC
llvm-svn: 240699
2015-06-25 21:11:08 +00:00
Rafael Espindola
b298fbcfdd llvm-nm: Don't print mapping symbols.
This matches the behavior of gnu nm. Fixes pr23930.

llvm-svn: 240695
2015-06-25 21:00:51 +00:00
Pete Cooper
c2ffa0891f Use foreach loop over constant operands. NFC.
A number of places had explicit loops over Constant::operands().
Just use foreach loops where possible.

llvm-svn: 240694
2015-06-25 20:51:38 +00:00
Rafael Espindola
e6fd0df168 We don't need the targets to read objects.
llvm-svn: 240684
2015-06-25 20:20:19 +00:00
Jingyue Wu
35a6e27706 [InstCombine] call SimplifyICmpInst with correct context
Summary:
Fixes PR23809. Without passing the context to SimplifyICmpInst, we would
use the assume to prove that the condition feeding the assume is
trivially true (see isValidAssumeForContext in ValueTracking.cpp),
causing the removal of the assume which may be useful for later
optimizations.

Test Plan: pr23800.ll

Reviewers: hfinkel, majnemer

Reviewed By: hfinkel

Subscribers: henryhu, llvm-commits, wengxt, broune, meheff, eliben

Differential Revision: http://reviews.llvm.org/D10695

llvm-svn: 240683
2015-06-25 20:14:47 +00:00
Rafael Espindola
c53c13d76f Diagnose undefined temporary symbols.
We already disallowed

.global .Lfoo

so this is reasonable.

This is a small cherry pick from r240130.

llvm-svn: 240681
2015-06-25 20:10:45 +00:00
Paul Robinson
45b7074442 Make this test verify .debug_pubnames is actually missing.
It was matching at EOF regardless of whether the section was present.

llvm-svn: 240679
2015-06-25 19:37:13 +00:00
Yaron Keren
dce18afe3b Rangify for loop in Inliner.cpp. NFC.
llvm-svn: 240678
2015-06-25 19:28:24 +00:00
Douglas Katzman
c6d8bcc603 Add Arg::getValues method with const 'this' and const result
llvm-svn: 240673
2015-06-25 18:48:26 +00:00