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Commit Graph

13127 Commits

Author SHA1 Message Date
Nick Lewycky
07ed4434b8 Obey the isVolatile bit on memory intrinsics when analyzing uses of a global
variable. Noticed by inspection.

Simulate memset in EvaluateFunction where the target of the memset and the
value we're setting are both the null value. Fixes PR10047!

llvm-svn: 132288
2011-05-29 18:41:56 +00:00
Rafael Espindola
9550e237a8 Use %rbp on a 64 bit test.
llvm-svn: 132279
2011-05-29 04:04:50 +00:00
Benjamin Kramer
ad67c34014 Move ARM specific test into the ARM subdir.
llvm-svn: 132255
2011-05-28 11:01:30 +00:00
Benjamin Kramer
129192d295 ConstantFoldInstOperands doesn't like compares, hand it off to instsimplify instead.
Fixes PR10040.

llvm-svn: 132254
2011-05-28 10:16:58 +00:00
John McCall
119a0222f5 Implement and document the llvm.eh.resume intrinsic, which is
transformed by the inliner into a branch to the enclosing landing pad
(when inlined through an invoke).  If not so optimized, it is lowered
DWARF EH preparation into a call to _Unwind_Resume (or _Unwind_SjLj_Resume
as appropriate).  Its chief advantage is that it takes both the
exception value and the selector value as arguments, meaning that there
is zero effort in recovering these;  however, the frontend is required
to pass these down, which is not actually particularly difficult.

Also document the behavior of landing pads a bit better, and make it
clearer that it's okay that personality functions don't always land at
landing pads.  This is just a fact of life.  Don't write optimizations that
rely on pushing things over an unwind edge.

llvm-svn: 132253
2011-05-28 07:45:59 +00:00
Bruno Cardoso Lopes
6d5e369a10 Add support for ARM ldrexd/strexd intrinsics. They both use i32 register pairs
to load/store i64 values. Since there's no current support to explicitly
declare such restrictions, implement it by using specific hardcoded register
pairs during isel.

llvm-svn: 132248
2011-05-28 04:07:29 +00:00
Eric Christopher
000dd7d0e6 Implement the 'M' output modifier for arm inline asm. This is fairly
register allocation dependent and will occasionally break. WIP in the
register allocator to model paired/etc registers.

rdar://9119939

llvm-svn: 132242
2011-05-28 01:40:44 +00:00
Chad Rosier
d0a64ab2af Add missing newlines.
llvm-svn: 132241
2011-05-28 01:35:58 +00:00
Akira Hatanaka
1590e4eab1 Define a wrapper node for target constant nodes (tglobaladdr, etc.).
Need this to prevent emitting illegal conditional move instructions. 

llvm-svn: 132240
2011-05-28 01:07:07 +00:00
Chad Rosier
fbc91cd006 Fix test cases that were previously using grep to use FileCheck
llvm-svn: 132237
2011-05-28 00:15:10 +00:00
Cameron Zwarich
cd3c1b5829 Fix the remaining atomic intrinsics to use the right register classes on Thumb2,
and add some basic tests for them.

llvm-svn: 132235
2011-05-27 23:54:00 +00:00
Bruno Cardoso Lopes
93eae0fd19 ARM asm parser wasn't able to parse a "mov" instruction while in Thumb
mode (only the "mov.w" variant). Now, when parsing "mov" in thumb mode,
default to the Thumb 1 versions/encodings.

llvm-svn: 132233
2011-05-27 23:46:09 +00:00
Eli Friedman
a64ba39381 Force a triple to make this test pass on Darwin.
llvm-svn: 132228
2011-05-27 23:12:48 +00:00
Cameron Zwarich
ded03d4e24 Add a GR32_NOREX_NOSP register class and fix a bug where getMatchingSuperRegClass()
was saying that the matching superregister class of GR32_NOREX in GR64_NOREX_NOSP
is GR64_NOREX, which drops the NOSP constraint. This fixes PR10032.

llvm-svn: 132225
2011-05-27 22:26:04 +00:00
Rafael Espindola
9ce5cebde6 Fix a regression I recently introduced by removing DwarfRegNum of
subregisters:

When a value is in a subregister, at least report the location as being
the superregister. We should extend the .td files to encode the bit
range so that we can produce a DW_OP_bit_piece.

llvm-svn: 132224
2011-05-27 22:15:01 +00:00
Rafael Espindola
2230168a0f Make size computation less brittle.
llvm-svn: 132222
2011-05-27 22:05:41 +00:00
Charles Davis
cb20ea9935 Add the suffix to the Win64 EH data sections' names if given. Add a test for
this. XFAIL'd, because the COFF AsmParser can't handle .section yet.

llvm-svn: 132220
2011-05-27 21:38:47 +00:00
Chad Rosier
336767fc2a Typo is test case
llvm-svn: 132214
2011-05-27 20:16:57 +00:00
Jakob Stoklund Olesen
516eb93107 Make room for register allocation to improve.
llvm-svn: 132213
2011-05-27 20:15:06 +00:00
Evan Cheng
0fcb465bab Don't use movw / movt for iOS static codegen for now to workaround some tools issues. rdar://9514789
llvm-svn: 132211
2011-05-27 20:11:27 +00:00
Jakob Stoklund Olesen
fb206b98bd Delete a test that is no longer relevant.
According to PR2536, the old spiller had trouble with the IMPLICIT_DEF in this
code:

  %reg1028<def> = MOV16rm %reg0, 1, %reg0, <ga:g_5>, Mem:LD(2,2) [g_5 + 0]
  %reg1039<def> = IMPLICIT_DEF
  %reg1038<def> = INSERT_SUBREG %reg1039, %reg1028, 2
  %reg1025<def> = AND32ri %reg1038, 65534, %%EFLAGS<imp-def>

However, today we emit a zero-extending load instead:

  %vreg10<def> = MOVZX32rm16 %noreg, 1, %noreg, <ga:@g_5>, %noreg; %mem:LD2[@g_5] GR32:%vreg10
  %vreg0<def> = AND32ri %vreg10, 65534, %%EFLAGS<imp-def,dead>; %GR32:%vreg0,%vreg10

This makes the test pointless since it no longer creates the spiller hazard.

llvm-svn: 132210
2011-05-27 20:02:42 +00:00
Chad Rosier
f2b2b472cc CRC32 intrinsics were renamed at revision 132163. This submission
fixes aliasing issues with the old and new names as well as adds test
cases for the auto-upgrader.
Fixes rdar 9472944.

llvm-svn: 132207
2011-05-27 19:38:10 +00:00
Evan Cheng
4192d53d1e Add iOS test
llvm-svn: 132203
2011-05-27 19:04:21 +00:00
John McCall
2f479c4d42 Fix the inliner to maintain the current de facto invoke semantics:
- the selector for the landing pad must provide all available information
    about the handlers, filters, and cleanups within that landing pad
  - calls to _Unwind_Resume must be converted to branches to the enclosing
    lpad so as to avoid re-entering the unwinder when the lpad claimed it
    was going to handle the exception in some way
This is quite specific to libUnwind-based unwinding.  In an effort to not
interfere too badly with other unwinders, and with existing hacks in frontends,
this only triggers on _Unwind_Resume (not _Unwind_Resume_or_Rethrow) and does
nothing with selectors if it cannot find a selector call for either lpad.

llvm-svn: 132200
2011-05-27 18:34:38 +00:00
Eli Friedman
55343ef7bb And fix the test in r132194.
llvm-svn: 132196
2011-05-27 18:14:28 +00:00
Eli Friedman
560532051b Fix a silly mistake (which trips over an assertion) in r132099. rdar://9515076
llvm-svn: 132194
2011-05-27 18:02:04 +00:00
Devang Patel
62a7038a9f Select DW_AT_const_value size based on variable size.
llvm-svn: 132193
2011-05-27 16:45:18 +00:00
Charles Davis
01cde4d080 Assorted fixes for Win64 EH unwind info emission:
- Flip order of bitfields. This gets our output matching GAS.
- Handle case where the end of the prolog wasn't specified.
- If the resulting unwind info struct is less than 8 bytes, pad to 8 bytes.

Add a test for the latter two.

llvm-svn: 132188
2011-05-27 15:10:25 +00:00
Benjamin Kramer
5b491b9d0e InstCombine: Make switch folding with equality compares more aggressive by trying instsimplify on the arm where we know the compared value.
Stuff like "x == y ? y : x&y" now folds into "x&y".

llvm-svn: 132185
2011-05-27 13:00:16 +00:00
Cameron Zwarich
a9c418b1c3 Fix PR10029 - VerifyCoalescing failure on patterns_dfa.c of 445.gobmk.
llvm-svn: 132181
2011-05-27 05:04:51 +00:00
Charles Davis
028e424cf3 Add a test for Win64 EH unwind information emission.
llvm-svn: 132180
2011-05-27 03:54:43 +00:00
Chad Rosier
b87c4a6945 Renamed llvm.x86.sse42.crc32 intrinsics; crc64 doesn't exist.
crc32.[8|16|32] have been renamed to .crc32.32.[8|16|32] and
crc64.[8|16|32] have been renamed to .crc32.64.[8|64].

llvm-svn: 132163
2011-05-26 23:13:19 +00:00
Devang Patel
e0b7ab9296 During branch folding avoid inserting redundant DBG_VALUE machine instructions.
llvm-svn: 132148
2011-05-26 21:47:59 +00:00
Galina Kistanova
ceabe8c579 Make few ExecutionEngine tests XFAIL for ARM, since ExecutionEngine is broken for ARM, please remove the following XFAIL when it will be fixed.
llvm-svn: 132135
2011-05-26 19:17:14 +00:00
Akira Hatanaka
5bfbea9ef2 Add support for C++ exception handling.
llvm-svn: 132131
2011-05-26 18:59:03 +00:00
Eli Friedman
15dc009422 Fix test on Windows.
llvm-svn: 132126
2011-05-26 18:00:32 +00:00
Charles Davis
cf332d9ff7 Add a test for the chained directives that I forgot last time.
llvm-svn: 132110
2011-05-26 05:17:43 +00:00
Stuart Hastings
837a958ff6 Reverting 132105: it broke some LLVM-GCC DejaGNU tests.
llvm-svn: 132108
2011-05-26 04:09:49 +00:00
Charles Davis
0021487a8e Test .seh_startchained and .seh_endchained parsing.
Rework how the MCWin64EHUnwindInfo instances are stored. Fix issues with
chained unwind areas exposed by the test that were related to this.

The ChainedParent field had the wrong address, because when the chained unwind
info was added, the addresses shifted around. Now we store the pointers to the
structures, which are now allocated from the MC heap.

llvm-svn: 132106
2011-05-26 02:45:47 +00:00
Stuart Hastings
e704bfb21e Correctly handle a one-word struct passed byval on x86_64.
rdar://problem/6920088

llvm-svn: 132105
2011-05-26 02:44:56 +00:00
Andrew Trick
0577c5768b indvars: incremental fixes for -disable-iv-rewrite and testcases.
Use a proper worklist for use-def traversal without holding onto an
iterator. Now that we process all IV uses, we need complete logic for
resusing existing derived IV defs. See HoistStep.

llvm-svn: 132103
2011-05-26 00:46:11 +00:00
Eli Friedman
93ffb875ad Rewrite fast-isel integer cast handling to handle more cases, and to be simpler and more consistent.
The practical effects here are that x86-64 fast-isel can now handle trunc from i8 to i1, and ARM fast-isel can handle many more constructs involving integers narrower than 32 bits (including loads, stores, and many integer casts).

rdar://9437928 .

llvm-svn: 132099
2011-05-25 23:49:02 +00:00
Akira Hatanaka
3f49cbeb37 Define WeakRefDirective.
llvm-svn: 132098
2011-05-25 23:30:30 +00:00
Eli Friedman
5cd755549b PR9998: ashr exact %x, 31 is not equivalent to sdiv exact %x, -2147483648.
llvm-svn: 132097
2011-05-25 23:26:20 +00:00
Charles Davis
ede0f07dae Add tests for .seh_setframe and .seh_handlerdata parsing. Fix issues with
them.

I had to add a special SwitchSectionNoChange method to MCStreamer just for
.seh_handlerdata. If this isn't OK, please let me know, and I'll find some
other way to fix .seh_handlerdata streaming.

llvm-svn: 132084
2011-05-25 21:43:45 +00:00
Eric Christopher
807da21e47 Implement the 'm' modifier. Note that it only works for memory operands.
Part of rdar://9119939

llvm-svn: 132081
2011-05-25 20:51:58 +00:00
Akira Hatanaka
32b5043265 Custom-lower FCOPYSIGN nodes.
llvm-svn: 132074
2011-05-25 19:32:07 +00:00
Charles Davis
6b67ee5130 Add tests for .seh_savereg and .seh_savexmm parsing. Once again, fix the
buggy methods that parse these directives.

llvm-svn: 132045
2011-05-25 04:51:25 +00:00
Cameron Zwarich
beae5f20e8 Make tTAILJMPr/tTAILJMPrND emit a tBX without a preceding MOV of PC to LR. This
fixes <rdar://problem/9495913>

llvm-svn: 132042
2011-05-25 04:45:27 +00:00
Andrew Trick
0aa40b2f8f indvars: fixed IV cloning in -disable-iv-rewrite mode with associated
cleanup and overdue test cases.

llvm-svn: 132038
2011-05-25 04:42:22 +00:00