Bob Wilson
9482015a0a
Rename ARM "lane_cst" operands to "nohash_imm" since they are used for
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several things other than Neon vector lane numbers. For inline assembly
operands with a "c" print code, check that they really are immediates.
llvm-svn: 79676
2009-08-21 21:58:55 +00:00
Evan Cheng
86546fb692
Fix an obvious copy-n-paste bug.
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llvm-svn: 79535
2009-08-20 17:01:04 +00:00
David Goodwin
d57f44783c
Update Cortex-A8 instruction itineraries for integer instructions.
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llvm-svn: 79436
2009-08-19 18:00:44 +00:00
Evan Cheng
d4d2a3d0a6
Fix revsh pattern.
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llvm-svn: 79318
2009-08-18 05:43:23 +00:00
Evan Cheng
7d8caa143b
Also shrink immediate branches; also more assembler workarounds.
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llvm-svn: 79014
2009-08-14 18:31:44 +00:00
Evan Cheng
45d6a21e21
Shrink ADR and LDR from constantpool late during constantpool island pass.
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llvm-svn: 78970
2009-08-14 00:32:16 +00:00
David Goodwin
dd797db6bd
Finalize itineraries for cortex-a8 integer multiply
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llvm-svn: 78908
2009-08-13 15:51:13 +00:00
David Goodwin
90e7f9873c
Enhance the InstrStage object to enable the specification of an Itinerary with overlapping stages. The default is to maintain the current behavior that the "next" stage immediately follows the previous one.
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llvm-svn: 78827
2009-08-12 18:31:53 +00:00
Evan Cheng
c369ccbe83
Shrink Thumb2 movcc instructions.
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llvm-svn: 78790
2009-08-12 05:17:19 +00:00
Evan Cheng
410447e028
80 col violation.
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llvm-svn: 78778
2009-08-12 02:03:03 +00:00
Evan Cheng
a29ee9f509
Shrinkify Thumb2 r = add sp, imm.
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llvm-svn: 78745
2009-08-11 23:00:31 +00:00
Evan Cheng
783028063e
Shrinkify Thumb2 load / store multiple instructions.
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llvm-svn: 78717
2009-08-11 21:11:32 +00:00
Owen Anderson
48f2f0ae72
Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
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the latter is capable of representing either a primitive or an extended type.
llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Owen Anderson
b4bce99769
Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
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llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Evan Cheng
ad380aa97a
Add support to reduce most of 32-bit Thumb2 arithmetic instructions.
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llvm-svn: 78550
2009-08-10 02:37:24 +00:00
Anton Korobeynikov
44fa9f179c
Use subclassing to print lane-like immediates (w/o hash) eliminating
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'no_hash' modifier. Hopefully this will make Daniel happy :)
llvm-svn: 78514
2009-08-08 23:10:41 +00:00
Evan Cheng
fb833354b6
tADDhirr should target GPR, not tGPR.
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llvm-svn: 78454
2009-08-08 03:19:44 +00:00
Evan Cheng
5af3c8154b
tBfar is bl, which clobbers LR.
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llvm-svn: 78370
2009-08-07 05:45:07 +00:00
Evan Cheng
48b49cf5b9
It turns out most of the thumb2 instructions are not allowed to touch SP. The semantics of such instructions are unpredictable. We have just been lucky that tests have been passing.
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This patch takes pain to ensure all the PEI lowering code does the right thing when lowering frame indices, insert code to manipulate stack pointers, etc. It's also custom lowering dynamic stack alloc into pseudo instructions so we can insert the right instructions at scheduling time.
This fixes PR4659 and PR4682.
llvm-svn: 78361
2009-08-07 00:34:42 +00:00
David Goodwin
3aafcc1dd2
Add parameter to pattern classes to enable an itinerary to be specified for instructions. For now just use the existing itineraries or NoItinerary.
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llvm-svn: 78321
2009-08-06 16:52:47 +00:00
Evan Cheng
e366789b50
Fix part 1 of pr4682. PICADD is a 16-bit instruction even in thumb2 mode.
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llvm-svn: 78126
2009-08-04 23:47:55 +00:00
Evan Cheng
5ef6928dff
Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the same
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instructions for calls since BL and BLX are always 32-bit long and BX is always
16-bit long.
Also, we should be using BLX to call external function stubs.
llvm-svn: 77756
2009-08-01 00:16:10 +00:00
Evan Cheng
90a1ca6e17
Make sure Thumb2 uses the right call instructions.
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llvm-svn: 77507
2009-07-29 21:26:42 +00:00
Evan Cheng
c8d3891c87
- Fix an obvious copy and paste error.
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- Darwin Thumb2 call clobbers r9.
llvm-svn: 77500
2009-07-29 20:10:36 +00:00
Evan Cheng
cf483eb0c0
In thumb2 mode, add pc is unpredictable. Use add + mov pc instead (that is until more optimization goes in).
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llvm-svn: 77364
2009-07-28 20:53:24 +00:00
David Goodwin
6ff3fd8021
Remove TPat. No patterns depend on just isThumb(). Must use either T1Pat (isThumb1Only()) or T2Pat (is Thumb2).
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llvm-svn: 77242
2009-07-27 19:59:26 +00:00
Evan Cheng
a6737e21cf
Rename tMOVhi2lor to tMOVgpr2tgpr. It's not moving from a high register to a low register. It's moving from a GPR register class to a more restrictive tGPR class. Also change tMOVlor2hir, and tMOVhir2hir.
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llvm-svn: 77172
2009-07-26 23:59:01 +00:00
Evan Cheng
8997f6bfc1
Since we have moved unified assembly, switch to ADR instruction instead of a the difficult-to-read .set + add syntax to materialize pc-relative address.
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Turns out this also fixed a poor code selection on Thumb1. I have no idea why we were using a mov + add to do the same thing as ADR before.
llvm-svn: 76889
2009-07-23 18:26:03 +00:00
Evan Cheng
4a77f28c47
Use getTargetConstant instead of getConstant since it's meant as an constant operand.
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llvm-svn: 76803
2009-07-22 22:03:29 +00:00
Evan Cheng
34576850e1
Don't forget D16 - D31 are clobbered by calls and sjlj eh.
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llvm-svn: 76729
2009-07-22 06:46:53 +00:00
Evan Cheng
4fdb43a89d
Add R12 to the list of registers clobbered by 16-bit Thumb calls as a pre-caution. r12 could be live once we have mixed 32-bit and 16-bit instructions.
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llvm-svn: 76728
2009-07-22 06:37:28 +00:00
Evan Cheng
192fc19379
Do not select tSXTB / tSXTH in thumb2 mode.
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llvm-svn: 76600
2009-07-21 18:15:26 +00:00
Evan Cheng
490d2cc5a4
Fix tSUBspi operand definition. It reads and writes sp, which is a high register.
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llvm-svn: 76155
2009-07-17 05:43:12 +00:00
Evan Cheng
b8666f7abc
1. In Thumb mode, select tBx instead of ARM variants.
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2. BX does not "use" the link register, it defines it.
3. Fix a couple more places in thumb td file that still uses pre-UAL syntax.
llvm-svn: 75585
2009-07-14 01:49:27 +00:00
Evan Cheng
03d981d91b
Smarter isel of ldrsb / ldrsh. Only make use of these when [r,r] address is feasible.
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llvm-svn: 75360
2009-07-11 07:08:13 +00:00
Evan Cheng
268b47b1fb
Major changes to Thumb (not Thumb2). Many 16-bit instructions either modifies CPSR when they are outside the IT blocks, or they can predicated when in Thumb2. Move the implicit def of CPSR to an optional def which defaults CPSR. This allows the 's' bit to be toggled dynamically.
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A side-effect of this change is asm printer is now using unified assembly. There are some minor clean ups and fixes as well.
llvm-svn: 75359
2009-07-11 06:43:01 +00:00
Evan Cheng
74f5327e53
We don't need separate thumb1 instructions tADDSi3 etc. for addc and subc. The "normal" version always modify condition register CPSR so we should just use def : pat to match to the same instructions.
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llvm-svn: 75219
2009-07-10 02:09:04 +00:00
Evan Cheng
24f2aefc87
Add a thumb2 pass to insert IT blocks.
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llvm-svn: 75218
2009-07-10 01:54:42 +00:00
Evan Cheng
1b15e9611e
Added Thumb IT instruction.
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llvm-svn: 75198
2009-07-09 23:43:36 +00:00
David Goodwin
49fbd8d6b7
Use common code for both ARM and Thumb-2 instruction and register info.
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llvm-svn: 75067
2009-07-08 23:10:31 +00:00
David Goodwin
5bdef4b3f7
Checkpoint Thumb2 Instr info work. Generalized base code so that it can be shared between ARM and Thumb2. Not yet activated because register information must be generalized first.
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llvm-svn: 75010
2009-07-08 16:09:28 +00:00
David Goodwin
5545d82866
Add conditional and unconditional thumb-2 branch. Add thumb-2 jump table.
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llvm-svn: 74543
2009-06-30 18:04:13 +00:00
Evan Cheng
2a527c3419
A few more load instructions.
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llvm-svn: 74500
2009-06-30 02:15:48 +00:00
David Goodwin
9e1280adf3
Rename ARMcmpNZ to ARMcmpZ and use it to represent comparisons that set only the Z flag (i.e. eq and ne). Make ARMcmpZ commutative.
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llvm-svn: 74423
2009-06-29 15:33:01 +00:00
Evan Cheng
093adf3ff9
Implement Thumb2 ldr.
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After much back and forth, I decided to deviate from ARM design and split LDR into 4 instructions (r + imm12, r + imm8, r + r << imm12, constantpool). The advantage of this is 1) it follows the latest ARM technical manual, and 2) makes it easier to reduce the width of the instruction later. The down side is this creates more inconsistency between the two sub-targets. We should split ARM LDR instruction in a similar fashion later. I've added a README entry for this.
llvm-svn: 74420
2009-06-29 07:51:04 +00:00
Evan Cheng
817712377a
Renaming for consistency.
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llvm-svn: 74368
2009-06-27 02:26:13 +00:00
Evan Cheng
e45355b804
tst is also commutable.
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llvm-svn: 74236
2009-06-26 00:19:07 +00:00
David Goodwin
a0ed5f6847
Add Def/Use of CPSR for Thumb-1 instructions.
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llvm-svn: 74219
2009-06-25 22:49:55 +00:00
David Goodwin
c72bad36d7
Test commit
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llvm-svn: 74185
2009-06-25 17:52:32 +00:00
Evan Cheng
8e61610960
Some reorg and additional comments.
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llvm-svn: 74152
2009-06-25 01:05:06 +00:00